ElphelWiki - User contributions [en]

Talk:Porting Theora to 353 cameras

2008-05-22T14:07:30Z

JeremViewsurf:

Ok, I started a new page on the Theora project in 353 cameras. I started with a global approach and a list of modules that need to be changed or replaced on the 353 model. Feel free to correct me or add suggestions as I'm not (yet...) an expert on Elphel cameras. I think the first step is to make an exhaustive list of the hardware blocks that need modifications and then detail what need to be done in each block. --[[User:JeremViewsurf|JeremViewsurf]] 03:48, 19 February 2008 (CST)

As I understand your first need is not a streaming but producing a small video clip to be uploaded via FTP. This can be done more easy with minimal non FPGA modifications.

We will probably create a CVS branch for your port, to be able to test it we need to compile a standard 7.1.x firmware disabling everything sensor or FPGA related and change the FPGA bitstream. --[[User:Polto|Alexandre.Poltorak]] 07:53, 19 February 2008 (CST)

You mean that it should be possible that the system can handle software Ogg Theora encoding for a non real-time application such as producing small video clips ? I'm aware that it depends on the output resolution, framerate and length of the clip but does a 1 min 1024x768 @ 25fps clip for example can be processed in a reasonable delay ? I'll discuss with Viewsurf's development team in order to obtain more precise specs concerning video output (in terms of length, resolution, framerate and encoding delay acceptable) but if you can give me an idea of what the software part can handle, I would consider spending more time in soft Theora transcoding instead of FPGA design. --[[User:JeremViewsurf|JeremViewsurf]] 03:37, 20 February 2008 (CST)

No, sorry i was not speaking of transcoding. It would take too much calculation power and is not possible on the camera's CPU. The Theora encoding should be done in FPGA. What i was speaking about is the software part.. I think you do not need a streamer for the first steps. You only need to generate a clip in the FPGA memory, and upload it to a FTP. --[[User:Polto|Alexandre.Poltorak]] 08:32, 20 February 2008 (CST)

----

Some questions concerning changes in the FPGA :
* Is it necessary to keep histogram and timestamp blocks in a design which supports Theora only ?
** I believe the camera will be rather crippled w/o those features--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
* Is it possible to keep channel 0, 1 and 3 design without changes in the memory controller ?
** Theora implementation used different (more advanced) memory controller that the JPEG, it was getting 95% efficiency at Theora data structure, so you need Theora memory controller. But if you mean by "Channel 0 design" the gamma tables and histograms - yes, they probably could be ported (with some changes, of course). As for channels 1 and 3 - similar are available in Theora 333 also--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
* The 353 design uses 2 DMA fifos between the compressor and the system interface instead of one in the 333 design. Is it possible to keep only one 333 DMA fifo in the final design ?
** Yes, of course - but this is so minor difference. The more important is that in Theora that FIFO could make the compressor wait if ETRAX DMA is not ready - at the beginning of the frame in theora there is a data "burst".--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
* In the 353 design, all signals and blocks I/O concerning 90° phase clock are commented. Is it possible to uncomment them in order to restore the clock ?
** Maybe yes, more likely no. 353 and 333 use different FPGAs.--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
* Motion compensation seems not to be implemented in the Theora compressor yet. Is it possible to add this feature later in the compressor block without major changes in the final design ?
** No, I'm afraid that is not possible - I believe we need faster FPGA for that and likely faster/wider memory.--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
--[[User:JeremViewsurf|JeremViewsurf]] 02:43, 25 February 2008 (CST)

----

I'm currently working on the FPGA control register and I have a question concerning the I2C pads controlled by the control register (via dcr[16:21]). In the 333 design there are 2 I2C "channels" : (sda0,scl0) and (sda1,scl1) and only one on the 353 design. Is it possible to keep a single i2c channel on the new design ? In other ways, what is the purpose of the i2c "channels" in each device ? --[[User:JeremViewsurf|JeremViewsurf]] 03:19, 3 March 2008 (CST)

The later 353 software also has 2 I2C channels, similar to 333. One channel is designed to communicate to the sensor (and goes through 30-pin flex cable), the other - to additional boards that sit on top of the 353, that I2C bus uses 2 bits (0,1) of the 12-bit GPIO of the 353 FPGA. It is currently used by multiple I2C peripherals on teh 10369 board (IDE bus configuration, clock/calendar, temperature sensor/fan control, EEPROM, USB hub configuration --[[User:Andrey.filippov|Andrey.filippov]] 12:27, 5 March 2008 (CST)

----

I tried to implement the new design according to the specs I proposed on this article. I instantiated the Theora compressor and the 8-channel memory controller in the place of the former jpeg compressor and memory controller and adapted registers and addresses (see article). The synthesis of this design with ISE is completed without error but I expect more issues with the place & route procedure. It would be great if I could share this work on a CVS to have some critics and some support, we had a discussion about that with Alexandre but I'm still waiting for an account. Before going farther, I'm trying to run the simulation with Icarus but I'm experiencing some issues with the compilation :

channel0.v:154: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+('sd1)
channel1.v:152: error: operand of concatenation has indefinite width: (ntile_x[3:0])+('sd1)
channel1.v:155: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+('sd1)

I would appreciate some support concerning how to test and debug the new design since this seems to be a tough issue to deal with.

When simulating Theora I used Silos III simulator on Windows, some work is needed to make it work with Icarus. First step - patch Xilinx unisim library, then - go through code (maybe it needs width for sd1?. The other problem that will come out - in Silos tasks were reenterable, each instance having it's own set of local variables (I used it when simulating CPU interrupts), in Icarus - they all share the same.--[[User:Andrey.filippov|Andrey.filippov]] 12:27, 5 March 2008 (CST)
--[[User:JeremViewsurf|JeremViewsurf]] 08:57, 5 March 2008 (CST)

I fixed the previous compilation error in Icarus, in channel0.v and channel1.v replace
channel0.v:154: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+1
channel1.v:152: error: operand of concatenation has indefinite width: (ntile_x[3:0])+1
channel1.v:155: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+1

with

channel0.v:154: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+11'h1
channel1.v:152: error: operand of concatenation has indefinite width: (ntile_x[3:0])+4'h1
channel1.v:155: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+11'h1

I can finally visualize some chronograms in gtkwave however I'm using the old 353 testbench... Time to understand how the testbench is structured and to think about a smarter one to test the new design. --[[User:JeremViewsurf|JeremViewsurf]] 03:13, 6 March 2008 (CST)

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I'm working on the simulation of the 333 Theora design (x333t.tf) and it looks like there are three simulation modes for this design that can be switched with 'define : MASTERMODE, MASTERMODE1,SINGLE_ST. What is the difference between these modes and how does each work in summary ? --[[User:JeremViewsurf|JeremViewsurf]] 10:45, 10 March 2008 (CDT)

The source code is now available on the Elphel CVS : [http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ | http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/]. The synthesis of this code is OK but it still have to be tested. I split the testbench between the main simulation sequence and the different tasks. The x353_sim.sh script is up to date but the simulation itself (x353_1.tf) is inadequate to test the design (it is still the old MJPEG testbench). The testbench in the 6.3.9 firmware (333 Theora) seems to fit better but I still need to know how it works precisely in order to adapt it to the 353 design. --[[User:JeremViewsurf|JeremViewsurf]] 09:22, 11 March 2008 (CDT)

----

Some news concerning the simulation of Theora on the 353 :
* I instantiated the x353t module with the sensor and the sdram.
* I'm trying to go through the initialization sequence
* The global initialization works (with glbl.v)
* The DCM reset works (SDRAM clocks SDCLK_D and SDNCLK_D are working)
* I didn't check if the tables programmation is ok yet
* The sdram initialization sequence works :

Initialize SDRAM

>> 214455.000 ns >> cpu_wr(21, 00017fff)
At time 214556.000 ns PRE : Addr[10] = 1, Bank = 11

>> 214605.000 ns >> cpu_wr(21, 00002002)
At time 214708.000 ns EMR : Extended Mode Register
At time 214708.000 ns EMR : Enable DLL

>> 214755.000 ns >> cpu_wr(21, 00000163)
At time 214860.000 ns LMR : Load Mode Register
At time 214860.000 ns LMR : Burst Length = 8
At time 214860.000 ns LMR : CAS Latency = 2.5

>> 214905.000 ns >> cpu_wr(21, 00017fff)
At time 215004.000 ns PRE : Addr[10] = 1, Bank = 11

>> 215055.000 ns >> cpu_wr(21, 00008000)
At time 215156.000 ns AREF : Auto Refresh

>> 215205.000 ns >> cpu_wr(21, 00008000)
At time 215308.000 ns AREF : Auto Refresh
testbench353t.i_mt46v16m16fg: at time 215308.000 ns MEMORY: Power Up and Initialization Sequence is complete

>> 215355.000 ns >> cpu_wr(21, 00000063)
At time 215460.000 ns LMR : Load Mode Register
At time 215460.000 ns LMR : Burst Length = 8
At time 215460.000 ns LMR : CAS Latency = 2.5

Initialize SDRAM done

I committed the changes to the CVS. --[[User:JeremViewsurf|JeremViewsurf]] 05:20, 19 March 2008 (CDT)

I checked the table programming (quantization, huffman, etc), the procedure seems ok. I finally have data output on the SDA and SDD ports after having replace the sensorpix and sensortrig blocks in the 353 with those that were in the 333 Theora (with some modifications in the width of some signals). However, the timings seems completely different between the two sensors and I experience memory overflow during the simulation :

...
At time 1498748.000 ns WRITE: Bank = 3, Row = 0034, Col = 06d, Data = 0000
At time 1498748.000 ns ERROR: Memory overflow.
Write to Address 180d06d with Data 0000 will be lost.
You must increase the part_mem_bits parameter or define FULL_MEM.
At time 1498748.000 ns WRITE: Bank = 3, Col = 070
At time 1498752.000 ns WRITE: Bank = 3, Row = 0034, Col = 06e, Data = 0000
At time 1498752.000 ns ERROR: Memory overflow.
Write to Address 180d06e with Data 0000 will be lost.
You must increase the part_mem_bits parameter or define FULL_MEM.
...

--[[User:JeremViewsurf|JeremViewsurf]] 11:46, 26 March 2008 (CDT)

Have you tried to increase "part_mem_bits"? It's in ddr_parameters.v
--[[User:Oleg|Oleg]] 20:06, 26 March 2008 (CDT)

I defined FULL_MEM in ddr.v to be sure, there is no more memory overflow error. However is the simulation still representative of reality ? --[[User:JeremViewsurf|JeremViewsurf]] 03:32, 27 March 2008 (CDT)

----

I have a question concerning the sensor in both 333 and 353 design. In the 333 the sensor has a 10 bit output that goes directly to the sensorpix module (through sensorpads) to a 10 bit input. However In the 353, the sensor has a 12 bit output that goes to the sensorpads module and is treated to produce a 16 bit output that goes to the sensorpix module. What is the purpose of the extra bits in the 353 design ? Is it possible to extract a 10 bit output from the 353 sensorpad module to feed a 333 sensorpix block ? It looks like that the higher 10 bits of the ipxd[15:0] signal are different from the lower 6 bits (the latter can be forced to 0 with the cnven signal). Are these 10 bits similar to the 10 bits output of the 333 sensor ?

'''sensorpads353.v'''
...
ipxd_pre[ 5:0] <= cnven?6'b0:{ipxded[3:2],pxd14?ipxded[1:0]:2'h0,2'h0};
ipxd_pre[15:6] <= ipxded[15:6];
ipxd[15:0] <= ipxd_pre[15:0];
...

--[[User:JeremViewsurf|JeremViewsurf]] 03:37, 31 March 2008 (CDT)

The 5MPix sensor does have 12 bit output and all the bits are used during "gamma"-table conversion to 8 bits. Even more - the same FPGA code now supports 10347 boards (for Kodak KAI-11002/16000 CCD sensors) that produce 14-bit data.

After the data (10-12-14 bits) reaches the FPGA, it can go two ways - through the LUT (with linear interpolation) conversion to 8 bits and raw - 2 bytes/pixel format, where pixel data is MSB-aligned (actually bit 14 being the highest, bit 15 is left 0 to allow subtraction without overflow). I believe you should use that part (from the sensor interface to the SDRAM - including gamma tables and histograms) the same for Theora as it is now in 353 (for JPEG)--[[User:Andrey.filippov|Andrey.filippov]] 12:09, 31 March 2008 (CDT)

----

I restored the sensorpix353 and sensortrig353 in the Theora design and tested the data path from the sensor to the dma output. Looks like there is no data coming out of the mcontr channel 7 (after the token read buffer). Same issue with the 333 Theora simulation although the design is obviously correct. This might be a flaw in the testbench (?) as I used somehow the same for the two designs. Moreover I can't simulated over 2ms and I can't figure out why the simulations stops at that time. Maybe the second stage of the compressor processes data after 2 ms so it is never reached by the simulator (?)

[[Image:Datapath.jpg]]

--[[User:JeremViewsurf|JeremViewsurf]] 05:17, 7 April 2008 (CDT)

"simulation over 2ms" - $stop in line 639 of x353t.tf finishes the simulation. And there's one file is missing in cvs - linear1028rgb.dat - Jeremy, could you upload it.--[[User:Oleg|Oleg]] 11:44, 8 April 2008 (CDT)

The missing file is now on the cvs, let me know if something else is missing. If you want to check the set of signals in my simulation above, use pxdpath.sav in gtkwave. Before $stop in line 639 of x353t.tf there is now a 5ms delay (#5000000) to let the simulation run, it stops at 700µs... --[[User:JeremViewsurf|JeremViewsurf]] 02:24, 9 April 2008 (CDT)

I needed to copy 'defines333.vh' and '*.dat's from theora/ folder.--[[User:Oleg|Oleg]] 03:59, 10 April 2008 (CDT)

I'm now trying with a 5 ms delay and without $stop after the delay, the simulation is currently at 2.3 ms and is still running ! I looked at the waves, still no output after ch7 (after mcontr_tok_rd to be more precise). --[[User:JeremViewsurf|JeremViewsurf]] 03:44, 9 April 2008 (CDT)

----

At last, I have some output after the memory controller channel 7 after 5h30 of simulation... Basically it seems that a whole frame have to be processed before having any output. Maybe changing nstx and nsty (number of blocks in a row and rows in a frame) parameters would reduce simulation time.

[[Image:Finaldatapath.jpg]]

--[[User:JeremViewsurf|JeremViewsurf]] 07:53, 11 April 2008 (CDT)

Jeremy, what frame size do you try to simulate ? You should try on a minimal: 32x128. Look on the 333 Theora testbench for more info. --[[User:Polto|Alexandre.Poltorak]] 14:28, 11 April 2008 (CDT)

I realized that I did not check the frame dimensions and I tried to simulate 1280x1024 frames (init_dimensions(9,7)). I changed to init_dimensions(1,1) thus setting nstx and nsty to 1. I now have output on ch7 after 2 ms, thanks. --[[User:JeremViewsurf|JeremViewsurf]] 04:07, 14 April 2008 (CDT)

----

I carried out the synthesis of the design with ISE, I am able to get the .bit file with some warnings (old constraints file from 353 : some timings not met, some clocks warnings and obviously unused signals) but no error. I started to have a look at the driver and made a first version of the definition file x3x3.h (see CVS). Some macros at the end may be obsolete as they command the 353 memory controller. --[[User:JeremViewsurf|JeremViewsurf]] 08:32, 17 April 2008 (CDT)

Problem while compiling with definition file x3x3.h :
Making install in packages/os/linux-2.6 for crisv32-axis-linux-gnu
make[2]: entrant dans le répertoire « /home/larrey/Elphel/353t_clean/elphel353-7.1.7.11/elphel353t/packages/os/linux-2.6-R1_4_2 »
subdirs=
MAKE /home/larrey/Elphel/353t_clean/elphel353-7.1.7.11/elphel353t/os/linux-2.6 zImage
make[3]: entrant dans le répertoire « /home/larrey/Elphel/353t_clean/elphel353-7.1.7.11/elphel353t/os/linux-2.6-tag--devboard-R2_10-4 »
CHK include/linux/version.h
CHK include/linux/utsrelease.h
CHK include/linux/compile.h
CC arch/cris/arch-v32/drivers/elphel/fpgajtag.o
In file included from arch/cris/arch-v32/drivers/elphel/fpgajtag.c:95:
arch/cris/arch-v32/drivers/elphel/x3x3.h:963:45: "[" may not appear in macro parameter list
make[5]: *** [arch/cris/arch-v32/drivers/elphel/fpgajtag.o] Erreur 1

At the first occurrence of #include "x3x3.h" some 353 macros such as #define X313_IRQSTATE(port_csp0_addr[0x11],port_csp0_addr[0x11]) with the "[" character stops the compilation. --[[User:JeremViewsurf|JeremViewsurf]] 10:48, 21 April 2008 (CDT)

Strange. Could you pls use LANG=CC ? So others will be able to read error messages too :) What GNU/Linux distribution do you use ? what version of gcc-cris? Also it would be better to sync to last CVS, many bugs was resolved since .11. --[[User:Polto|Alexandre.Poltorak]] 12:45, 21 April 2008 (CDT)
In the http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/os/linux-2.6-tag--devboard-R2_10-4/arch/cris/arch-v32/drivers/elphel/x353.h?view=markup
1053: #define X313_IRQSTATE (port_csp0_addr[0x11],port_csp0_addr[0x11])
there is a space between "X313_IRQSTATE" and "(" separating macro name with 0 parameters and the macro body. Where could that space character disappear in your example?--[[User:Andrey.filippov|Andrey.filippov]] 14:22, 21 April 2008 (CDT)

Andrey is right, that was just a stupid space problem... By the way, I'll get the latest version of the source code as I'm working on the driver (well just trying to understand how is it structured right now...). Thanks for the quick answer. --[[User:JeremViewsurf|JeremViewsurf]] 02:17, 22 April 2008 (CDT)

----

Working on the driver made me realize that the compressor never reached the end of a frame... The compressor just stopped processing data after a while and a bunch of signal switched to an undetermined state. I was working on this issue and realized that I got a problem with clock phases and data was written to wrong locations in the sdram. Now it looks like it's fixed, I don't have undetermined signals anymore and the done_compress signal goes high after a frame is processed. Fixed files have been committed.

I am now dealing with interrupts and I can't make the IRQ signal go high when done_compress is high like the 333 design. In the 333 design there's a simple interrupt manager that let the irq go through according to a certain mask value. However I don't understand how the 353 interrupt vector block works... At that time I just plugged the interrupt sources (done_compress, reset_compress etc) in the irq_in input but obviously I think there are more to do to make that work. --[[User:JeremViewsurf|JeremViewsurf]] 03:32, 22 May 2008 (CDT)

By the way, I tried to use the old 333 interrupts manager block with the new design and it seems to work with the simulation (IRQ goes high for some time when the frame is done processing). However I'm stuck with how to modify the device driver with this design, (R_IRQ_MASK0_SET used but undeclared). --[[User:JeremViewsurf|JeremViewsurf]] 09:07, 22 May 2008 (CDT)

Talk:Porting Theora to 353 cameras

2008-05-22T08:32:03Z

JeremViewsurf:

Ok, I started a new page on the Theora project in 353 cameras. I started with a global approach and a list of modules that need to be changed or replaced on the 353 model. Feel free to correct me or add suggestions as I'm not (yet...) an expert on Elphel cameras. I think the first step is to make an exhaustive list of the hardware blocks that need modifications and then detail what need to be done in each block. --[[User:JeremViewsurf|JeremViewsurf]] 03:48, 19 February 2008 (CST)

As I understand your first need is not a streaming but producing a small video clip to be uploaded via FTP. This can be done more easy with minimal non FPGA modifications.

We will probably create a CVS branch for your port, to be able to test it we need to compile a standard 7.1.x firmware disabling everything sensor or FPGA related and change the FPGA bitstream. --[[User:Polto|Alexandre.Poltorak]] 07:53, 19 February 2008 (CST)

You mean that it should be possible that the system can handle software Ogg Theora encoding for a non real-time application such as producing small video clips ? I'm aware that it depends on the output resolution, framerate and length of the clip but does a 1 min 1024x768 @ 25fps clip for example can be processed in a reasonable delay ? I'll discuss with Viewsurf's development team in order to obtain more precise specs concerning video output (in terms of length, resolution, framerate and encoding delay acceptable) but if you can give me an idea of what the software part can handle, I would consider spending more time in soft Theora transcoding instead of FPGA design. --[[User:JeremViewsurf|JeremViewsurf]] 03:37, 20 February 2008 (CST)

No, sorry i was not speaking of transcoding. It would take too much calculation power and is not possible on the camera's CPU. The Theora encoding should be done in FPGA. What i was speaking about is the software part.. I think you do not need a streamer for the first steps. You only need to generate a clip in the FPGA memory, and upload it to a FTP. --[[User:Polto|Alexandre.Poltorak]] 08:32, 20 February 2008 (CST)

----

Some questions concerning changes in the FPGA :
* Is it necessary to keep histogram and timestamp blocks in a design which supports Theora only ?
** I believe the camera will be rather crippled w/o those features--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
* Is it possible to keep channel 0, 1 and 3 design without changes in the memory controller ?
** Theora implementation used different (more advanced) memory controller that the JPEG, it was getting 95% efficiency at Theora data structure, so you need Theora memory controller. But if you mean by "Channel 0 design" the gamma tables and histograms - yes, they probably could be ported (with some changes, of course). As for channels 1 and 3 - similar are available in Theora 333 also--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
* The 353 design uses 2 DMA fifos between the compressor and the system interface instead of one in the 333 design. Is it possible to keep only one 333 DMA fifo in the final design ?
** Yes, of course - but this is so minor difference. The more important is that in Theora that FIFO could make the compressor wait if ETRAX DMA is not ready - at the beginning of the frame in theora there is a data "burst".--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
* In the 353 design, all signals and blocks I/O concerning 90° phase clock are commented. Is it possible to uncomment them in order to restore the clock ?
** Maybe yes, more likely no. 353 and 333 use different FPGAs.--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
* Motion compensation seems not to be implemented in the Theora compressor yet. Is it possible to add this feature later in the compressor block without major changes in the final design ?
** No, I'm afraid that is not possible - I believe we need faster FPGA for that and likely faster/wider memory.--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
--[[User:JeremViewsurf|JeremViewsurf]] 02:43, 25 February 2008 (CST)

----

I'm currently working on the FPGA control register and I have a question concerning the I2C pads controlled by the control register (via dcr[16:21]). In the 333 design there are 2 I2C "channels" : (sda0,scl0) and (sda1,scl1) and only one on the 353 design. Is it possible to keep a single i2c channel on the new design ? In other ways, what is the purpose of the i2c "channels" in each device ? --[[User:JeremViewsurf|JeremViewsurf]] 03:19, 3 March 2008 (CST)

The later 353 software also has 2 I2C channels, similar to 333. One channel is designed to communicate to the sensor (and goes through 30-pin flex cable), the other - to additional boards that sit on top of the 353, that I2C bus uses 2 bits (0,1) of the 12-bit GPIO of the 353 FPGA. It is currently used by multiple I2C peripherals on teh 10369 board (IDE bus configuration, clock/calendar, temperature sensor/fan control, EEPROM, USB hub configuration --[[User:Andrey.filippov|Andrey.filippov]] 12:27, 5 March 2008 (CST)

----

I tried to implement the new design according to the specs I proposed on this article. I instantiated the Theora compressor and the 8-channel memory controller in the place of the former jpeg compressor and memory controller and adapted registers and addresses (see article). The synthesis of this design with ISE is completed without error but I expect more issues with the place & route procedure. It would be great if I could share this work on a CVS to have some critics and some support, we had a discussion about that with Alexandre but I'm still waiting for an account. Before going farther, I'm trying to run the simulation with Icarus but I'm experiencing some issues with the compilation :

channel0.v:154: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+('sd1)
channel1.v:152: error: operand of concatenation has indefinite width: (ntile_x[3:0])+('sd1)
channel1.v:155: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+('sd1)

I would appreciate some support concerning how to test and debug the new design since this seems to be a tough issue to deal with.

When simulating Theora I used Silos III simulator on Windows, some work is needed to make it work with Icarus. First step - patch Xilinx unisim library, then - go through code (maybe it needs width for sd1?. The other problem that will come out - in Silos tasks were reenterable, each instance having it's own set of local variables (I used it when simulating CPU interrupts), in Icarus - they all share the same.--[[User:Andrey.filippov|Andrey.filippov]] 12:27, 5 March 2008 (CST)
--[[User:JeremViewsurf|JeremViewsurf]] 08:57, 5 March 2008 (CST)

I fixed the previous compilation error in Icarus, in channel0.v and channel1.v replace
channel0.v:154: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+1
channel1.v:152: error: operand of concatenation has indefinite width: (ntile_x[3:0])+1
channel1.v:155: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+1

with

channel0.v:154: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+11'h1
channel1.v:152: error: operand of concatenation has indefinite width: (ntile_x[3:0])+4'h1
channel1.v:155: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+11'h1

I can finally visualize some chronograms in gtkwave however I'm using the old 353 testbench... Time to understand how the testbench is structured and to think about a smarter one to test the new design. --[[User:JeremViewsurf|JeremViewsurf]] 03:13, 6 March 2008 (CST)

----

I'm working on the simulation of the 333 Theora design (x333t.tf) and it looks like there are three simulation modes for this design that can be switched with 'define : MASTERMODE, MASTERMODE1,SINGLE_ST. What is the difference between these modes and how does each work in summary ? --[[User:JeremViewsurf|JeremViewsurf]] 10:45, 10 March 2008 (CDT)

The source code is now available on the Elphel CVS : [http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ | http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/]. The synthesis of this code is OK but it still have to be tested. I split the testbench between the main simulation sequence and the different tasks. The x353_sim.sh script is up to date but the simulation itself (x353_1.tf) is inadequate to test the design (it is still the old MJPEG testbench). The testbench in the 6.3.9 firmware (333 Theora) seems to fit better but I still need to know how it works precisely in order to adapt it to the 353 design. --[[User:JeremViewsurf|JeremViewsurf]] 09:22, 11 March 2008 (CDT)

----

Some news concerning the simulation of Theora on the 353 :
* I instantiated the x353t module with the sensor and the sdram.
* I'm trying to go through the initialization sequence
* The global initialization works (with glbl.v)
* The DCM reset works (SDRAM clocks SDCLK_D and SDNCLK_D are working)
* I didn't check if the tables programmation is ok yet
* The sdram initialization sequence works :

Initialize SDRAM

>> 214455.000 ns >> cpu_wr(21, 00017fff)
At time 214556.000 ns PRE : Addr[10] = 1, Bank = 11

>> 214605.000 ns >> cpu_wr(21, 00002002)
At time 214708.000 ns EMR : Extended Mode Register
At time 214708.000 ns EMR : Enable DLL

>> 214755.000 ns >> cpu_wr(21, 00000163)
At time 214860.000 ns LMR : Load Mode Register
At time 214860.000 ns LMR : Burst Length = 8
At time 214860.000 ns LMR : CAS Latency = 2.5

>> 214905.000 ns >> cpu_wr(21, 00017fff)
At time 215004.000 ns PRE : Addr[10] = 1, Bank = 11

>> 215055.000 ns >> cpu_wr(21, 00008000)
At time 215156.000 ns AREF : Auto Refresh

>> 215205.000 ns >> cpu_wr(21, 00008000)
At time 215308.000 ns AREF : Auto Refresh
testbench353t.i_mt46v16m16fg: at time 215308.000 ns MEMORY: Power Up and Initialization Sequence is complete

>> 215355.000 ns >> cpu_wr(21, 00000063)
At time 215460.000 ns LMR : Load Mode Register
At time 215460.000 ns LMR : Burst Length = 8
At time 215460.000 ns LMR : CAS Latency = 2.5

Initialize SDRAM done

I committed the changes to the CVS. --[[User:JeremViewsurf|JeremViewsurf]] 05:20, 19 March 2008 (CDT)

I checked the table programming (quantization, huffman, etc), the procedure seems ok. I finally have data output on the SDA and SDD ports after having replace the sensorpix and sensortrig blocks in the 353 with those that were in the 333 Theora (with some modifications in the width of some signals). However, the timings seems completely different between the two sensors and I experience memory overflow during the simulation :

...
At time 1498748.000 ns WRITE: Bank = 3, Row = 0034, Col = 06d, Data = 0000
At time 1498748.000 ns ERROR: Memory overflow.
Write to Address 180d06d with Data 0000 will be lost.
You must increase the part_mem_bits parameter or define FULL_MEM.
At time 1498748.000 ns WRITE: Bank = 3, Col = 070
At time 1498752.000 ns WRITE: Bank = 3, Row = 0034, Col = 06e, Data = 0000
At time 1498752.000 ns ERROR: Memory overflow.
Write to Address 180d06e with Data 0000 will be lost.
You must increase the part_mem_bits parameter or define FULL_MEM.
...

--[[User:JeremViewsurf|JeremViewsurf]] 11:46, 26 March 2008 (CDT)

Have you tried to increase "part_mem_bits"? It's in ddr_parameters.v
--[[User:Oleg|Oleg]] 20:06, 26 March 2008 (CDT)

I defined FULL_MEM in ddr.v to be sure, there is no more memory overflow error. However is the simulation still representative of reality ? --[[User:JeremViewsurf|JeremViewsurf]] 03:32, 27 March 2008 (CDT)

----

I have a question concerning the sensor in both 333 and 353 design. In the 333 the sensor has a 10 bit output that goes directly to the sensorpix module (through sensorpads) to a 10 bit input. However In the 353, the sensor has a 12 bit output that goes to the sensorpads module and is treated to produce a 16 bit output that goes to the sensorpix module. What is the purpose of the extra bits in the 353 design ? Is it possible to extract a 10 bit output from the 353 sensorpad module to feed a 333 sensorpix block ? It looks like that the higher 10 bits of the ipxd[15:0] signal are different from the lower 6 bits (the latter can be forced to 0 with the cnven signal). Are these 10 bits similar to the 10 bits output of the 333 sensor ?

'''sensorpads353.v'''
...
ipxd_pre[ 5:0] <= cnven?6'b0:{ipxded[3:2],pxd14?ipxded[1:0]:2'h0,2'h0};
ipxd_pre[15:6] <= ipxded[15:6];
ipxd[15:0] <= ipxd_pre[15:0];
...

--[[User:JeremViewsurf|JeremViewsurf]] 03:37, 31 March 2008 (CDT)

The 5MPix sensor does have 12 bit output and all the bits are used during "gamma"-table conversion to 8 bits. Even more - the same FPGA code now supports 10347 boards (for Kodak KAI-11002/16000 CCD sensors) that produce 14-bit data.

After the data (10-12-14 bits) reaches the FPGA, it can go two ways - through the LUT (with linear interpolation) conversion to 8 bits and raw - 2 bytes/pixel format, where pixel data is MSB-aligned (actually bit 14 being the highest, bit 15 is left 0 to allow subtraction without overflow). I believe you should use that part (from the sensor interface to the SDRAM - including gamma tables and histograms) the same for Theora as it is now in 353 (for JPEG)--[[User:Andrey.filippov|Andrey.filippov]] 12:09, 31 March 2008 (CDT)

----

I restored the sensorpix353 and sensortrig353 in the Theora design and tested the data path from the sensor to the dma output. Looks like there is no data coming out of the mcontr channel 7 (after the token read buffer). Same issue with the 333 Theora simulation although the design is obviously correct. This might be a flaw in the testbench (?) as I used somehow the same for the two designs. Moreover I can't simulated over 2ms and I can't figure out why the simulations stops at that time. Maybe the second stage of the compressor processes data after 2 ms so it is never reached by the simulator (?)

[[Image:Datapath.jpg]]

--[[User:JeremViewsurf|JeremViewsurf]] 05:17, 7 April 2008 (CDT)

"simulation over 2ms" - $stop in line 639 of x353t.tf finishes the simulation. And there's one file is missing in cvs - linear1028rgb.dat - Jeremy, could you upload it.--[[User:Oleg|Oleg]] 11:44, 8 April 2008 (CDT)

The missing file is now on the cvs, let me know if something else is missing. If you want to check the set of signals in my simulation above, use pxdpath.sav in gtkwave. Before $stop in line 639 of x353t.tf there is now a 5ms delay (#5000000) to let the simulation run, it stops at 700µs... --[[User:JeremViewsurf|JeremViewsurf]] 02:24, 9 April 2008 (CDT)

I needed to copy 'defines333.vh' and '*.dat's from theora/ folder.--[[User:Oleg|Oleg]] 03:59, 10 April 2008 (CDT)

I'm now trying with a 5 ms delay and without $stop after the delay, the simulation is currently at 2.3 ms and is still running ! I looked at the waves, still no output after ch7 (after mcontr_tok_rd to be more precise). --[[User:JeremViewsurf|JeremViewsurf]] 03:44, 9 April 2008 (CDT)

----

At last, I have some output after the memory controller channel 7 after 5h30 of simulation... Basically it seems that a whole frame have to be processed before having any output. Maybe changing nstx and nsty (number of blocks in a row and rows in a frame) parameters would reduce simulation time.

[[Image:Finaldatapath.jpg]]

--[[User:JeremViewsurf|JeremViewsurf]] 07:53, 11 April 2008 (CDT)

Jeremy, what frame size do you try to simulate ? You should try on a minimal: 32x128. Look on the 333 Theora testbench for more info. --[[User:Polto|Alexandre.Poltorak]] 14:28, 11 April 2008 (CDT)

I realized that I did not check the frame dimensions and I tried to simulate 1280x1024 frames (init_dimensions(9,7)). I changed to init_dimensions(1,1) thus setting nstx and nsty to 1. I now have output on ch7 after 2 ms, thanks. --[[User:JeremViewsurf|JeremViewsurf]] 04:07, 14 April 2008 (CDT)

----

I carried out the synthesis of the design with ISE, I am able to get the .bit file with some warnings (old constraints file from 353 : some timings not met, some clocks warnings and obviously unused signals) but no error. I started to have a look at the driver and made a first version of the definition file x3x3.h (see CVS). Some macros at the end may be obsolete as they command the 353 memory controller. --[[User:JeremViewsurf|JeremViewsurf]] 08:32, 17 April 2008 (CDT)

Problem while compiling with definition file x3x3.h :
Making install in packages/os/linux-2.6 for crisv32-axis-linux-gnu
make[2]: entrant dans le répertoire « /home/larrey/Elphel/353t_clean/elphel353-7.1.7.11/elphel353t/packages/os/linux-2.6-R1_4_2 »
subdirs=
MAKE /home/larrey/Elphel/353t_clean/elphel353-7.1.7.11/elphel353t/os/linux-2.6 zImage
make[3]: entrant dans le répertoire « /home/larrey/Elphel/353t_clean/elphel353-7.1.7.11/elphel353t/os/linux-2.6-tag--devboard-R2_10-4 »
CHK include/linux/version.h
CHK include/linux/utsrelease.h
CHK include/linux/compile.h
CC arch/cris/arch-v32/drivers/elphel/fpgajtag.o
In file included from arch/cris/arch-v32/drivers/elphel/fpgajtag.c:95:
arch/cris/arch-v32/drivers/elphel/x3x3.h:963:45: "[" may not appear in macro parameter list
make[5]: *** [arch/cris/arch-v32/drivers/elphel/fpgajtag.o] Erreur 1

At the first occurrence of #include "x3x3.h" some 353 macros such as #define X313_IRQSTATE(port_csp0_addr[0x11],port_csp0_addr[0x11]) with the "[" character stops the compilation. --[[User:JeremViewsurf|JeremViewsurf]] 10:48, 21 April 2008 (CDT)

Strange. Could you pls use LANG=CC ? So others will be able to read error messages too :) What GNU/Linux distribution do you use ? what version of gcc-cris? Also it would be better to sync to last CVS, many bugs was resolved since .11. --[[User:Polto|Alexandre.Poltorak]] 12:45, 21 April 2008 (CDT)
In the http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/os/linux-2.6-tag--devboard-R2_10-4/arch/cris/arch-v32/drivers/elphel/x353.h?view=markup
1053: #define X313_IRQSTATE (port_csp0_addr[0x11],port_csp0_addr[0x11])
there is a space between "X313_IRQSTATE" and "(" separating macro name with 0 parameters and the macro body. Where could that space character disappear in your example?--[[User:Andrey.filippov|Andrey.filippov]] 14:22, 21 April 2008 (CDT)

Andrey is right, that was just a stupid space problem... By the way, I'll get the latest version of the source code as I'm working on the driver (well just trying to understand how is it structured right now...). Thanks for the quick answer. --[[User:JeremViewsurf|JeremViewsurf]] 02:17, 22 April 2008 (CDT)

----

Working on the driver made me realize that the compressor never reached the end of a frame... The compressor just stopped processing data after a while and a bunch of signal switched to an undetermined state. I was working on this issue and realized that I got a problem with clock phases and data was written to wrong locations in the sdram. Now it looks like it's fixed, I don't have undetermined signals anymore and the done_compress signal goes high after a frame is processed. Fixed files have been committed.

I am now dealing with interrupts and I can't make the IRQ signal go high when done_compress is high like the 333 design. In the 333 design there's a simple interrupt manager that let the irq go through according to a certain mask value. However I don't understand how the 353 interrupt vector block works... At that time I just plugged the interrupt sources (done_compress, reset_compress etc) in the irq_in input but obviously I think there are mor to do to make that work. --[[User:JeremViewsurf|JeremViewsurf]] 03:32, 22 May 2008 (CDT)

Talk:Porting Theora to 353 cameras

2008-04-22T07:17:50Z

JeremViewsurf:

Talk:Porting Theora to 353 cameras

2008-04-21T15:48:43Z

JeremViewsurf:

Talk:Porting Theora to 353 cameras

2008-04-17T14:08:51Z

JeremViewsurf:

Talk:Porting Theora to 353 cameras

2008-04-17T13:32:14Z

JeremViewsurf:

--[[User:JeremViewsurf|JeremViewsurf]] 08:32, 17 April 2008 (CDT)Ok, I started a new page on the Theora project in 353 cameras. I started with a global approach and a list of modules that need to be changed or replaced on the 353 model. Feel free to correct me or add suggestions as I'm not (yet...) an expert on Elphel cameras. I think the first step is to make an exhaustive list of the hardware blocks that need modifications and then detail what need to be done in each block. --[[User:JeremViewsurf|JeremViewsurf]] 03:48, 19 February 2008 (CST)

As I understand your first need is not a streaming but producing a small video clip to be uploaded via FTP. This can be done more easy with minimal non FPGA modifications.

We will probably create a CVS branch for your port, to be able to test it we need to compile a standard 7.1.x firmware disabling everything sensor or FPGA related and change the FPGA bitstream. --[[User:Polto|Alexandre.Poltorak]] 07:53, 19 February 2008 (CST)

You mean that it should be possible that the system can handle software Ogg Theora encoding for a non real-time application such as producing small video clips ? I'm aware that it depends on the output resolution, framerate and length of the clip but does a 1 min 1024x768 @ 25fps clip for example can be processed in a reasonable delay ? I'll discuss with Viewsurf's development team in order to obtain more precise specs concerning video output (in terms of length, resolution, framerate and encoding delay acceptable) but if you can give me an idea of what the software part can handle, I would consider spending more time in soft Theora transcoding instead of FPGA design. --[[User:JeremViewsurf|JeremViewsurf]] 03:37, 20 February 2008 (CST)

No, sorry i was not speaking of transcoding. It would take too much calculation power and is not possible on the camera's CPU. The Theora encoding should be done in FPGA. What i was speaking about is the software part.. I think you do not need a streamer for the first steps. You only need to generate a clip in the FPGA memory, and upload it to a FTP. --[[User:Polto|Alexandre.Poltorak]] 08:32, 20 February 2008 (CST)

----

Some questions concerning changes in the FPGA :
* Is it necessary to keep histogram and timestamp blocks in a design which supports Theora only ?
** I believe the camera will be rather crippled w/o those features--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
* Is it possible to keep channel 0, 1 and 3 design without changes in the memory controller ?
** Theora implementation used different (more advanced) memory controller that the JPEG, it was getting 95% efficiency at Theora data structure, so you need Theora memory controller. But if you mean by "Channel 0 design" the gamma tables and histograms - yes, they probably could be ported (with some changes, of course). As for channels 1 and 3 - similar are available in Theora 333 also--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
* The 353 design uses 2 DMA fifos between the compressor and the system interface instead of one in the 333 design. Is it possible to keep only one 333 DMA fifo in the final design ?
** Yes, of course - but this is so minor difference. The more important is that in Theora that FIFO could make the compressor wait if ETRAX DMA is not ready - at the beginning of the frame in theora there is a data "burst".--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
* In the 353 design, all signals and blocks I/O concerning 90° phase clock are commented. Is it possible to uncomment them in order to restore the clock ?
** Maybe yes, more likely no. 353 and 333 use different FPGAs.--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
* Motion compensation seems not to be implemented in the Theora compressor yet. Is it possible to add this feature later in the compressor block without major changes in the final design ?
** No, I'm afraid that is not possible - I believe we need faster FPGA for that and likely faster/wider memory.--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
--[[User:JeremViewsurf|JeremViewsurf]] 02:43, 25 February 2008 (CST)

----

I'm currently working on the FPGA control register and I have a question concerning the I2C pads controlled by the control register (via dcr[16:21]). In the 333 design there are 2 I2C "channels" : (sda0,scl0) and (sda1,scl1) and only one on the 353 design. Is it possible to keep a single i2c channel on the new design ? In other ways, what is the purpose of the i2c "channels" in each device ? --[[User:JeremViewsurf|JeremViewsurf]] 03:19, 3 March 2008 (CST)

The later 353 software also has 2 I2C channels, similar to 333. One channel is designed to communicate to the sensor (and goes through 30-pin flex cable), the other - to additional boards that sit on top of the 353, that I2C bus uses 2 bits (0,1) of the 12-bit GPIO of the 353 FPGA. It is currently used by multiple I2C peripherals on teh 10369 board (IDE bus configuration, clock/calendar, temperature sensor/fan control, EEPROM, USB hub configuration --[[User:Andrey.filippov|Andrey.filippov]] 12:27, 5 March 2008 (CST)

----

I tried to implement the new design according to the specs I proposed on this article. I instantiated the Theora compressor and the 8-channel memory controller in the place of the former jpeg compressor and memory controller and adapted registers and addresses (see article). The synthesis of this design with ISE is completed without error but I expect more issues with the place & route procedure. It would be great if I could share this work on a CVS to have some critics and some support, we had a discussion about that with Alexandre but I'm still waiting for an account. Before going farther, I'm trying to run the simulation with Icarus but I'm experiencing some issues with the compilation :

channel0.v:154: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+('sd1)
channel1.v:152: error: operand of concatenation has indefinite width: (ntile_x[3:0])+('sd1)
channel1.v:155: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+('sd1)

I would appreciate some support concerning how to test and debug the new design since this seems to be a tough issue to deal with.

When simulating Theora I used Silos III simulator on Windows, some work is needed to make it work with Icarus. First step - patch Xilinx unisim library, then - go through code (maybe it needs width for sd1?. The other problem that will come out - in Silos tasks were reenterable, each instance having it's own set of local variables (I used it when simulating CPU interrupts), in Icarus - they all share the same.--[[User:Andrey.filippov|Andrey.filippov]] 12:27, 5 March 2008 (CST)
--[[User:JeremViewsurf|JeremViewsurf]] 08:57, 5 March 2008 (CST)

I fixed the previous compilation error in Icarus, in channel0.v and channel1.v replace
channel0.v:154: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+1
channel1.v:152: error: operand of concatenation has indefinite width: (ntile_x[3:0])+1
channel1.v:155: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+1

with

channel0.v:154: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+11'h1
channel1.v:152: error: operand of concatenation has indefinite width: (ntile_x[3:0])+4'h1
channel1.v:155: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+11'h1

I can finally visualize some chronograms in gtkwave however I'm using the old 353 testbench... Time to understand how the testbench is structured and to think about a smarter one to test the new design. --[[User:JeremViewsurf|JeremViewsurf]] 03:13, 6 March 2008 (CST)

----

I'm working on the simulation of the 333 Theora design (x333t.tf) and it looks like there are three simulation modes for this design that can be switched with 'define : MASTERMODE, MASTERMODE1,SINGLE_ST. What is the difference between these modes and how does each work in summary ? --[[User:JeremViewsurf|JeremViewsurf]] 10:45, 10 March 2008 (CDT)

The source code is now available on the Elphel CVS : [http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ | http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/]. The synthesis of this code is OK but it still have to be tested. I split the testbench between the main simulation sequence and the different tasks. The x353_sim.sh script is up to date but the simulation itself (x353_1.tf) is inadequate to test the design (it is still the old MJPEG testbench). The testbench in the 6.3.9 firmware (333 Theora) seems to fit better but I still need to know how it works precisely in order to adapt it to the 353 design. --[[User:JeremViewsurf|JeremViewsurf]] 09:22, 11 March 2008 (CDT)

----

Some news concerning the simulation of Theora on the 353 :
* I instantiated the x353t module with the sensor and the sdram.
* I'm trying to go through the initialization sequence
* The global initialization works (with glbl.v)
* The DCM reset works (SDRAM clocks SDCLK_D and SDNCLK_D are working)
* I didn't check if the tables programmation is ok yet
* The sdram initialization sequence works :

Initialize SDRAM

>> 214455.000 ns >> cpu_wr(21, 00017fff)
At time 214556.000 ns PRE : Addr[10] = 1, Bank = 11

>> 214605.000 ns >> cpu_wr(21, 00002002)
At time 214708.000 ns EMR : Extended Mode Register
At time 214708.000 ns EMR : Enable DLL

>> 214755.000 ns >> cpu_wr(21, 00000163)
At time 214860.000 ns LMR : Load Mode Register
At time 214860.000 ns LMR : Burst Length = 8
At time 214860.000 ns LMR : CAS Latency = 2.5

>> 214905.000 ns >> cpu_wr(21, 00017fff)
At time 215004.000 ns PRE : Addr[10] = 1, Bank = 11

>> 215055.000 ns >> cpu_wr(21, 00008000)
At time 215156.000 ns AREF : Auto Refresh

>> 215205.000 ns >> cpu_wr(21, 00008000)
At time 215308.000 ns AREF : Auto Refresh
testbench353t.i_mt46v16m16fg: at time 215308.000 ns MEMORY: Power Up and Initialization Sequence is complete

>> 215355.000 ns >> cpu_wr(21, 00000063)
At time 215460.000 ns LMR : Load Mode Register
At time 215460.000 ns LMR : Burst Length = 8
At time 215460.000 ns LMR : CAS Latency = 2.5

Initialize SDRAM done

I committed the changes to the CVS. --[[User:JeremViewsurf|JeremViewsurf]] 05:20, 19 March 2008 (CDT)

I checked the table programming (quantization, huffman, etc), the procedure seems ok. I finally have data output on the SDA and SDD ports after having replace the sensorpix and sensortrig blocks in the 353 with those that were in the 333 Theora (with some modifications in the width of some signals). However, the timings seems completely different between the two sensors and I experience memory overflow during the simulation :

...
At time 1498748.000 ns WRITE: Bank = 3, Row = 0034, Col = 06d, Data = 0000
At time 1498748.000 ns ERROR: Memory overflow.
Write to Address 180d06d with Data 0000 will be lost.
You must increase the part_mem_bits parameter or define FULL_MEM.
At time 1498748.000 ns WRITE: Bank = 3, Col = 070
At time 1498752.000 ns WRITE: Bank = 3, Row = 0034, Col = 06e, Data = 0000
At time 1498752.000 ns ERROR: Memory overflow.
Write to Address 180d06e with Data 0000 will be lost.
You must increase the part_mem_bits parameter or define FULL_MEM.
...

--[[User:JeremViewsurf|JeremViewsurf]] 11:46, 26 March 2008 (CDT)

Have you tried to increase "part_mem_bits"? It's in ddr_parameters.v
--[[User:Oleg|Oleg]] 20:06, 26 March 2008 (CDT)

I defined FULL_MEM in ddr.v to be sure, there is no more memory overflow error. However is the simulation still representative of reality ? --[[User:JeremViewsurf|JeremViewsurf]] 03:32, 27 March 2008 (CDT)

----

I have a question concerning the sensor in both 333 and 353 design. In the 333 the sensor has a 10 bit output that goes directly to the sensorpix module (through sensorpads) to a 10 bit input. However In the 353, the sensor has a 12 bit output that goes to the sensorpads module and is treated to produce a 16 bit output that goes to the sensorpix module. What is the purpose of the extra bits in the 353 design ? Is it possible to extract a 10 bit output from the 353 sensorpad module to feed a 333 sensorpix block ? It looks like that the higher 10 bits of the ipxd[15:0] signal are different from the lower 6 bits (the latter can be forced to 0 with the cnven signal). Are these 10 bits similar to the 10 bits output of the 333 sensor ?

'''sensorpads353.v'''
...
ipxd_pre[ 5:0] <= cnven?6'b0:{ipxded[3:2],pxd14?ipxded[1:0]:2'h0,2'h0};
ipxd_pre[15:6] <= ipxded[15:6];
ipxd[15:0] <= ipxd_pre[15:0];
...

--[[User:JeremViewsurf|JeremViewsurf]] 03:37, 31 March 2008 (CDT)

The 5MPix sensor does have 12 bit output and all the bits are used during "gamma"-table conversion to 8 bits. Even more - the same FPGA code now supports 10347 boards (for Kodak KAI-11002/16000 CCD sensors) that produce 14-bit data.

After the data (10-12-14 bits) reaches the FPGA, it can go two ways - through the LUT (with linear interpolation) conversion to 8 bits and raw - 2 bytes/pixel format, where pixel data is MSB-aligned (actually bit 14 being the highest, bit 15 is left 0 to allow subtraction without overflow). I believe you should use that part (from the sensor interface to the SDRAM - including gamma tables and histograms) the same for Theora as it is now in 353 (for JPEG)--[[User:Andrey.filippov|Andrey.filippov]] 12:09, 31 March 2008 (CDT)

----

I restored the sensorpix353 and sensortrig353 in the Theora design and tested the data path from the sensor to the dma output. Looks like there is no data coming out of the mcontr channel 7 (after the token read buffer). Same issue with the 333 Theora simulation although the design is obviously correct. This might be a flaw in the testbench (?) as I used somehow the same for the two designs. Moreover I can't simulated over 2ms and I can't figure out why the simulations stops at that time. Maybe the second stage of the compressor processes data after 2 ms so it is never reached by the simulator (?)

[[Image:Datapath.jpg]]

--[[User:JeremViewsurf|JeremViewsurf]] 05:17, 7 April 2008 (CDT)

"simulation over 2ms" - $stop in line 639 of x353t.tf finishes the simulation. And there's one file is missing in cvs - linear1028rgb.dat - Jeremy, could you upload it.--[[User:Oleg|Oleg]] 11:44, 8 April 2008 (CDT)

The missing file is now on the cvs, let me know if something else is missing. If you want to check the set of signals in my simulation above, use pxdpath.sav in gtkwave. Before $stop in line 639 of x353t.tf there is now a 5ms delay (#5000000) to let the simulation run, it stops at 700µs... --[[User:JeremViewsurf|JeremViewsurf]] 02:24, 9 April 2008 (CDT)

I needed to copy 'defines333.vh' and '*.dat's from theora/ folder.--[[User:Oleg|Oleg]] 03:59, 10 April 2008 (CDT)

I'm now trying with a 5 ms delay and without $stop after the delay, the simulation is currently at 2.3 ms and is still running ! I looked at the waves, still no output after ch7 (after mcontr_tok_rd to be more precise). --[[User:JeremViewsurf|JeremViewsurf]] 03:44, 9 April 2008 (CDT)

----

At last, I have some output after the memory controller channel 7 after 5h30 of simulation... Basically it seems that a whole frame have to be processed before having any output. Maybe changing nstx and nsty (number of blocks in a row and rows in a frame) parameters would reduce simulation time.

[[Image:Finaldatapath.jpg]]

--[[User:JeremViewsurf|JeremViewsurf]] 07:53, 11 April 2008 (CDT)

Jeremy, what frame size do you try to simulate ? You should try on a minimal: 32x128. Look on the 333 Theora testbench for more info. --[[User:Polto|Alexandre.Poltorak]] 14:28, 11 April 2008 (CDT)

I realized that I did not check the frame dimensions and I tried to simulate 1280x1024 frames (init_dimensions(9,7)). I changed to init_dimensions(1,1) thus setting nstx and nsty to 1. I now have output on ch7 after 2 ms, thanks. --[[User:JeremViewsurf|JeremViewsurf]] 04:07, 14 April 2008 (CDT)

----

I carried out the synthesis of the design with ISE, I am able to get the .bit file with some warnings (old constraints file from 353 : some timings not met, some clocks warnings and obviously unused signals) but no error. I started to have a look at the driver and made a first version of the definition file x3x3.h (see CVS). Some macros at the end may be obsolete as they command the 353 memory controller. --[[User:JeremViewsurf|JeremViewsurf]] 08:32, 17 April 2008 (CDT)

Porting Theora to 353 cameras

2008-04-16T14:16:31Z

JeremViewsurf: /* Compressor */

Elphel model 333 cameras were able to encode and stream Ogg Theora with 6.3.9 firmware. However, this model is no longer produced by Elphel. The goal of this project is to use the full potential of 353 cameras (larger FPGA, faster CPU) in order to port the Ogg Theora feature on the new hardware. First, the camera should be able to upload small Theora clips via FTP.

Different solutions are possible as previously mentioned in the [[Theora]] page :
* Instantiate both the Theora compressor and the MJPEG compressor in the FPGA since the new Spartan 3E seems to be large enough to handle the two features.
* Replace the existing MJPEG compressor with the Theora compressor and implement software Theora to JPEG conversion if JPEG is needed.
* Replace the existing MJPEG compressor in the 353 camera with the Theora compressor and keep two configuration files on the camera filesystem (one for Theora the other for MJPEG). FPGA code could be changed at run-time according to the needs.

Dealing with the last solution seems to be a good start for this project as the other features mentioned can be added later. In all cases, both FPGA code and software code will need to be adapted.

The source code of this project is available at [http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/]
== Hardware updates ==

=== Compressor ===
[[Image:Schematic.png|frame|[[Media:Schematic.png|333 Theora design with the 2 stage compressor and the 8-channel memory controller]]]]
Replace the MJPEG compressor in the 353 with the 333 Theora compressor ([http://elphel.cvs.sourceforge.net/elphel/camera333/fpga/x333 333 Theora FPGA code]). Maybe some adaptations need to be done within the Theora compressor itself. However, assuming that the compressor worked in 333 cameras a simple instantiation should suffice.

=== Memory controller ===
Replace the 4-channel memory controller with an 8 channel memory interface as in the 333 model in order to handle Theora specific data.

{|border="1" cellpadding="2"
! Channel !! 333 Theora !! 353
|-
| '''0''' || 8/16 bit data from sensor to SDRAM || Data from the sensor (it can be combined with FPN correction data) to the SDRAM in either 8-bit mode or 16-bit
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module || Reads FPN data from SDRAM (8bit - subtract, 8 bit - scale) and feeds it to FPGA for FPN correction of the data on the way from sensor to SDRAM (through channel 0)
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor || Provides data to JPEG encoder in 16x16x8bit MCUs. It can also provide data directly to CPU through DMA bypassing any compression
|-
| '''3''' || PIO read/write of SDRAM data || Provides bidirectional access from CPU through 8x32 bit window.
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM ||
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM ||
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63] ||
|-
| '''7''' || reading 12-bit pre-tokens from SDRAM in indexed coded order ||
|-
|}

=== Sensor interface ===
''sensorpix'' block must be adapted in order to provide a coherent interface between the memory controller and the sensor (channels 0 and 1)

=== System Interface ===
Adapt the system interface to assure communication between FPGA and its environment.

A feature of the system interface is to establish communication between the system CPU and the different blocks within the FPGA (compressor, memory controller etc). This is done by selecting a block with the address bus ''a[12:0]'' connected to the internal address bus ''ial[7:0]'':

'''x353.v'''
always @ (posedge cwr) begin
a0[7:0]<=ial[7:0]; // may want to change to just ia if ia will be late enough;
wnr0 <= ~irnw;
da_ctl0 <= (ial[7:0]==8'h00); // 0x00 WE to control 32-bit register (1 loc)
da_dmamode0 <= (ial[7:0]==8'h01); // 0x01 select writing to dma_cntr/dma_raw (1 loc)
da_sensormode0 <= (ial[7:0]==8'h02); // 0x02 select writing to sensorpix (1 loc)
...
da_compressor0 <= (ial[7:1]==7'h06); // 0x0c..0x0d - will be farther decoded in the compressor module
...

Since memory controller and compressor are to be replaced these addresses have to be adapted.

''353 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x09''' || da_saturation0 || write color saturation values
|-
| '''0x0a''' || da_framesync_dly0 || write frame sync interrupt delay (in scan lines)
|-
| '''0x0c..0x0d''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x0e''' || da_table_a0 || write tables address
|-
| '''0x0f''' || twr0 || write tables data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts0 || interrupt control
|-
| '''0x20..0x2f''' || da_dswe0 || select reading/writing to mcontr (16 locations)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist0 || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc0 || real time clock
|-
| '''0x48''' || da_timestamp0 || write timestamp mode
|-
| '''0x74''' || da_xjtag0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync0 || control of external sync module 0x78 - 0x7b
|-
|}

''333 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or aftre trigger)
|-
| '''0x06''' || da_interrupts0 || interrupt mask
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x10''' || da_debug || write 0x10 any - load debug shift, read (through cs4) -shift
|-
| '''0x20..0x27''' || da_mcontr0 || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table0 || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
|}

Addresses 0x01,2,3,4,5,6,8 and 0x30 can be kept in the 353 system interface. The interrupt mask address 0x06 in the 333 sys interface is no longer used (353 uses interrupt vectors). The Theora compressor and the new memory controller addresses have to be mapped again in the new design (addresses 0x0c..0x0d and 0x20 to 0x2f in the 353 sys interface).

=== Interrupts ===
Adapt the Theora compressor interrupts to the 353 interrupt vector .

The 353 interrupt vector can handle up to 16 different irq. However, only irq 0 to 7 are used :
'''x353.v'''

assign irq_in= {8'b0, // extra
compressor_done_compress, // 7 - will go high after all data is sent out (reset by compressor)
compressor_done_input, // 6 - will go high after EOT and persist until DCT is enabled (reset by compressor)
dcc_rdy, // 5 - obsolete in 333 - channel3 has 128 more dc coefficients (or some if the compression is finished)
compressor_eot, // 4 - compressor read in the last MCU (predictable time to end of transfer)
sr_sensortrig[2], // 3 - (sync to pclk) - level, reset by writing to sensor triggering command register
xfer_over_irq, // 2 - (sync to pclk) - frame acquisition over
trig_irq, // 1 - (sync to pclk) - external trigger
vacts}; // 0 - (sync to pclk) - frame sync

353 MJPEG compressor triggers irqs 4, 6 and 7. 333 Theora compressor is the source of two irqs :
'''compressor_all.v'''

done, // single-cycle pulse when the compressed frame is sent out (IRQ source).
reset_compress, // reset compressor done interrupt (writing any compressor command)

Adaptation should consist of assigning Theora compressor irq sources to vectors 6 and 7 for example if the MJPEG compressor is to be replaced.

=== DMA FIFOs ===
353 design uses 2 DMA FIFOs between the compressor and the system interface instead of one for the 333 Theora compressor. The two DMA FIFOs have also slight differences between the two design. Maybe a single 333 FIFO should be kept for the final design (?)

=== FPGA -> CPU data out MUX ===
The purpose of this MUX is to route data out from the different FPGA blocks to the system interface and then to the data bus to the CPU. The selection is made with the internal address bus ''ia''.
_
--| \
--| |
--| |
--| |--- iod[31:0] -> to system interface
--| |
--| |
|_/
from system interface -> ia[7:0]__|

'' 333 MUX ''
{|border="1" cellpadding="2"
! Adress range !! ia(5) !! ia(4) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''1''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''1''' || '''0''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''1''' || '''1''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0.. (even)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''0''' || dma_d0[31:0] || DMA 0 data
|-
| '''0x0.. (odd)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''1''' || dma_d1[31:0] || DMA 1 data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''X''' || '''X''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''X''' || '''X''' || dsdo[31:0] || Data out from descriptor memory
|-
| '''0x3..''' || '''0''' || '''1''' || '''1''' || '''X''' || '''X''' || bdo[31:0] || 32-bit data from SDRAM channel3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''X''' || '''0''' || '''X''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''X''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''X''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''X''' || '''X''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''X''' || '''X''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

'' 333 MUX ''
{|border="1" cellpadding="2"
! Address || ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || {24'b0,irqr[7:0]} || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(2) !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''0''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''0''' || '''1''' || '''1''' || MODELREV || Model revision
|-
| '''0x14''' || '''1''' || '''X''' || '''0''' || {8'h0,imgptr[23:0]} || Image pointer in 32-byte chunks
|-
| '''0x15''' || '''1''' || '''X''' || '''1''' || hifreq[31:0] || Accumulated high-freq components
|-
|}

'' 333 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock0
|-
| '''2''' || sr_sda1 || I2C
|-
| '''3''' || sr_scl1 || I2C clock1
|-
| '''4..12''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''17''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''18''' || 1'b0 || 0x0
|-
| '''19''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''20''' || itrig || TRIG input
|-
| '''21..22''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)
, 01 - clock is too late
, 10 - clock is too early
, 11 - OK (some measurements show too late, some - too early)
|-
| '''23''' || dcm_done ||
|-
| '''24''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''25''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''26''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''27''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''28''' || tok_frame_num_wr || Odd/even frame of tokens written
|-
| '''29''' || 1'b0 || 0x0
|-
| '''30''' || debug_out || Debug shift register output
|-
| '''31''' || 'b0 || 0x0
|-
|}

'' 353 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2''' || sr_ch0rdy || Ready to write next page (channel 0) SENSOR->SDRAM
|-
| '''3''' || sr_ch1rdy || Ready to read next page (channel 1) SDRAM->FPN(SENSOR)
|-
| '''4''' || sr_ch2rdy || Ready to read next page (channel 2) SDRAM->DMA
|-
| '''5''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''6''' || sr_wrempty || CPU write buffer empty (valid only in write mode). May reprogram channel3.
|-
| '''7..10''' || sr_nextFrame[3:0] || (level) generated before actual block is filled - needed to be combined with the pulse from buffer control
|-
| '''11..13''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''14''' || dcc_rdy || 128 of DC components from JPEG encoder are available (same as interrupt)
|-
| '''15''' || compressor_done_input || will go high after EOT and persist until DCT is enabled
|-
| '''16''' || compressor_done_compress || will go high after all data is sent out
|-
| '''17''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''19..18''' || dcm_err[1:0] || SDRAM DCM phase error
|-
| '''20''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''21''' || dcm_locked || SDRAM DCM overflow
|-
| '''22''' || dcm_status[0] || SDRAM DCM overflow
|-
| '''24..23''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''25''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''26''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''27''' || sens_dcm_status[0] || Sensor DCM overflow
|-
| '''28''' || clockios_locked || dcm locked
|-
| '''29..30''' || clockios_status[1:0] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''31''' || 1'b0 || 0x0
|-
|}

=== Control register ===
The dcr[31:0] bus is used to control the different blocks according to the control register values. The control register can be directly written by the CPU at the address 0x00.

''333 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0..2''' || Not used ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || iobuf || EXPS (output pin)
|-
| '''12''' || iobuf || EXPS (output pin)
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || i2cpads || scl1 out
|-
| '''20''' || i2cpads || scl1 enable
|-
| '''21''' || i2cpads || sda1 out
|-
| '''22''' || i2cpads || sda1 enable
|-
| '''23''' || Not used ||
|-
| '''24..27''' || clock_pclk || pclk source
|-
| '''28..30''' || Not used ||
|-
| '''31''' || clock_pclk || clk enable
|-
|}

''353 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0''' || Not used ||
|-
| '''1..2''' || compressor, sensorpix, histogram ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || sensorpads || sensor trigger
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || sensorpads || dclkmode
|-
| '''20''' || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || Not used ||
|-
| '''24..25''' || BUFGMUX || pclk source
|-
| '''28..30''' || compressor ||
|-
| '''31''' || clock_pclk ||
|-
|}

=== Others ===
* Looks like Theora compressor requires 90° phase clock that was abandoned in the 353 design.
Using different phases reduces AC component of the current through the power/ground lines of the FPGA by spreading register transitions. Theora has larger core so it may help spreading phases.--[[User:Andrey.filippov|Andrey.filippov]] 13:45, 25 February 2008 (CST)
* ...?

== Software updates ==

* Adapt FPGA definitions ([http://elphel.cvs.sourceforge.net/elphel/elphel353/elphel353/os/linux-2.6-tag--devboard-R2_01-1/arch/cris/arch-v32/drivers/elphel/x353.h?revision=1.8&view=markup&sortdir=down x353.h]) and most likely some other FPGA drivers.
* ...?

These lists of update are obviously incomplete. They need to be more detailed in order to make an exhaustive list of the changes that have to be done.

== 353 Theora new design ==
=== Compressor ===

Writing tables in compressor (and mcontr8ch) is the same than the 333 design :
* ia = 0x2d and idi = table address (X313_WA_COMP_TA=0x2d)
then
* ia = 0x2c and idi = table data (X313_WA_COMP_TD=0x2c)

Example : Writing zerobin and quantization tables in 353 Theora design

[[Image:Writetabs.jpg]]

=== Sensorpix ===

Most of the 353 design was used for the new design. Writing procedure for gamma tables in sensorpix block is the same than in 353 (ie with ta bus and twr_gamma signal).

* ia = 0x0e and idi = table address

then

* ia = 0x0f and idi = table data

Table address is not autoincremented within the sensorpix block but is fed externally with the ta bus.

[[Image:Gammatab.jpg]]

=== Memory controller ===

{|border="1" cellpadding="2"
! Channel !! Description
|-
| '''0''' || 8/16 bit data from sensor to SDRAM
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor
|-
| '''3''' || PIO read/write of SDRAM data
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63]
|-
| '''7''' || Reading 12-bit pre-tokens from SDRAM in indexed coded order
|-
|}

=== System interface ===

{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm || tune SDRAM clock phase
|-
| '''0x0a''' || da_framesync_dly || write frame sync interrupt delay (in scan lines)
|-
| '''0x0e''' || da_table_a0 || write gamma table address
|-
| '''0x0f''' || twr0 || write gamma table data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts || interrupt control
|-
| '''0x20..0x27''' || da_mcontr || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc || real time clock
|-
| '''0x48''' || da_timestamp || write timestamp mode
|-
| '''0x74''' || da_xjta0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync || control of external sync module 0x78 - 0x7b
|-
|}

=== Interrupts ===

{|border="1" cellpadding="2"
! irq_in !! Signal !! Comments
|-
| '''15..8''' || GND || Extra
|-
| '''7''' || compressor_done_compress || single-cycle pulse when the compressed frame is sent out
|-
| '''6''' || compressor_reset_compress || reset compressor done interrupt (writing any compressor command)
|-
| '''5''' || GND || dcc_rdy was tied to GND in the 333 design
|-
| '''4''' || GND || eot irq was tied to GND in the 333 design
|-
| '''3''' || sr_sensortrig[2] || (sync to pclk) - level, reset by writing to sensor triggering command register
|-
| '''2''' || xfer_over_irq || (sync to pclk) - frame acquisition over
|-
| '''1''' || trig_irq || (sync to pclk) - external trigger
|-
| '''0''' || vacts || (sync to pclk) - frame sync
|-
|}

=== DMA FIFOs ===
A single DMA FIFO from the 333 design will be instanciated.

=== FPGA -> CPU data out MUX ===

{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || '''0''' || '''x''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''x''' || '''x''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''x''' || '''0''' || '''x''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''x''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''x''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''x''' || '''x''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''x''' || '''x''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

{|border="1" cellpadding="2"
! Address !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' Status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C data
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2..10''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''11''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''12''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''17..18''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)

, 01 - clock is too late , 10 - clock is too early , 11 - OK (some measurements show too late, some - too early)
|-
| '''19''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''20''' || dcm_locked || SDRAM DCM overflow
|-
| '''21..22''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''23''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''24''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''25''' || clockios_locked || dcm locked
|-
| '''26''' || clockios_status[1] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''27''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''28''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''29''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''30''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''31''' || took_frame_num_wr || Odd/even frame of tokens written
|-
|}

=== Control register ===
{|border="1" cellpadding="2"
! bit # !! Signal || Destination block !! Comments
|-
| '''0''' || || Not used ||
|-
| '''1..2''' || cb_bayer_phase || compressor, sensorpix, histogram ||
|-
| '''3''' || || sensorpads || Inverts idclk phase (Not used)
|-
| '''4''' || cb_fillfactory || sensorpads || fillfactory sensor mode
|-
| '''5''' || cb_dlyhact || sensorpads || delay hact pulse by 1
|-
| '''6''' || cb_zoran || sensorpads || ''cb_zoran''
|-
| '''7''' || cb_skipline || sensorpads || skip first scan line from the sensor
|-
| '''8''' || cb_xt_pol || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || iarst || sensorpads || ''iarst''
|-
| '''10''' || iaro || sensorpads || ''iaro''
|-
| '''11''' || cb_encnvclk || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || cb_sensor_trigger || sensorpads || sensor trigger
|-
| '''13''' || imrst || sensorpads || ''imrst''
|-
| '''14''' || cb_scl0_o || iobuf || XRST (output pin)
|-
| '''15''' || cb_scl0_o || i2cpads || scl0 out
|-
| '''16''' || cb_scl0_en || i2cpads || scl0 enable
|-
| '''17''' || cb_sda0_o || i2cpads || sda0 out
|-
| '''18''' || cb_sda0_en || i2cpads || sda0 enable
|-
| '''19''' || cb_dclkmode || sensorpads || dclkmode
|-
| '''20''' || cb_pxd14 || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || cb_latehact || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || || Not used ||
|-
| '''24..25''' || cb_pclksrc || BUFGMUX || pclk source
|-
| '''28..30''' || || Not used ||
|-
| '''31''' || || Not used ||
|-
|}

=== Others ===

== See also ==

*[http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ 353 Theora CVS]
*[[Theora]]
*[[FPGA_Development_in_Elphel_cameras|FPGA Development in Elphel cameras]]
*[[Design Ideas|FPGA Theora Encoder for Videoconferencing]]
*[[10353]]

Porting Theora to 353 cameras

2008-04-16T14:15:53Z

JeremViewsurf: /* Compressor */

Elphel model 333 cameras were able to encode and stream Ogg Theora with 6.3.9 firmware. However, this model is no longer produced by Elphel. The goal of this project is to use the full potential of 353 cameras (larger FPGA, faster CPU) in order to port the Ogg Theora feature on the new hardware. First, the camera should be able to upload small Theora clips via FTP.

Different solutions are possible as previously mentioned in the [[Theora]] page :
* Instantiate both the Theora compressor and the MJPEG compressor in the FPGA since the new Spartan 3E seems to be large enough to handle the two features.
* Replace the existing MJPEG compressor with the Theora compressor and implement software Theora to JPEG conversion if JPEG is needed.
* Replace the existing MJPEG compressor in the 353 camera with the Theora compressor and keep two configuration files on the camera filesystem (one for Theora the other for MJPEG). FPGA code could be changed at run-time according to the needs.

Dealing with the last solution seems to be a good start for this project as the other features mentioned can be added later. In all cases, both FPGA code and software code will need to be adapted.

The source code of this project is available at [http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/]
== Hardware updates ==

=== Compressor ===
[[Image:Schematic.png|frame|[[Media:Schematic.png|333 Theora design with the 2 stage compressor and the 8-channel memory controller]]]]
Replace the MJPEG compressor in the 353 with the 333 Theora compressor ([http://elphel.cvs.sourceforge.net/elphel/camera333/fpga/x333 333 Theora FPGA code]). Maybe some adaptations need to be done within the Theora compressor itself. However, assuming that the compressor worked in 333 cameras a simple instantiation should suffice.

=== Memory controller ===
Replace the 4-channel memory controller with an 8 channel memory interface as in the 333 model in order to handle Theora specific data.

{|border="1" cellpadding="2"
! Channel !! 333 Theora !! 353
|-
| '''0''' || 8/16 bit data from sensor to SDRAM || Data from the sensor (it can be combined with FPN correction data) to the SDRAM in either 8-bit mode or 16-bit
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module || Reads FPN data from SDRAM (8bit - subtract, 8 bit - scale) and feeds it to FPGA for FPN correction of the data on the way from sensor to SDRAM (through channel 0)
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor || Provides data to JPEG encoder in 16x16x8bit MCUs. It can also provide data directly to CPU through DMA bypassing any compression
|-
| '''3''' || PIO read/write of SDRAM data || Provides bidirectional access from CPU through 8x32 bit window.
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM ||
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM ||
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63] ||
|-
| '''7''' || reading 12-bit pre-tokens from SDRAM in indexed coded order ||
|-
|}

=== Sensor interface ===
''sensorpix'' block must be adapted in order to provide a coherent interface between the memory controller and the sensor (channels 0 and 1)

=== System Interface ===
Adapt the system interface to assure communication between FPGA and its environment.

A feature of the system interface is to establish communication between the system CPU and the different blocks within the FPGA (compressor, memory controller etc). This is done by selecting a block with the address bus ''a[12:0]'' connected to the internal address bus ''ial[7:0]'':

'''x353.v'''
always @ (posedge cwr) begin
a0[7:0]<=ial[7:0]; // may want to change to just ia if ia will be late enough;
wnr0 <= ~irnw;
da_ctl0 <= (ial[7:0]==8'h00); // 0x00 WE to control 32-bit register (1 loc)
da_dmamode0 <= (ial[7:0]==8'h01); // 0x01 select writing to dma_cntr/dma_raw (1 loc)
da_sensormode0 <= (ial[7:0]==8'h02); // 0x02 select writing to sensorpix (1 loc)
...
da_compressor0 <= (ial[7:1]==7'h06); // 0x0c..0x0d - will be farther decoded in the compressor module
...

Since memory controller and compressor are to be replaced these addresses have to be adapted.

''353 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x09''' || da_saturation0 || write color saturation values
|-
| '''0x0a''' || da_framesync_dly0 || write frame sync interrupt delay (in scan lines)
|-
| '''0x0c..0x0d''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x0e''' || da_table_a0 || write tables address
|-
| '''0x0f''' || twr0 || write tables data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts0 || interrupt control
|-
| '''0x20..0x2f''' || da_dswe0 || select reading/writing to mcontr (16 locations)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist0 || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc0 || real time clock
|-
| '''0x48''' || da_timestamp0 || write timestamp mode
|-
| '''0x74''' || da_xjtag0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync0 || control of external sync module 0x78 - 0x7b
|-
|}

''333 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or aftre trigger)
|-
| '''0x06''' || da_interrupts0 || interrupt mask
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x10''' || da_debug || write 0x10 any - load debug shift, read (through cs4) -shift
|-
| '''0x20..0x27''' || da_mcontr0 || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table0 || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
|}

Addresses 0x01,2,3,4,5,6,8 and 0x30 can be kept in the 353 system interface. The interrupt mask address 0x06 in the 333 sys interface is no longer used (353 uses interrupt vectors). The Theora compressor and the new memory controller addresses have to be mapped again in the new design (addresses 0x0c..0x0d and 0x20 to 0x2f in the 353 sys interface).

=== Interrupts ===
Adapt the Theora compressor interrupts to the 353 interrupt vector .

The 353 interrupt vector can handle up to 16 different irq. However, only irq 0 to 7 are used :
'''x353.v'''

assign irq_in= {8'b0, // extra
compressor_done_compress, // 7 - will go high after all data is sent out (reset by compressor)
compressor_done_input, // 6 - will go high after EOT and persist until DCT is enabled (reset by compressor)
dcc_rdy, // 5 - obsolete in 333 - channel3 has 128 more dc coefficients (or some if the compression is finished)
compressor_eot, // 4 - compressor read in the last MCU (predictable time to end of transfer)
sr_sensortrig[2], // 3 - (sync to pclk) - level, reset by writing to sensor triggering command register
xfer_over_irq, // 2 - (sync to pclk) - frame acquisition over
trig_irq, // 1 - (sync to pclk) - external trigger
vacts}; // 0 - (sync to pclk) - frame sync

353 MJPEG compressor triggers irqs 4, 6 and 7. 333 Theora compressor is the source of two irqs :
'''compressor_all.v'''

done, // single-cycle pulse when the compressed frame is sent out (IRQ source).
reset_compress, // reset compressor done interrupt (writing any compressor command)

Adaptation should consist of assigning Theora compressor irq sources to vectors 6 and 7 for example if the MJPEG compressor is to be replaced.

=== DMA FIFOs ===
353 design uses 2 DMA FIFOs between the compressor and the system interface instead of one for the 333 Theora compressor. The two DMA FIFOs have also slight differences between the two design. Maybe a single 333 FIFO should be kept for the final design (?)

=== FPGA -> CPU data out MUX ===
The purpose of this MUX is to route data out from the different FPGA blocks to the system interface and then to the data bus to the CPU. The selection is made with the internal address bus ''ia''.
_
--| \
--| |
--| |
--| |--- iod[31:0] -> to system interface
--| |
--| |
|_/
from system interface -> ia[7:0]__|

'' 333 MUX ''
{|border="1" cellpadding="2"
! Adress range !! ia(5) !! ia(4) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''1''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''1''' || '''0''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''1''' || '''1''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0.. (even)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''0''' || dma_d0[31:0] || DMA 0 data
|-
| '''0x0.. (odd)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''1''' || dma_d1[31:0] || DMA 1 data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''X''' || '''X''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''X''' || '''X''' || dsdo[31:0] || Data out from descriptor memory
|-
| '''0x3..''' || '''0''' || '''1''' || '''1''' || '''X''' || '''X''' || bdo[31:0] || 32-bit data from SDRAM channel3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''X''' || '''0''' || '''X''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''X''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''X''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''X''' || '''X''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''X''' || '''X''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

'' 333 MUX ''
{|border="1" cellpadding="2"
! Address || ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || {24'b0,irqr[7:0]} || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(2) !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''0''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''0''' || '''1''' || '''1''' || MODELREV || Model revision
|-
| '''0x14''' || '''1''' || '''X''' || '''0''' || {8'h0,imgptr[23:0]} || Image pointer in 32-byte chunks
|-
| '''0x15''' || '''1''' || '''X''' || '''1''' || hifreq[31:0] || Accumulated high-freq components
|-
|}

'' 333 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock0
|-
| '''2''' || sr_sda1 || I2C
|-
| '''3''' || sr_scl1 || I2C clock1
|-
| '''4..12''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''17''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''18''' || 1'b0 || 0x0
|-
| '''19''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''20''' || itrig || TRIG input
|-
| '''21..22''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)
, 01 - clock is too late
, 10 - clock is too early
, 11 - OK (some measurements show too late, some - too early)
|-
| '''23''' || dcm_done ||
|-
| '''24''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''25''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''26''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''27''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''28''' || tok_frame_num_wr || Odd/even frame of tokens written
|-
| '''29''' || 1'b0 || 0x0
|-
| '''30''' || debug_out || Debug shift register output
|-
| '''31''' || 'b0 || 0x0
|-
|}

'' 353 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2''' || sr_ch0rdy || Ready to write next page (channel 0) SENSOR->SDRAM
|-
| '''3''' || sr_ch1rdy || Ready to read next page (channel 1) SDRAM->FPN(SENSOR)
|-
| '''4''' || sr_ch2rdy || Ready to read next page (channel 2) SDRAM->DMA
|-
| '''5''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''6''' || sr_wrempty || CPU write buffer empty (valid only in write mode). May reprogram channel3.
|-
| '''7..10''' || sr_nextFrame[3:0] || (level) generated before actual block is filled - needed to be combined with the pulse from buffer control
|-
| '''11..13''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''14''' || dcc_rdy || 128 of DC components from JPEG encoder are available (same as interrupt)
|-
| '''15''' || compressor_done_input || will go high after EOT and persist until DCT is enabled
|-
| '''16''' || compressor_done_compress || will go high after all data is sent out
|-
| '''17''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''19..18''' || dcm_err[1:0] || SDRAM DCM phase error
|-
| '''20''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''21''' || dcm_locked || SDRAM DCM overflow
|-
| '''22''' || dcm_status[0] || SDRAM DCM overflow
|-
| '''24..23''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''25''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''26''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''27''' || sens_dcm_status[0] || Sensor DCM overflow
|-
| '''28''' || clockios_locked || dcm locked
|-
| '''29..30''' || clockios_status[1:0] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''31''' || 1'b0 || 0x0
|-
|}

=== Control register ===
The dcr[31:0] bus is used to control the different blocks according to the control register values. The control register can be directly written by the CPU at the address 0x00.

''333 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0..2''' || Not used ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || iobuf || EXPS (output pin)
|-
| '''12''' || iobuf || EXPS (output pin)
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || i2cpads || scl1 out
|-
| '''20''' || i2cpads || scl1 enable
|-
| '''21''' || i2cpads || sda1 out
|-
| '''22''' || i2cpads || sda1 enable
|-
| '''23''' || Not used ||
|-
| '''24..27''' || clock_pclk || pclk source
|-
| '''28..30''' || Not used ||
|-
| '''31''' || clock_pclk || clk enable
|-
|}

''353 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0''' || Not used ||
|-
| '''1..2''' || compressor, sensorpix, histogram ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || sensorpads || sensor trigger
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || sensorpads || dclkmode
|-
| '''20''' || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || Not used ||
|-
| '''24..25''' || BUFGMUX || pclk source
|-
| '''28..30''' || compressor ||
|-
| '''31''' || clock_pclk ||
|-
|}

=== Others ===
* Looks like Theora compressor requires 90° phase clock that was abandoned in the 353 design.
Using different phases reduces AC component of the current through the power/ground lines of the FPGA by spreading register transitions. Theora has larger core so it may help spreading phases.--[[User:Andrey.filippov|Andrey.filippov]] 13:45, 25 February 2008 (CST)
* ...?

== Software updates ==

* Adapt FPGA definitions ([http://elphel.cvs.sourceforge.net/elphel/elphel353/elphel353/os/linux-2.6-tag--devboard-R2_01-1/arch/cris/arch-v32/drivers/elphel/x353.h?revision=1.8&view=markup&sortdir=down x353.h]) and most likely some other FPGA drivers.
* ...?

These lists of update are obviously incomplete. They need to be more detailed in order to make an exhaustive list of the changes that have to be done.

== 353 Theora new design ==
=== Compressor ===

Writing tables in compressor (and mcontr8ch) is the same than the 333 design :
* (X313_WA_COMP_TA)ia = 0x2d and idi = table address (X313_WA_COMP_TA=0x2d)
then
* ia = 0x2c and idi = table data (X313_WA_COMP_TD=0x2c)

Example : Writing zerobin and quantization tables in 353 Theora design

[[Image:Writetabs.jpg]]

=== Sensorpix ===

Most of the 353 design was used for the new design. Writing procedure for gamma tables in sensorpix block is the same than in 353 (ie with ta bus and twr_gamma signal).

* ia = 0x0e and idi = table address

then

* ia = 0x0f and idi = table data

Table address is not autoincremented within the sensorpix block but is fed externally with the ta bus.

[[Image:Gammatab.jpg]]

=== Memory controller ===

{|border="1" cellpadding="2"
! Channel !! Description
|-
| '''0''' || 8/16 bit data from sensor to SDRAM
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor
|-
| '''3''' || PIO read/write of SDRAM data
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63]
|-
| '''7''' || Reading 12-bit pre-tokens from SDRAM in indexed coded order
|-
|}

=== System interface ===

{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm || tune SDRAM clock phase
|-
| '''0x0a''' || da_framesync_dly || write frame sync interrupt delay (in scan lines)
|-
| '''0x0e''' || da_table_a0 || write gamma table address
|-
| '''0x0f''' || twr0 || write gamma table data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts || interrupt control
|-
| '''0x20..0x27''' || da_mcontr || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc || real time clock
|-
| '''0x48''' || da_timestamp || write timestamp mode
|-
| '''0x74''' || da_xjta0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync || control of external sync module 0x78 - 0x7b
|-
|}

=== Interrupts ===

{|border="1" cellpadding="2"
! irq_in !! Signal !! Comments
|-
| '''15..8''' || GND || Extra
|-
| '''7''' || compressor_done_compress || single-cycle pulse when the compressed frame is sent out
|-
| '''6''' || compressor_reset_compress || reset compressor done interrupt (writing any compressor command)
|-
| '''5''' || GND || dcc_rdy was tied to GND in the 333 design
|-
| '''4''' || GND || eot irq was tied to GND in the 333 design
|-
| '''3''' || sr_sensortrig[2] || (sync to pclk) - level, reset by writing to sensor triggering command register
|-
| '''2''' || xfer_over_irq || (sync to pclk) - frame acquisition over
|-
| '''1''' || trig_irq || (sync to pclk) - external trigger
|-
| '''0''' || vacts || (sync to pclk) - frame sync
|-
|}

=== DMA FIFOs ===
A single DMA FIFO from the 333 design will be instanciated.

=== FPGA -> CPU data out MUX ===

{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || '''0''' || '''x''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''x''' || '''x''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''x''' || '''0''' || '''x''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''x''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''x''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''x''' || '''x''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''x''' || '''x''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

{|border="1" cellpadding="2"
! Address !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' Status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C data
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2..10''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''11''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''12''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''17..18''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)

, 01 - clock is too late , 10 - clock is too early , 11 - OK (some measurements show too late, some - too early)
|-
| '''19''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''20''' || dcm_locked || SDRAM DCM overflow
|-
| '''21..22''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''23''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''24''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''25''' || clockios_locked || dcm locked
|-
| '''26''' || clockios_status[1] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''27''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''28''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''29''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''30''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''31''' || took_frame_num_wr || Odd/even frame of tokens written
|-
|}

=== Control register ===
{|border="1" cellpadding="2"
! bit # !! Signal || Destination block !! Comments
|-
| '''0''' || || Not used ||
|-
| '''1..2''' || cb_bayer_phase || compressor, sensorpix, histogram ||
|-
| '''3''' || || sensorpads || Inverts idclk phase (Not used)
|-
| '''4''' || cb_fillfactory || sensorpads || fillfactory sensor mode
|-
| '''5''' || cb_dlyhact || sensorpads || delay hact pulse by 1
|-
| '''6''' || cb_zoran || sensorpads || ''cb_zoran''
|-
| '''7''' || cb_skipline || sensorpads || skip first scan line from the sensor
|-
| '''8''' || cb_xt_pol || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || iarst || sensorpads || ''iarst''
|-
| '''10''' || iaro || sensorpads || ''iaro''
|-
| '''11''' || cb_encnvclk || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || cb_sensor_trigger || sensorpads || sensor trigger
|-
| '''13''' || imrst || sensorpads || ''imrst''
|-
| '''14''' || cb_scl0_o || iobuf || XRST (output pin)
|-
| '''15''' || cb_scl0_o || i2cpads || scl0 out
|-
| '''16''' || cb_scl0_en || i2cpads || scl0 enable
|-
| '''17''' || cb_sda0_o || i2cpads || sda0 out
|-
| '''18''' || cb_sda0_en || i2cpads || sda0 enable
|-
| '''19''' || cb_dclkmode || sensorpads || dclkmode
|-
| '''20''' || cb_pxd14 || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || cb_latehact || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || || Not used ||
|-
| '''24..25''' || cb_pclksrc || BUFGMUX || pclk source
|-
| '''28..30''' || || Not used ||
|-
| '''31''' || || Not used ||
|-
|}

=== Others ===

== See also ==

*[http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ 353 Theora CVS]
*[[Theora]]
*[[FPGA_Development_in_Elphel_cameras|FPGA Development in Elphel cameras]]
*[[Design Ideas|FPGA Theora Encoder for Videoconferencing]]
*[[10353]]

Talk:Porting Theora to 353 cameras

2008-04-14T09:07:48Z

JeremViewsurf:

Talk:Porting Theora to 353 cameras

2008-04-11T12:53:20Z

JeremViewsurf:

File:Finaldatapath.jpg

2008-04-11T12:47:36Z

JeremViewsurf: Finally some output after the dma_fifo block

Finally some output after the dma_fifo block

Talk:Porting Theora to 353 cameras

2008-04-10T09:41:07Z

JeremViewsurf:

Porting Theora to 353 cameras

2008-04-09T15:41:33Z

JeremViewsurf: /* Sensorpix */

Elphel model 333 cameras were able to encode and stream Ogg Theora with 6.3.9 firmware. However, this model is no longer produced by Elphel. The goal of this project is to use the full potential of 353 cameras (larger FPGA, faster CPU) in order to port the Ogg Theora feature on the new hardware. First, the camera should be able to upload small Theora clips via FTP.

Different solutions are possible as previously mentioned in the [[Theora]] page :
* Instantiate both the Theora compressor and the MJPEG compressor in the FPGA since the new Spartan 3E seems to be large enough to handle the two features.
* Replace the existing MJPEG compressor with the Theora compressor and implement software Theora to JPEG conversion if JPEG is needed.
* Replace the existing MJPEG compressor in the 353 camera with the Theora compressor and keep two configuration files on the camera filesystem (one for Theora the other for MJPEG). FPGA code could be changed at run-time according to the needs.

Dealing with the last solution seems to be a good start for this project as the other features mentioned can be added later. In all cases, both FPGA code and software code will need to be adapted.

The source code of this project is available at [http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/]
== Hardware updates ==

=== Compressor ===
[[Image:Schematic.png|frame|[[Media:Schematic.png|333 Theora design with the 2 stage compressor and the 8-channel memory controller]]]]
Replace the MJPEG compressor in the 353 with the 333 Theora compressor ([http://elphel.cvs.sourceforge.net/elphel/camera333/fpga/x333 333 Theora FPGA code]). Maybe some adaptations need to be done within the Theora compressor itself. However, assuming that the compressor worked in 333 cameras a simple instantiation should suffice.

=== Memory controller ===
Replace the 4-channel memory controller with an 8 channel memory interface as in the 333 model in order to handle Theora specific data.

{|border="1" cellpadding="2"
! Channel !! 333 Theora !! 353
|-
| '''0''' || 8/16 bit data from sensor to SDRAM || Data from the sensor (it can be combined with FPN correction data) to the SDRAM in either 8-bit mode or 16-bit
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module || Reads FPN data from SDRAM (8bit - subtract, 8 bit - scale) and feeds it to FPGA for FPN correction of the data on the way from sensor to SDRAM (through channel 0)
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor || Provides data to JPEG encoder in 16x16x8bit MCUs. It can also provide data directly to CPU through DMA bypassing any compression
|-
| '''3''' || PIO read/write of SDRAM data || Provides bidirectional access from CPU through 8x32 bit window.
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM ||
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM ||
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63] ||
|-
| '''7''' || reading 12-bit pre-tokens from SDRAM in indexed coded order ||
|-
|}

=== Sensor interface ===
''sensorpix'' block must be adapted in order to provide a coherent interface between the memory controller and the sensor (channels 0 and 1)

=== System Interface ===
Adapt the system interface to assure communication between FPGA and its environment.

A feature of the system interface is to establish communication between the system CPU and the different blocks within the FPGA (compressor, memory controller etc). This is done by selecting a block with the address bus ''a[12:0]'' connected to the internal address bus ''ial[7:0]'':

'''x353.v'''
always @ (posedge cwr) begin
a0[7:0]<=ial[7:0]; // may want to change to just ia if ia will be late enough;
wnr0 <= ~irnw;
da_ctl0 <= (ial[7:0]==8'h00); // 0x00 WE to control 32-bit register (1 loc)
da_dmamode0 <= (ial[7:0]==8'h01); // 0x01 select writing to dma_cntr/dma_raw (1 loc)
da_sensormode0 <= (ial[7:0]==8'h02); // 0x02 select writing to sensorpix (1 loc)
...
da_compressor0 <= (ial[7:1]==7'h06); // 0x0c..0x0d - will be farther decoded in the compressor module
...

Since memory controller and compressor are to be replaced these addresses have to be adapted.

''353 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x09''' || da_saturation0 || write color saturation values
|-
| '''0x0a''' || da_framesync_dly0 || write frame sync interrupt delay (in scan lines)
|-
| '''0x0c..0x0d''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x0e''' || da_table_a0 || write tables address
|-
| '''0x0f''' || twr0 || write tables data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts0 || interrupt control
|-
| '''0x20..0x2f''' || da_dswe0 || select reading/writing to mcontr (16 locations)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist0 || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc0 || real time clock
|-
| '''0x48''' || da_timestamp0 || write timestamp mode
|-
| '''0x74''' || da_xjtag0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync0 || control of external sync module 0x78 - 0x7b
|-
|}

''333 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or aftre trigger)
|-
| '''0x06''' || da_interrupts0 || interrupt mask
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x10''' || da_debug || write 0x10 any - load debug shift, read (through cs4) -shift
|-
| '''0x20..0x27''' || da_mcontr0 || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table0 || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
|}

Addresses 0x01,2,3,4,5,6,8 and 0x30 can be kept in the 353 system interface. The interrupt mask address 0x06 in the 333 sys interface is no longer used (353 uses interrupt vectors). The Theora compressor and the new memory controller addresses have to be mapped again in the new design (addresses 0x0c..0x0d and 0x20 to 0x2f in the 353 sys interface).

=== Interrupts ===
Adapt the Theora compressor interrupts to the 353 interrupt vector .

The 353 interrupt vector can handle up to 16 different irq. However, only irq 0 to 7 are used :
'''x353.v'''

assign irq_in= {8'b0, // extra
compressor_done_compress, // 7 - will go high after all data is sent out (reset by compressor)
compressor_done_input, // 6 - will go high after EOT and persist until DCT is enabled (reset by compressor)
dcc_rdy, // 5 - obsolete in 333 - channel3 has 128 more dc coefficients (or some if the compression is finished)
compressor_eot, // 4 - compressor read in the last MCU (predictable time to end of transfer)
sr_sensortrig[2], // 3 - (sync to pclk) - level, reset by writing to sensor triggering command register
xfer_over_irq, // 2 - (sync to pclk) - frame acquisition over
trig_irq, // 1 - (sync to pclk) - external trigger
vacts}; // 0 - (sync to pclk) - frame sync

353 MJPEG compressor triggers irqs 4, 6 and 7. 333 Theora compressor is the source of two irqs :
'''compressor_all.v'''

done, // single-cycle pulse when the compressed frame is sent out (IRQ source).
reset_compress, // reset compressor done interrupt (writing any compressor command)

Adaptation should consist of assigning Theora compressor irq sources to vectors 6 and 7 for example if the MJPEG compressor is to be replaced.

=== DMA FIFOs ===
353 design uses 2 DMA FIFOs between the compressor and the system interface instead of one for the 333 Theora compressor. The two DMA FIFOs have also slight differences between the two design. Maybe a single 333 FIFO should be kept for the final design (?)

=== FPGA -> CPU data out MUX ===
The purpose of this MUX is to route data out from the different FPGA blocks to the system interface and then to the data bus to the CPU. The selection is made with the internal address bus ''ia''.
_
--| \
--| |
--| |
--| |--- iod[31:0] -> to system interface
--| |
--| |
|_/
from system interface -> ia[7:0]__|

'' 333 MUX ''
{|border="1" cellpadding="2"
! Adress range !! ia(5) !! ia(4) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''1''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''1''' || '''0''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''1''' || '''1''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0.. (even)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''0''' || dma_d0[31:0] || DMA 0 data
|-
| '''0x0.. (odd)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''1''' || dma_d1[31:0] || DMA 1 data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''X''' || '''X''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''X''' || '''X''' || dsdo[31:0] || Data out from descriptor memory
|-
| '''0x3..''' || '''0''' || '''1''' || '''1''' || '''X''' || '''X''' || bdo[31:0] || 32-bit data from SDRAM channel3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''X''' || '''0''' || '''X''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''X''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''X''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''X''' || '''X''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''X''' || '''X''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

'' 333 MUX ''
{|border="1" cellpadding="2"
! Address || ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || {24'b0,irqr[7:0]} || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(2) !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''0''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''0''' || '''1''' || '''1''' || MODELREV || Model revision
|-
| '''0x14''' || '''1''' || '''X''' || '''0''' || {8'h0,imgptr[23:0]} || Image pointer in 32-byte chunks
|-
| '''0x15''' || '''1''' || '''X''' || '''1''' || hifreq[31:0] || Accumulated high-freq components
|-
|}

'' 333 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock0
|-
| '''2''' || sr_sda1 || I2C
|-
| '''3''' || sr_scl1 || I2C clock1
|-
| '''4..12''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''17''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''18''' || 1'b0 || 0x0
|-
| '''19''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''20''' || itrig || TRIG input
|-
| '''21..22''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)
, 01 - clock is too late
, 10 - clock is too early
, 11 - OK (some measurements show too late, some - too early)
|-
| '''23''' || dcm_done ||
|-
| '''24''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''25''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''26''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''27''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''28''' || tok_frame_num_wr || Odd/even frame of tokens written
|-
| '''29''' || 1'b0 || 0x0
|-
| '''30''' || debug_out || Debug shift register output
|-
| '''31''' || 'b0 || 0x0
|-
|}

'' 353 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2''' || sr_ch0rdy || Ready to write next page (channel 0) SENSOR->SDRAM
|-
| '''3''' || sr_ch1rdy || Ready to read next page (channel 1) SDRAM->FPN(SENSOR)
|-
| '''4''' || sr_ch2rdy || Ready to read next page (channel 2) SDRAM->DMA
|-
| '''5''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''6''' || sr_wrempty || CPU write buffer empty (valid only in write mode). May reprogram channel3.
|-
| '''7..10''' || sr_nextFrame[3:0] || (level) generated before actual block is filled - needed to be combined with the pulse from buffer control
|-
| '''11..13''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''14''' || dcc_rdy || 128 of DC components from JPEG encoder are available (same as interrupt)
|-
| '''15''' || compressor_done_input || will go high after EOT and persist until DCT is enabled
|-
| '''16''' || compressor_done_compress || will go high after all data is sent out
|-
| '''17''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''19..18''' || dcm_err[1:0] || SDRAM DCM phase error
|-
| '''20''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''21''' || dcm_locked || SDRAM DCM overflow
|-
| '''22''' || dcm_status[0] || SDRAM DCM overflow
|-
| '''24..23''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''25''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''26''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''27''' || sens_dcm_status[0] || Sensor DCM overflow
|-
| '''28''' || clockios_locked || dcm locked
|-
| '''29..30''' || clockios_status[1:0] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''31''' || 1'b0 || 0x0
|-
|}

=== Control register ===
The dcr[31:0] bus is used to control the different blocks according to the control register values. The control register can be directly written by the CPU at the address 0x00.

''333 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0..2''' || Not used ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || iobuf || EXPS (output pin)
|-
| '''12''' || iobuf || EXPS (output pin)
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || i2cpads || scl1 out
|-
| '''20''' || i2cpads || scl1 enable
|-
| '''21''' || i2cpads || sda1 out
|-
| '''22''' || i2cpads || sda1 enable
|-
| '''23''' || Not used ||
|-
| '''24..27''' || clock_pclk || pclk source
|-
| '''28..30''' || Not used ||
|-
| '''31''' || clock_pclk || clk enable
|-
|}

''353 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0''' || Not used ||
|-
| '''1..2''' || compressor, sensorpix, histogram ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || sensorpads || sensor trigger
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || sensorpads || dclkmode
|-
| '''20''' || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || Not used ||
|-
| '''24..25''' || BUFGMUX || pclk source
|-
| '''28..30''' || compressor ||
|-
| '''31''' || clock_pclk ||
|-
|}

=== Others ===
* Looks like Theora compressor requires 90° phase clock that was abandoned in the 353 design.
Using different phases reduces AC component of the current through the power/ground lines of the FPGA by spreading register transitions. Theora has larger core so it may help spreading phases.--[[User:Andrey.filippov|Andrey.filippov]] 13:45, 25 February 2008 (CST)
* ...?

== Software updates ==

* Adapt FPGA definitions ([http://elphel.cvs.sourceforge.net/elphel/elphel353/elphel353/os/linux-2.6-tag--devboard-R2_01-1/arch/cris/arch-v32/drivers/elphel/x353.h?revision=1.8&view=markup&sortdir=down x353.h]) and most likely some other FPGA drivers.
* ...?

These lists of update are obviously incomplete. They need to be more detailed in order to make an exhaustive list of the changes that have to be done.

== 353 Theora new design ==
=== Compressor ===

Writing tables in compressor (and mcontr8ch) is the same than the 333 design :
* ia = 0x2d and idi = table address
then
* ia = 0x2c and idi = table data

Example : Writing zerobin and quantization tables in 353 Theora design

[[Image:Writetabs.jpg]]

=== Sensorpix ===

Most of the 353 design was used for the new design. Writing procedure for gamma tables in sensorpix block is the same than in 353 (ie with ta bus and twr_gamma signal).

* ia = 0x0e and idi = table address

then

* ia = 0x0f and idi = table data

Table address is not autoincremented within the sensorpix block but is fed externally with the ta bus.

[[Image:Gammatab.jpg]]

=== Memory controller ===

{|border="1" cellpadding="2"
! Channel !! Description
|-
| '''0''' || 8/16 bit data from sensor to SDRAM
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor
|-
| '''3''' || PIO read/write of SDRAM data
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63]
|-
| '''7''' || Reading 12-bit pre-tokens from SDRAM in indexed coded order
|-
|}

=== System interface ===

{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm || tune SDRAM clock phase
|-
| '''0x0a''' || da_framesync_dly || write frame sync interrupt delay (in scan lines)
|-
| '''0x0e''' || da_table_a0 || write gamma table address
|-
| '''0x0f''' || twr0 || write gamma table data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts || interrupt control
|-
| '''0x20..0x27''' || da_mcontr || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc || real time clock
|-
| '''0x48''' || da_timestamp || write timestamp mode
|-
| '''0x74''' || da_xjta0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync || control of external sync module 0x78 - 0x7b
|-
|}

=== Interrupts ===

{|border="1" cellpadding="2"
! irq_in !! Signal !! Comments
|-
| '''15..8''' || GND || Extra
|-
| '''7''' || compressor_done_compress || single-cycle pulse when the compressed frame is sent out
|-
| '''6''' || compressor_reset_compress || reset compressor done interrupt (writing any compressor command)
|-
| '''5''' || GND || dcc_rdy was tied to GND in the 333 design
|-
| '''4''' || GND || eot irq was tied to GND in the 333 design
|-
| '''3''' || sr_sensortrig[2] || (sync to pclk) - level, reset by writing to sensor triggering command register
|-
| '''2''' || xfer_over_irq || (sync to pclk) - frame acquisition over
|-
| '''1''' || trig_irq || (sync to pclk) - external trigger
|-
| '''0''' || vacts || (sync to pclk) - frame sync
|-
|}

=== DMA FIFOs ===
A single DMA FIFO from the 333 design will be instanciated.

=== FPGA -> CPU data out MUX ===

{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || '''0''' || '''x''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''x''' || '''x''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''x''' || '''0''' || '''x''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''x''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''x''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''x''' || '''x''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''x''' || '''x''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

{|border="1" cellpadding="2"
! Address !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' Status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C data
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2..10''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''11''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''12''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''17..18''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)

, 01 - clock is too late , 10 - clock is too early , 11 - OK (some measurements show too late, some - too early)
|-
| '''19''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''20''' || dcm_locked || SDRAM DCM overflow
|-
| '''21..22''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''23''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''24''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''25''' || clockios_locked || dcm locked
|-
| '''26''' || clockios_status[1] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''27''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''28''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''29''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''30''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''31''' || took_frame_num_wr || Odd/even frame of tokens written
|-
|}

=== Control register ===
{|border="1" cellpadding="2"
! bit # !! Signal || Destination block !! Comments
|-
| '''0''' || || Not used ||
|-
| '''1..2''' || cb_bayer_phase || compressor, sensorpix, histogram ||
|-
| '''3''' || || sensorpads || Inverts idclk phase (Not used)
|-
| '''4''' || cb_fillfactory || sensorpads || fillfactory sensor mode
|-
| '''5''' || cb_dlyhact || sensorpads || delay hact pulse by 1
|-
| '''6''' || cb_zoran || sensorpads || ''cb_zoran''
|-
| '''7''' || cb_skipline || sensorpads || skip first scan line from the sensor
|-
| '''8''' || cb_xt_pol || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || iarst || sensorpads || ''iarst''
|-
| '''10''' || iaro || sensorpads || ''iaro''
|-
| '''11''' || cb_encnvclk || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || cb_sensor_trigger || sensorpads || sensor trigger
|-
| '''13''' || imrst || sensorpads || ''imrst''
|-
| '''14''' || cb_scl0_o || iobuf || XRST (output pin)
|-
| '''15''' || cb_scl0_o || i2cpads || scl0 out
|-
| '''16''' || cb_scl0_en || i2cpads || scl0 enable
|-
| '''17''' || cb_sda0_o || i2cpads || sda0 out
|-
| '''18''' || cb_sda0_en || i2cpads || sda0 enable
|-
| '''19''' || cb_dclkmode || sensorpads || dclkmode
|-
| '''20''' || cb_pxd14 || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || cb_latehact || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || || Not used ||
|-
| '''24..25''' || cb_pclksrc || BUFGMUX || pclk source
|-
| '''28..30''' || || Not used ||
|-
| '''31''' || || Not used ||
|-
|}

=== Others ===

== See also ==

*[http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ 353 Theora CVS]
*[[Theora]]
*[[FPGA_Development_in_Elphel_cameras|FPGA Development in Elphel cameras]]
*[[Design Ideas|FPGA Theora Encoder for Videoconferencing]]
*[[10353]]

Porting Theora to 353 cameras

2008-04-09T15:41:05Z

JeremViewsurf: /* Sensorpix */

Elphel model 333 cameras were able to encode and stream Ogg Theora with 6.3.9 firmware. However, this model is no longer produced by Elphel. The goal of this project is to use the full potential of 353 cameras (larger FPGA, faster CPU) in order to port the Ogg Theora feature on the new hardware. First, the camera should be able to upload small Theora clips via FTP.

Different solutions are possible as previously mentioned in the [[Theora]] page :
* Instantiate both the Theora compressor and the MJPEG compressor in the FPGA since the new Spartan 3E seems to be large enough to handle the two features.
* Replace the existing MJPEG compressor with the Theora compressor and implement software Theora to JPEG conversion if JPEG is needed.
* Replace the existing MJPEG compressor in the 353 camera with the Theora compressor and keep two configuration files on the camera filesystem (one for Theora the other for MJPEG). FPGA code could be changed at run-time according to the needs.

Dealing with the last solution seems to be a good start for this project as the other features mentioned can be added later. In all cases, both FPGA code and software code will need to be adapted.

The source code of this project is available at [http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/]
== Hardware updates ==

=== Compressor ===
[[Image:Schematic.png|frame|[[Media:Schematic.png|333 Theora design with the 2 stage compressor and the 8-channel memory controller]]]]
Replace the MJPEG compressor in the 353 with the 333 Theora compressor ([http://elphel.cvs.sourceforge.net/elphel/camera333/fpga/x333 333 Theora FPGA code]). Maybe some adaptations need to be done within the Theora compressor itself. However, assuming that the compressor worked in 333 cameras a simple instantiation should suffice.

=== Memory controller ===
Replace the 4-channel memory controller with an 8 channel memory interface as in the 333 model in order to handle Theora specific data.

{|border="1" cellpadding="2"
! Channel !! 333 Theora !! 353
|-
| '''0''' || 8/16 bit data from sensor to SDRAM || Data from the sensor (it can be combined with FPN correction data) to the SDRAM in either 8-bit mode or 16-bit
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module || Reads FPN data from SDRAM (8bit - subtract, 8 bit - scale) and feeds it to FPGA for FPN correction of the data on the way from sensor to SDRAM (through channel 0)
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor || Provides data to JPEG encoder in 16x16x8bit MCUs. It can also provide data directly to CPU through DMA bypassing any compression
|-
| '''3''' || PIO read/write of SDRAM data || Provides bidirectional access from CPU through 8x32 bit window.
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM ||
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM ||
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63] ||
|-
| '''7''' || reading 12-bit pre-tokens from SDRAM in indexed coded order ||
|-
|}

=== Sensor interface ===
''sensorpix'' block must be adapted in order to provide a coherent interface between the memory controller and the sensor (channels 0 and 1)

=== System Interface ===
Adapt the system interface to assure communication between FPGA and its environment.

A feature of the system interface is to establish communication between the system CPU and the different blocks within the FPGA (compressor, memory controller etc). This is done by selecting a block with the address bus ''a[12:0]'' connected to the internal address bus ''ial[7:0]'':

'''x353.v'''
always @ (posedge cwr) begin
a0[7:0]<=ial[7:0]; // may want to change to just ia if ia will be late enough;
wnr0 <= ~irnw;
da_ctl0 <= (ial[7:0]==8'h00); // 0x00 WE to control 32-bit register (1 loc)
da_dmamode0 <= (ial[7:0]==8'h01); // 0x01 select writing to dma_cntr/dma_raw (1 loc)
da_sensormode0 <= (ial[7:0]==8'h02); // 0x02 select writing to sensorpix (1 loc)
...
da_compressor0 <= (ial[7:1]==7'h06); // 0x0c..0x0d - will be farther decoded in the compressor module
...

Since memory controller and compressor are to be replaced these addresses have to be adapted.

''353 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x09''' || da_saturation0 || write color saturation values
|-
| '''0x0a''' || da_framesync_dly0 || write frame sync interrupt delay (in scan lines)
|-
| '''0x0c..0x0d''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x0e''' || da_table_a0 || write tables address
|-
| '''0x0f''' || twr0 || write tables data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts0 || interrupt control
|-
| '''0x20..0x2f''' || da_dswe0 || select reading/writing to mcontr (16 locations)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist0 || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc0 || real time clock
|-
| '''0x48''' || da_timestamp0 || write timestamp mode
|-
| '''0x74''' || da_xjtag0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync0 || control of external sync module 0x78 - 0x7b
|-
|}

''333 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or aftre trigger)
|-
| '''0x06''' || da_interrupts0 || interrupt mask
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x10''' || da_debug || write 0x10 any - load debug shift, read (through cs4) -shift
|-
| '''0x20..0x27''' || da_mcontr0 || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table0 || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
|}

Addresses 0x01,2,3,4,5,6,8 and 0x30 can be kept in the 353 system interface. The interrupt mask address 0x06 in the 333 sys interface is no longer used (353 uses interrupt vectors). The Theora compressor and the new memory controller addresses have to be mapped again in the new design (addresses 0x0c..0x0d and 0x20 to 0x2f in the 353 sys interface).

=== Interrupts ===
Adapt the Theora compressor interrupts to the 353 interrupt vector .

The 353 interrupt vector can handle up to 16 different irq. However, only irq 0 to 7 are used :
'''x353.v'''

assign irq_in= {8'b0, // extra
compressor_done_compress, // 7 - will go high after all data is sent out (reset by compressor)
compressor_done_input, // 6 - will go high after EOT and persist until DCT is enabled (reset by compressor)
dcc_rdy, // 5 - obsolete in 333 - channel3 has 128 more dc coefficients (or some if the compression is finished)
compressor_eot, // 4 - compressor read in the last MCU (predictable time to end of transfer)
sr_sensortrig[2], // 3 - (sync to pclk) - level, reset by writing to sensor triggering command register
xfer_over_irq, // 2 - (sync to pclk) - frame acquisition over
trig_irq, // 1 - (sync to pclk) - external trigger
vacts}; // 0 - (sync to pclk) - frame sync

353 MJPEG compressor triggers irqs 4, 6 and 7. 333 Theora compressor is the source of two irqs :
'''compressor_all.v'''

done, // single-cycle pulse when the compressed frame is sent out (IRQ source).
reset_compress, // reset compressor done interrupt (writing any compressor command)

Adaptation should consist of assigning Theora compressor irq sources to vectors 6 and 7 for example if the MJPEG compressor is to be replaced.

=== DMA FIFOs ===
353 design uses 2 DMA FIFOs between the compressor and the system interface instead of one for the 333 Theora compressor. The two DMA FIFOs have also slight differences between the two design. Maybe a single 333 FIFO should be kept for the final design (?)

=== FPGA -> CPU data out MUX ===
The purpose of this MUX is to route data out from the different FPGA blocks to the system interface and then to the data bus to the CPU. The selection is made with the internal address bus ''ia''.
_
--| \
--| |
--| |
--| |--- iod[31:0] -> to system interface
--| |
--| |
|_/
from system interface -> ia[7:0]__|

'' 333 MUX ''
{|border="1" cellpadding="2"
! Adress range !! ia(5) !! ia(4) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''1''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''1''' || '''0''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''1''' || '''1''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0.. (even)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''0''' || dma_d0[31:0] || DMA 0 data
|-
| '''0x0.. (odd)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''1''' || dma_d1[31:0] || DMA 1 data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''X''' || '''X''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''X''' || '''X''' || dsdo[31:0] || Data out from descriptor memory
|-
| '''0x3..''' || '''0''' || '''1''' || '''1''' || '''X''' || '''X''' || bdo[31:0] || 32-bit data from SDRAM channel3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''X''' || '''0''' || '''X''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''X''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''X''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''X''' || '''X''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''X''' || '''X''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

'' 333 MUX ''
{|border="1" cellpadding="2"
! Address || ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || {24'b0,irqr[7:0]} || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(2) !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''0''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''0''' || '''1''' || '''1''' || MODELREV || Model revision
|-
| '''0x14''' || '''1''' || '''X''' || '''0''' || {8'h0,imgptr[23:0]} || Image pointer in 32-byte chunks
|-
| '''0x15''' || '''1''' || '''X''' || '''1''' || hifreq[31:0] || Accumulated high-freq components
|-
|}

'' 333 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock0
|-
| '''2''' || sr_sda1 || I2C
|-
| '''3''' || sr_scl1 || I2C clock1
|-
| '''4..12''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''17''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''18''' || 1'b0 || 0x0
|-
| '''19''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''20''' || itrig || TRIG input
|-
| '''21..22''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)
, 01 - clock is too late
, 10 - clock is too early
, 11 - OK (some measurements show too late, some - too early)
|-
| '''23''' || dcm_done ||
|-
| '''24''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''25''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''26''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''27''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''28''' || tok_frame_num_wr || Odd/even frame of tokens written
|-
| '''29''' || 1'b0 || 0x0
|-
| '''30''' || debug_out || Debug shift register output
|-
| '''31''' || 'b0 || 0x0
|-
|}

'' 353 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2''' || sr_ch0rdy || Ready to write next page (channel 0) SENSOR->SDRAM
|-
| '''3''' || sr_ch1rdy || Ready to read next page (channel 1) SDRAM->FPN(SENSOR)
|-
| '''4''' || sr_ch2rdy || Ready to read next page (channel 2) SDRAM->DMA
|-
| '''5''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''6''' || sr_wrempty || CPU write buffer empty (valid only in write mode). May reprogram channel3.
|-
| '''7..10''' || sr_nextFrame[3:0] || (level) generated before actual block is filled - needed to be combined with the pulse from buffer control
|-
| '''11..13''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''14''' || dcc_rdy || 128 of DC components from JPEG encoder are available (same as interrupt)
|-
| '''15''' || compressor_done_input || will go high after EOT and persist until DCT is enabled
|-
| '''16''' || compressor_done_compress || will go high after all data is sent out
|-
| '''17''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''19..18''' || dcm_err[1:0] || SDRAM DCM phase error
|-
| '''20''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''21''' || dcm_locked || SDRAM DCM overflow
|-
| '''22''' || dcm_status[0] || SDRAM DCM overflow
|-
| '''24..23''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''25''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''26''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''27''' || sens_dcm_status[0] || Sensor DCM overflow
|-
| '''28''' || clockios_locked || dcm locked
|-
| '''29..30''' || clockios_status[1:0] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''31''' || 1'b0 || 0x0
|-
|}

=== Control register ===
The dcr[31:0] bus is used to control the different blocks according to the control register values. The control register can be directly written by the CPU at the address 0x00.

''333 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0..2''' || Not used ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || iobuf || EXPS (output pin)
|-
| '''12''' || iobuf || EXPS (output pin)
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || i2cpads || scl1 out
|-
| '''20''' || i2cpads || scl1 enable
|-
| '''21''' || i2cpads || sda1 out
|-
| '''22''' || i2cpads || sda1 enable
|-
| '''23''' || Not used ||
|-
| '''24..27''' || clock_pclk || pclk source
|-
| '''28..30''' || Not used ||
|-
| '''31''' || clock_pclk || clk enable
|-
|}

''353 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0''' || Not used ||
|-
| '''1..2''' || compressor, sensorpix, histogram ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || sensorpads || sensor trigger
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || sensorpads || dclkmode
|-
| '''20''' || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || Not used ||
|-
| '''24..25''' || BUFGMUX || pclk source
|-
| '''28..30''' || compressor ||
|-
| '''31''' || clock_pclk ||
|-
|}

=== Others ===
* Looks like Theora compressor requires 90° phase clock that was abandoned in the 353 design.
Using different phases reduces AC component of the current through the power/ground lines of the FPGA by spreading register transitions. Theora has larger core so it may help spreading phases.--[[User:Andrey.filippov|Andrey.filippov]] 13:45, 25 February 2008 (CST)
* ...?

== Software updates ==

* Adapt FPGA definitions ([http://elphel.cvs.sourceforge.net/elphel/elphel353/elphel353/os/linux-2.6-tag--devboard-R2_01-1/arch/cris/arch-v32/drivers/elphel/x353.h?revision=1.8&view=markup&sortdir=down x353.h]) and most likely some other FPGA drivers.
* ...?

These lists of update are obviously incomplete. They need to be more detailed in order to make an exhaustive list of the changes that have to be done.

== 353 Theora new design ==
=== Compressor ===

Writing tables in compressor (and mcontr8ch) is the same than the 333 design :
* ia = 0x2d and idi = table address
then
* ia = 0x2c and idi = table data

Example : Writing zerobin and quantization tables in 353 Theora design

[[Image:Writetabs.jpg]]

=== Sensorpix ===

Most of the 353 design was used for the new design. Writing procedure for gamma tables in sensorpix block is the same than in 353 (ie with ta bus and twr_gamma signal).

* ia = 0x0e and idi = table address

then

* ia = 0x0f and idi = table data

Table address is not autoincremented within the sensorpix block but is fed externally with the ta bus.

[[Image:.Gammatab.jpg]]

=== Memory controller ===

{|border="1" cellpadding="2"
! Channel !! Description
|-
| '''0''' || 8/16 bit data from sensor to SDRAM
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor
|-
| '''3''' || PIO read/write of SDRAM data
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63]
|-
| '''7''' || Reading 12-bit pre-tokens from SDRAM in indexed coded order
|-
|}

=== System interface ===

{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm || tune SDRAM clock phase
|-
| '''0x0a''' || da_framesync_dly || write frame sync interrupt delay (in scan lines)
|-
| '''0x0e''' || da_table_a0 || write gamma table address
|-
| '''0x0f''' || twr0 || write gamma table data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts || interrupt control
|-
| '''0x20..0x27''' || da_mcontr || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc || real time clock
|-
| '''0x48''' || da_timestamp || write timestamp mode
|-
| '''0x74''' || da_xjta0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync || control of external sync module 0x78 - 0x7b
|-
|}

=== Interrupts ===

{|border="1" cellpadding="2"
! irq_in !! Signal !! Comments
|-
| '''15..8''' || GND || Extra
|-
| '''7''' || compressor_done_compress || single-cycle pulse when the compressed frame is sent out
|-
| '''6''' || compressor_reset_compress || reset compressor done interrupt (writing any compressor command)
|-
| '''5''' || GND || dcc_rdy was tied to GND in the 333 design
|-
| '''4''' || GND || eot irq was tied to GND in the 333 design
|-
| '''3''' || sr_sensortrig[2] || (sync to pclk) - level, reset by writing to sensor triggering command register
|-
| '''2''' || xfer_over_irq || (sync to pclk) - frame acquisition over
|-
| '''1''' || trig_irq || (sync to pclk) - external trigger
|-
| '''0''' || vacts || (sync to pclk) - frame sync
|-
|}

=== DMA FIFOs ===
A single DMA FIFO from the 333 design will be instanciated.

=== FPGA -> CPU data out MUX ===

{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || '''0''' || '''x''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''x''' || '''x''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''x''' || '''0''' || '''x''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''x''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''x''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''x''' || '''x''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''x''' || '''x''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

{|border="1" cellpadding="2"
! Address !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' Status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C data
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2..10''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''11''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''12''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''17..18''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)

, 01 - clock is too late , 10 - clock is too early , 11 - OK (some measurements show too late, some - too early)
|-
| '''19''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''20''' || dcm_locked || SDRAM DCM overflow
|-
| '''21..22''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''23''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''24''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''25''' || clockios_locked || dcm locked
|-
| '''26''' || clockios_status[1] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''27''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''28''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''29''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''30''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''31''' || took_frame_num_wr || Odd/even frame of tokens written
|-
|}

=== Control register ===
{|border="1" cellpadding="2"
! bit # !! Signal || Destination block !! Comments
|-
| '''0''' || || Not used ||
|-
| '''1..2''' || cb_bayer_phase || compressor, sensorpix, histogram ||
|-
| '''3''' || || sensorpads || Inverts idclk phase (Not used)
|-
| '''4''' || cb_fillfactory || sensorpads || fillfactory sensor mode
|-
| '''5''' || cb_dlyhact || sensorpads || delay hact pulse by 1
|-
| '''6''' || cb_zoran || sensorpads || ''cb_zoran''
|-
| '''7''' || cb_skipline || sensorpads || skip first scan line from the sensor
|-
| '''8''' || cb_xt_pol || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || iarst || sensorpads || ''iarst''
|-
| '''10''' || iaro || sensorpads || ''iaro''
|-
| '''11''' || cb_encnvclk || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || cb_sensor_trigger || sensorpads || sensor trigger
|-
| '''13''' || imrst || sensorpads || ''imrst''
|-
| '''14''' || cb_scl0_o || iobuf || XRST (output pin)
|-
| '''15''' || cb_scl0_o || i2cpads || scl0 out
|-
| '''16''' || cb_scl0_en || i2cpads || scl0 enable
|-
| '''17''' || cb_sda0_o || i2cpads || sda0 out
|-
| '''18''' || cb_sda0_en || i2cpads || sda0 enable
|-
| '''19''' || cb_dclkmode || sensorpads || dclkmode
|-
| '''20''' || cb_pxd14 || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || cb_latehact || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || || Not used ||
|-
| '''24..25''' || cb_pclksrc || BUFGMUX || pclk source
|-
| '''28..30''' || || Not used ||
|-
| '''31''' || || Not used ||
|-
|}

=== Others ===

== See also ==

*[http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ 353 Theora CVS]
*[[Theora]]
*[[FPGA_Development_in_Elphel_cameras|FPGA Development in Elphel cameras]]
*[[Design Ideas|FPGA Theora Encoder for Videoconferencing]]
*[[10353]]

File:Gammatab.jpg

2008-04-09T15:40:50Z

JeremViewsurf: Writing gamma tables in sensorpix block

Writing gamma tables in sensorpix block

Porting Theora to 353 cameras

2008-04-09T15:37:17Z

JeremViewsurf: /* Compressor */

Elphel model 333 cameras were able to encode and stream Ogg Theora with 6.3.9 firmware. However, this model is no longer produced by Elphel. The goal of this project is to use the full potential of 353 cameras (larger FPGA, faster CPU) in order to port the Ogg Theora feature on the new hardware. First, the camera should be able to upload small Theora clips via FTP.

Different solutions are possible as previously mentioned in the [[Theora]] page :
* Instantiate both the Theora compressor and the MJPEG compressor in the FPGA since the new Spartan 3E seems to be large enough to handle the two features.
* Replace the existing MJPEG compressor with the Theora compressor and implement software Theora to JPEG conversion if JPEG is needed.
* Replace the existing MJPEG compressor in the 353 camera with the Theora compressor and keep two configuration files on the camera filesystem (one for Theora the other for MJPEG). FPGA code could be changed at run-time according to the needs.

Dealing with the last solution seems to be a good start for this project as the other features mentioned can be added later. In all cases, both FPGA code and software code will need to be adapted.

The source code of this project is available at [http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/]
== Hardware updates ==

=== Compressor ===
[[Image:Schematic.png|frame|[[Media:Schematic.png|333 Theora design with the 2 stage compressor and the 8-channel memory controller]]]]
Replace the MJPEG compressor in the 353 with the 333 Theora compressor ([http://elphel.cvs.sourceforge.net/elphel/camera333/fpga/x333 333 Theora FPGA code]). Maybe some adaptations need to be done within the Theora compressor itself. However, assuming that the compressor worked in 333 cameras a simple instantiation should suffice.

=== Memory controller ===
Replace the 4-channel memory controller with an 8 channel memory interface as in the 333 model in order to handle Theora specific data.

{|border="1" cellpadding="2"
! Channel !! 333 Theora !! 353
|-
| '''0''' || 8/16 bit data from sensor to SDRAM || Data from the sensor (it can be combined with FPN correction data) to the SDRAM in either 8-bit mode or 16-bit
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module || Reads FPN data from SDRAM (8bit - subtract, 8 bit - scale) and feeds it to FPGA for FPN correction of the data on the way from sensor to SDRAM (through channel 0)
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor || Provides data to JPEG encoder in 16x16x8bit MCUs. It can also provide data directly to CPU through DMA bypassing any compression
|-
| '''3''' || PIO read/write of SDRAM data || Provides bidirectional access from CPU through 8x32 bit window.
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM ||
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM ||
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63] ||
|-
| '''7''' || reading 12-bit pre-tokens from SDRAM in indexed coded order ||
|-
|}

=== Sensor interface ===
''sensorpix'' block must be adapted in order to provide a coherent interface between the memory controller and the sensor (channels 0 and 1)

=== System Interface ===
Adapt the system interface to assure communication between FPGA and its environment.

A feature of the system interface is to establish communication between the system CPU and the different blocks within the FPGA (compressor, memory controller etc). This is done by selecting a block with the address bus ''a[12:0]'' connected to the internal address bus ''ial[7:0]'':

'''x353.v'''
always @ (posedge cwr) begin
a0[7:0]<=ial[7:0]; // may want to change to just ia if ia will be late enough;
wnr0 <= ~irnw;
da_ctl0 <= (ial[7:0]==8'h00); // 0x00 WE to control 32-bit register (1 loc)
da_dmamode0 <= (ial[7:0]==8'h01); // 0x01 select writing to dma_cntr/dma_raw (1 loc)
da_sensormode0 <= (ial[7:0]==8'h02); // 0x02 select writing to sensorpix (1 loc)
...
da_compressor0 <= (ial[7:1]==7'h06); // 0x0c..0x0d - will be farther decoded in the compressor module
...

Since memory controller and compressor are to be replaced these addresses have to be adapted.

''353 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x09''' || da_saturation0 || write color saturation values
|-
| '''0x0a''' || da_framesync_dly0 || write frame sync interrupt delay (in scan lines)
|-
| '''0x0c..0x0d''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x0e''' || da_table_a0 || write tables address
|-
| '''0x0f''' || twr0 || write tables data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts0 || interrupt control
|-
| '''0x20..0x2f''' || da_dswe0 || select reading/writing to mcontr (16 locations)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist0 || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc0 || real time clock
|-
| '''0x48''' || da_timestamp0 || write timestamp mode
|-
| '''0x74''' || da_xjtag0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync0 || control of external sync module 0x78 - 0x7b
|-
|}

''333 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or aftre trigger)
|-
| '''0x06''' || da_interrupts0 || interrupt mask
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x10''' || da_debug || write 0x10 any - load debug shift, read (through cs4) -shift
|-
| '''0x20..0x27''' || da_mcontr0 || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table0 || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
|}

Addresses 0x01,2,3,4,5,6,8 and 0x30 can be kept in the 353 system interface. The interrupt mask address 0x06 in the 333 sys interface is no longer used (353 uses interrupt vectors). The Theora compressor and the new memory controller addresses have to be mapped again in the new design (addresses 0x0c..0x0d and 0x20 to 0x2f in the 353 sys interface).

=== Interrupts ===
Adapt the Theora compressor interrupts to the 353 interrupt vector .

The 353 interrupt vector can handle up to 16 different irq. However, only irq 0 to 7 are used :
'''x353.v'''

assign irq_in= {8'b0, // extra
compressor_done_compress, // 7 - will go high after all data is sent out (reset by compressor)
compressor_done_input, // 6 - will go high after EOT and persist until DCT is enabled (reset by compressor)
dcc_rdy, // 5 - obsolete in 333 - channel3 has 128 more dc coefficients (or some if the compression is finished)
compressor_eot, // 4 - compressor read in the last MCU (predictable time to end of transfer)
sr_sensortrig[2], // 3 - (sync to pclk) - level, reset by writing to sensor triggering command register
xfer_over_irq, // 2 - (sync to pclk) - frame acquisition over
trig_irq, // 1 - (sync to pclk) - external trigger
vacts}; // 0 - (sync to pclk) - frame sync

353 MJPEG compressor triggers irqs 4, 6 and 7. 333 Theora compressor is the source of two irqs :
'''compressor_all.v'''

done, // single-cycle pulse when the compressed frame is sent out (IRQ source).
reset_compress, // reset compressor done interrupt (writing any compressor command)

Adaptation should consist of assigning Theora compressor irq sources to vectors 6 and 7 for example if the MJPEG compressor is to be replaced.

=== DMA FIFOs ===
353 design uses 2 DMA FIFOs between the compressor and the system interface instead of one for the 333 Theora compressor. The two DMA FIFOs have also slight differences between the two design. Maybe a single 333 FIFO should be kept for the final design (?)

=== FPGA -> CPU data out MUX ===
The purpose of this MUX is to route data out from the different FPGA blocks to the system interface and then to the data bus to the CPU. The selection is made with the internal address bus ''ia''.
_
--| \
--| |
--| |
--| |--- iod[31:0] -> to system interface
--| |
--| |
|_/
from system interface -> ia[7:0]__|

'' 333 MUX ''
{|border="1" cellpadding="2"
! Adress range !! ia(5) !! ia(4) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''1''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''1''' || '''0''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''1''' || '''1''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0.. (even)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''0''' || dma_d0[31:0] || DMA 0 data
|-
| '''0x0.. (odd)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''1''' || dma_d1[31:0] || DMA 1 data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''X''' || '''X''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''X''' || '''X''' || dsdo[31:0] || Data out from descriptor memory
|-
| '''0x3..''' || '''0''' || '''1''' || '''1''' || '''X''' || '''X''' || bdo[31:0] || 32-bit data from SDRAM channel3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''X''' || '''0''' || '''X''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''X''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''X''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''X''' || '''X''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''X''' || '''X''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

'' 333 MUX ''
{|border="1" cellpadding="2"
! Address || ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || {24'b0,irqr[7:0]} || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(2) !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''0''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''0''' || '''1''' || '''1''' || MODELREV || Model revision
|-
| '''0x14''' || '''1''' || '''X''' || '''0''' || {8'h0,imgptr[23:0]} || Image pointer in 32-byte chunks
|-
| '''0x15''' || '''1''' || '''X''' || '''1''' || hifreq[31:0] || Accumulated high-freq components
|-
|}

'' 333 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock0
|-
| '''2''' || sr_sda1 || I2C
|-
| '''3''' || sr_scl1 || I2C clock1
|-
| '''4..12''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''17''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''18''' || 1'b0 || 0x0
|-
| '''19''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''20''' || itrig || TRIG input
|-
| '''21..22''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)
, 01 - clock is too late
, 10 - clock is too early
, 11 - OK (some measurements show too late, some - too early)
|-
| '''23''' || dcm_done ||
|-
| '''24''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''25''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''26''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''27''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''28''' || tok_frame_num_wr || Odd/even frame of tokens written
|-
| '''29''' || 1'b0 || 0x0
|-
| '''30''' || debug_out || Debug shift register output
|-
| '''31''' || 'b0 || 0x0
|-
|}

'' 353 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2''' || sr_ch0rdy || Ready to write next page (channel 0) SENSOR->SDRAM
|-
| '''3''' || sr_ch1rdy || Ready to read next page (channel 1) SDRAM->FPN(SENSOR)
|-
| '''4''' || sr_ch2rdy || Ready to read next page (channel 2) SDRAM->DMA
|-
| '''5''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''6''' || sr_wrempty || CPU write buffer empty (valid only in write mode). May reprogram channel3.
|-
| '''7..10''' || sr_nextFrame[3:0] || (level) generated before actual block is filled - needed to be combined with the pulse from buffer control
|-
| '''11..13''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''14''' || dcc_rdy || 128 of DC components from JPEG encoder are available (same as interrupt)
|-
| '''15''' || compressor_done_input || will go high after EOT and persist until DCT is enabled
|-
| '''16''' || compressor_done_compress || will go high after all data is sent out
|-
| '''17''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''19..18''' || dcm_err[1:0] || SDRAM DCM phase error
|-
| '''20''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''21''' || dcm_locked || SDRAM DCM overflow
|-
| '''22''' || dcm_status[0] || SDRAM DCM overflow
|-
| '''24..23''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''25''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''26''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''27''' || sens_dcm_status[0] || Sensor DCM overflow
|-
| '''28''' || clockios_locked || dcm locked
|-
| '''29..30''' || clockios_status[1:0] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''31''' || 1'b0 || 0x0
|-
|}

=== Control register ===
The dcr[31:0] bus is used to control the different blocks according to the control register values. The control register can be directly written by the CPU at the address 0x00.

''333 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0..2''' || Not used ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || iobuf || EXPS (output pin)
|-
| '''12''' || iobuf || EXPS (output pin)
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || i2cpads || scl1 out
|-
| '''20''' || i2cpads || scl1 enable
|-
| '''21''' || i2cpads || sda1 out
|-
| '''22''' || i2cpads || sda1 enable
|-
| '''23''' || Not used ||
|-
| '''24..27''' || clock_pclk || pclk source
|-
| '''28..30''' || Not used ||
|-
| '''31''' || clock_pclk || clk enable
|-
|}

''353 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0''' || Not used ||
|-
| '''1..2''' || compressor, sensorpix, histogram ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || sensorpads || sensor trigger
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || sensorpads || dclkmode
|-
| '''20''' || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || Not used ||
|-
| '''24..25''' || BUFGMUX || pclk source
|-
| '''28..30''' || compressor ||
|-
| '''31''' || clock_pclk ||
|-
|}

=== Others ===
* Looks like Theora compressor requires 90° phase clock that was abandoned in the 353 design.
Using different phases reduces AC component of the current through the power/ground lines of the FPGA by spreading register transitions. Theora has larger core so it may help spreading phases.--[[User:Andrey.filippov|Andrey.filippov]] 13:45, 25 February 2008 (CST)
* ...?

== Software updates ==

* Adapt FPGA definitions ([http://elphel.cvs.sourceforge.net/elphel/elphel353/elphel353/os/linux-2.6-tag--devboard-R2_01-1/arch/cris/arch-v32/drivers/elphel/x353.h?revision=1.8&view=markup&sortdir=down x353.h]) and most likely some other FPGA drivers.
* ...?

These lists of update are obviously incomplete. They need to be more detailed in order to make an exhaustive list of the changes that have to be done.

== 353 Theora new design ==
=== Compressor ===

Writing tables in compressor (and mcontr8ch) is the same than the 333 design :
* ia = 0x2d and idi = table start address
then
* ia = 0x2c and idi = table data

The write address is then autoincremented.

Example : Writing zerobin and quantization tables in 353 Theora design

[[Image:Writetabs.jpg]]

=== Sensorpix ===

Most of the 353 design was used for the new design. Writing procedure for gamma tables in sensorpix block is the same than in 353 (ie with ta bus and twr_gamma signal).

=== Memory controller ===

{|border="1" cellpadding="2"
! Channel !! Description
|-
| '''0''' || 8/16 bit data from sensor to SDRAM
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor
|-
| '''3''' || PIO read/write of SDRAM data
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63]
|-
| '''7''' || Reading 12-bit pre-tokens from SDRAM in indexed coded order
|-
|}

=== System interface ===

{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm || tune SDRAM clock phase
|-
| '''0x0a''' || da_framesync_dly || write frame sync interrupt delay (in scan lines)
|-
| '''0x0e''' || da_table_a0 || write gamma table address
|-
| '''0x0f''' || twr0 || write gamma table data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts || interrupt control
|-
| '''0x20..0x27''' || da_mcontr || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc || real time clock
|-
| '''0x48''' || da_timestamp || write timestamp mode
|-
| '''0x74''' || da_xjta0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync || control of external sync module 0x78 - 0x7b
|-
|}

=== Interrupts ===

{|border="1" cellpadding="2"
! irq_in !! Signal !! Comments
|-
| '''15..8''' || GND || Extra
|-
| '''7''' || compressor_done_compress || single-cycle pulse when the compressed frame is sent out
|-
| '''6''' || compressor_reset_compress || reset compressor done interrupt (writing any compressor command)
|-
| '''5''' || GND || dcc_rdy was tied to GND in the 333 design
|-
| '''4''' || GND || eot irq was tied to GND in the 333 design
|-
| '''3''' || sr_sensortrig[2] || (sync to pclk) - level, reset by writing to sensor triggering command register
|-
| '''2''' || xfer_over_irq || (sync to pclk) - frame acquisition over
|-
| '''1''' || trig_irq || (sync to pclk) - external trigger
|-
| '''0''' || vacts || (sync to pclk) - frame sync
|-
|}

=== DMA FIFOs ===
A single DMA FIFO from the 333 design will be instanciated.

=== FPGA -> CPU data out MUX ===

{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || '''0''' || '''x''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''x''' || '''x''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''x''' || '''0''' || '''x''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''x''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''x''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''x''' || '''x''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''x''' || '''x''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

{|border="1" cellpadding="2"
! Address !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' Status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C data
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2..10''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''11''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''12''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''17..18''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)

, 01 - clock is too late , 10 - clock is too early , 11 - OK (some measurements show too late, some - too early)
|-
| '''19''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''20''' || dcm_locked || SDRAM DCM overflow
|-
| '''21..22''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''23''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''24''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''25''' || clockios_locked || dcm locked
|-
| '''26''' || clockios_status[1] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''27''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''28''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''29''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''30''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''31''' || took_frame_num_wr || Odd/even frame of tokens written
|-
|}

=== Control register ===
{|border="1" cellpadding="2"
! bit # !! Signal || Destination block !! Comments
|-
| '''0''' || || Not used ||
|-
| '''1..2''' || cb_bayer_phase || compressor, sensorpix, histogram ||
|-
| '''3''' || || sensorpads || Inverts idclk phase (Not used)
|-
| '''4''' || cb_fillfactory || sensorpads || fillfactory sensor mode
|-
| '''5''' || cb_dlyhact || sensorpads || delay hact pulse by 1
|-
| '''6''' || cb_zoran || sensorpads || ''cb_zoran''
|-
| '''7''' || cb_skipline || sensorpads || skip first scan line from the sensor
|-
| '''8''' || cb_xt_pol || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || iarst || sensorpads || ''iarst''
|-
| '''10''' || iaro || sensorpads || ''iaro''
|-
| '''11''' || cb_encnvclk || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || cb_sensor_trigger || sensorpads || sensor trigger
|-
| '''13''' || imrst || sensorpads || ''imrst''
|-
| '''14''' || cb_scl0_o || iobuf || XRST (output pin)
|-
| '''15''' || cb_scl0_o || i2cpads || scl0 out
|-
| '''16''' || cb_scl0_en || i2cpads || scl0 enable
|-
| '''17''' || cb_sda0_o || i2cpads || sda0 out
|-
| '''18''' || cb_sda0_en || i2cpads || sda0 enable
|-
| '''19''' || cb_dclkmode || sensorpads || dclkmode
|-
| '''20''' || cb_pxd14 || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || cb_latehact || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || || Not used ||
|-
| '''24..25''' || cb_pclksrc || BUFGMUX || pclk source
|-
| '''28..30''' || || Not used ||
|-
| '''31''' || || Not used ||
|-
|}

=== Others ===

== See also ==

*[http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ 353 Theora CVS]
*[[Theora]]
*[[FPGA_Development_in_Elphel_cameras|FPGA Development in Elphel cameras]]
*[[Design Ideas|FPGA Theora Encoder for Videoconferencing]]
*[[10353]]

Porting Theora to 353 cameras

2008-04-09T15:17:08Z

JeremViewsurf: /* Compressor */

Elphel model 333 cameras were able to encode and stream Ogg Theora with 6.3.9 firmware. However, this model is no longer produced by Elphel. The goal of this project is to use the full potential of 353 cameras (larger FPGA, faster CPU) in order to port the Ogg Theora feature on the new hardware. First, the camera should be able to upload small Theora clips via FTP.

Different solutions are possible as previously mentioned in the [[Theora]] page :
* Instantiate both the Theora compressor and the MJPEG compressor in the FPGA since the new Spartan 3E seems to be large enough to handle the two features.
* Replace the existing MJPEG compressor with the Theora compressor and implement software Theora to JPEG conversion if JPEG is needed.
* Replace the existing MJPEG compressor in the 353 camera with the Theora compressor and keep two configuration files on the camera filesystem (one for Theora the other for MJPEG). FPGA code could be changed at run-time according to the needs.

Dealing with the last solution seems to be a good start for this project as the other features mentioned can be added later. In all cases, both FPGA code and software code will need to be adapted.

The source code of this project is available at [http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/]
== Hardware updates ==

=== Compressor ===
[[Image:Schematic.png|frame|[[Media:Schematic.png|333 Theora design with the 2 stage compressor and the 8-channel memory controller]]]]
Replace the MJPEG compressor in the 353 with the 333 Theora compressor ([http://elphel.cvs.sourceforge.net/elphel/camera333/fpga/x333 333 Theora FPGA code]). Maybe some adaptations need to be done within the Theora compressor itself. However, assuming that the compressor worked in 333 cameras a simple instantiation should suffice.

=== Memory controller ===
Replace the 4-channel memory controller with an 8 channel memory interface as in the 333 model in order to handle Theora specific data.

{|border="1" cellpadding="2"
! Channel !! 333 Theora !! 353
|-
| '''0''' || 8/16 bit data from sensor to SDRAM || Data from the sensor (it can be combined with FPN correction data) to the SDRAM in either 8-bit mode or 16-bit
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module || Reads FPN data from SDRAM (8bit - subtract, 8 bit - scale) and feeds it to FPGA for FPN correction of the data on the way from sensor to SDRAM (through channel 0)
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor || Provides data to JPEG encoder in 16x16x8bit MCUs. It can also provide data directly to CPU through DMA bypassing any compression
|-
| '''3''' || PIO read/write of SDRAM data || Provides bidirectional access from CPU through 8x32 bit window.
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM ||
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM ||
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63] ||
|-
| '''7''' || reading 12-bit pre-tokens from SDRAM in indexed coded order ||
|-
|}

=== Sensor interface ===
''sensorpix'' block must be adapted in order to provide a coherent interface between the memory controller and the sensor (channels 0 and 1)

=== System Interface ===
Adapt the system interface to assure communication between FPGA and its environment.

A feature of the system interface is to establish communication between the system CPU and the different blocks within the FPGA (compressor, memory controller etc). This is done by selecting a block with the address bus ''a[12:0]'' connected to the internal address bus ''ial[7:0]'':

'''x353.v'''
always @ (posedge cwr) begin
a0[7:0]<=ial[7:0]; // may want to change to just ia if ia will be late enough;
wnr0 <= ~irnw;
da_ctl0 <= (ial[7:0]==8'h00); // 0x00 WE to control 32-bit register (1 loc)
da_dmamode0 <= (ial[7:0]==8'h01); // 0x01 select writing to dma_cntr/dma_raw (1 loc)
da_sensormode0 <= (ial[7:0]==8'h02); // 0x02 select writing to sensorpix (1 loc)
...
da_compressor0 <= (ial[7:1]==7'h06); // 0x0c..0x0d - will be farther decoded in the compressor module
...

Since memory controller and compressor are to be replaced these addresses have to be adapted.

''353 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x09''' || da_saturation0 || write color saturation values
|-
| '''0x0a''' || da_framesync_dly0 || write frame sync interrupt delay (in scan lines)
|-
| '''0x0c..0x0d''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x0e''' || da_table_a0 || write tables address
|-
| '''0x0f''' || twr0 || write tables data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts0 || interrupt control
|-
| '''0x20..0x2f''' || da_dswe0 || select reading/writing to mcontr (16 locations)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist0 || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc0 || real time clock
|-
| '''0x48''' || da_timestamp0 || write timestamp mode
|-
| '''0x74''' || da_xjtag0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync0 || control of external sync module 0x78 - 0x7b
|-
|}

''333 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or aftre trigger)
|-
| '''0x06''' || da_interrupts0 || interrupt mask
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x10''' || da_debug || write 0x10 any - load debug shift, read (through cs4) -shift
|-
| '''0x20..0x27''' || da_mcontr0 || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table0 || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
|}

Addresses 0x01,2,3,4,5,6,8 and 0x30 can be kept in the 353 system interface. The interrupt mask address 0x06 in the 333 sys interface is no longer used (353 uses interrupt vectors). The Theora compressor and the new memory controller addresses have to be mapped again in the new design (addresses 0x0c..0x0d and 0x20 to 0x2f in the 353 sys interface).

=== Interrupts ===
Adapt the Theora compressor interrupts to the 353 interrupt vector .

The 353 interrupt vector can handle up to 16 different irq. However, only irq 0 to 7 are used :
'''x353.v'''

assign irq_in= {8'b0, // extra
compressor_done_compress, // 7 - will go high after all data is sent out (reset by compressor)
compressor_done_input, // 6 - will go high after EOT and persist until DCT is enabled (reset by compressor)
dcc_rdy, // 5 - obsolete in 333 - channel3 has 128 more dc coefficients (or some if the compression is finished)
compressor_eot, // 4 - compressor read in the last MCU (predictable time to end of transfer)
sr_sensortrig[2], // 3 - (sync to pclk) - level, reset by writing to sensor triggering command register
xfer_over_irq, // 2 - (sync to pclk) - frame acquisition over
trig_irq, // 1 - (sync to pclk) - external trigger
vacts}; // 0 - (sync to pclk) - frame sync

353 MJPEG compressor triggers irqs 4, 6 and 7. 333 Theora compressor is the source of two irqs :
'''compressor_all.v'''

done, // single-cycle pulse when the compressed frame is sent out (IRQ source).
reset_compress, // reset compressor done interrupt (writing any compressor command)

Adaptation should consist of assigning Theora compressor irq sources to vectors 6 and 7 for example if the MJPEG compressor is to be replaced.

=== DMA FIFOs ===
353 design uses 2 DMA FIFOs between the compressor and the system interface instead of one for the 333 Theora compressor. The two DMA FIFOs have also slight differences between the two design. Maybe a single 333 FIFO should be kept for the final design (?)

=== FPGA -> CPU data out MUX ===
The purpose of this MUX is to route data out from the different FPGA blocks to the system interface and then to the data bus to the CPU. The selection is made with the internal address bus ''ia''.
_
--| \
--| |
--| |
--| |--- iod[31:0] -> to system interface
--| |
--| |
|_/
from system interface -> ia[7:0]__|

'' 333 MUX ''
{|border="1" cellpadding="2"
! Adress range !! ia(5) !! ia(4) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''1''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''1''' || '''0''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''1''' || '''1''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0.. (even)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''0''' || dma_d0[31:0] || DMA 0 data
|-
| '''0x0.. (odd)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''1''' || dma_d1[31:0] || DMA 1 data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''X''' || '''X''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''X''' || '''X''' || dsdo[31:0] || Data out from descriptor memory
|-
| '''0x3..''' || '''0''' || '''1''' || '''1''' || '''X''' || '''X''' || bdo[31:0] || 32-bit data from SDRAM channel3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''X''' || '''0''' || '''X''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''X''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''X''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''X''' || '''X''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''X''' || '''X''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

'' 333 MUX ''
{|border="1" cellpadding="2"
! Address || ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || {24'b0,irqr[7:0]} || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(2) !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''0''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''0''' || '''1''' || '''1''' || MODELREV || Model revision
|-
| '''0x14''' || '''1''' || '''X''' || '''0''' || {8'h0,imgptr[23:0]} || Image pointer in 32-byte chunks
|-
| '''0x15''' || '''1''' || '''X''' || '''1''' || hifreq[31:0] || Accumulated high-freq components
|-
|}

'' 333 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock0
|-
| '''2''' || sr_sda1 || I2C
|-
| '''3''' || sr_scl1 || I2C clock1
|-
| '''4..12''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''17''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''18''' || 1'b0 || 0x0
|-
| '''19''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''20''' || itrig || TRIG input
|-
| '''21..22''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)
, 01 - clock is too late
, 10 - clock is too early
, 11 - OK (some measurements show too late, some - too early)
|-
| '''23''' || dcm_done ||
|-
| '''24''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''25''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''26''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''27''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''28''' || tok_frame_num_wr || Odd/even frame of tokens written
|-
| '''29''' || 1'b0 || 0x0
|-
| '''30''' || debug_out || Debug shift register output
|-
| '''31''' || 'b0 || 0x0
|-
|}

'' 353 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2''' || sr_ch0rdy || Ready to write next page (channel 0) SENSOR->SDRAM
|-
| '''3''' || sr_ch1rdy || Ready to read next page (channel 1) SDRAM->FPN(SENSOR)
|-
| '''4''' || sr_ch2rdy || Ready to read next page (channel 2) SDRAM->DMA
|-
| '''5''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''6''' || sr_wrempty || CPU write buffer empty (valid only in write mode). May reprogram channel3.
|-
| '''7..10''' || sr_nextFrame[3:0] || (level) generated before actual block is filled - needed to be combined with the pulse from buffer control
|-
| '''11..13''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''14''' || dcc_rdy || 128 of DC components from JPEG encoder are available (same as interrupt)
|-
| '''15''' || compressor_done_input || will go high after EOT and persist until DCT is enabled
|-
| '''16''' || compressor_done_compress || will go high after all data is sent out
|-
| '''17''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''19..18''' || dcm_err[1:0] || SDRAM DCM phase error
|-
| '''20''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''21''' || dcm_locked || SDRAM DCM overflow
|-
| '''22''' || dcm_status[0] || SDRAM DCM overflow
|-
| '''24..23''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''25''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''26''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''27''' || sens_dcm_status[0] || Sensor DCM overflow
|-
| '''28''' || clockios_locked || dcm locked
|-
| '''29..30''' || clockios_status[1:0] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''31''' || 1'b0 || 0x0
|-
|}

=== Control register ===
The dcr[31:0] bus is used to control the different blocks according to the control register values. The control register can be directly written by the CPU at the address 0x00.

''333 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0..2''' || Not used ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || iobuf || EXPS (output pin)
|-
| '''12''' || iobuf || EXPS (output pin)
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || i2cpads || scl1 out
|-
| '''20''' || i2cpads || scl1 enable
|-
| '''21''' || i2cpads || sda1 out
|-
| '''22''' || i2cpads || sda1 enable
|-
| '''23''' || Not used ||
|-
| '''24..27''' || clock_pclk || pclk source
|-
| '''28..30''' || Not used ||
|-
| '''31''' || clock_pclk || clk enable
|-
|}

''353 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0''' || Not used ||
|-
| '''1..2''' || compressor, sensorpix, histogram ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || sensorpads || sensor trigger
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || sensorpads || dclkmode
|-
| '''20''' || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || Not used ||
|-
| '''24..25''' || BUFGMUX || pclk source
|-
| '''28..30''' || compressor ||
|-
| '''31''' || clock_pclk ||
|-
|}

=== Others ===
* Looks like Theora compressor requires 90° phase clock that was abandoned in the 353 design.
Using different phases reduces AC component of the current through the power/ground lines of the FPGA by spreading register transitions. Theora has larger core so it may help spreading phases.--[[User:Andrey.filippov|Andrey.filippov]] 13:45, 25 February 2008 (CST)
* ...?

== Software updates ==

* Adapt FPGA definitions ([http://elphel.cvs.sourceforge.net/elphel/elphel353/elphel353/os/linux-2.6-tag--devboard-R2_01-1/arch/cris/arch-v32/drivers/elphel/x353.h?revision=1.8&view=markup&sortdir=down x353.h]) and most likely some other FPGA drivers.
* ...?

These lists of update are obviously incomplete. They need to be more detailed in order to make an exhaustive list of the changes that have to be done.

== 353 Theora new design ==
=== Compressor ===

Writing tables in compressor (and mcontr8ch) is the same than the 333 design :
* ia = 0x2d and idi = table address
then
* ia = 0x2c and idi = table data

Example : Writing zerobin and quantization tables in 353 Theora design

[[Image:Writetabs.jpg]]

=== Sensorpix ===

Most of the 353 design was used for the new design. Writing procedure for gamma tables in sensorpix block is the same than in 353 (ie with ta bus and twr_gamma signal).

=== Memory controller ===

{|border="1" cellpadding="2"
! Channel !! Description
|-
| '''0''' || 8/16 bit data from sensor to SDRAM
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor
|-
| '''3''' || PIO read/write of SDRAM data
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63]
|-
| '''7''' || Reading 12-bit pre-tokens from SDRAM in indexed coded order
|-
|}

=== System interface ===

{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm || tune SDRAM clock phase
|-
| '''0x0a''' || da_framesync_dly || write frame sync interrupt delay (in scan lines)
|-
| '''0x0e''' || da_table_a0 || write gamma table address
|-
| '''0x0f''' || twr0 || write gamma table data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts || interrupt control
|-
| '''0x20..0x27''' || da_mcontr || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc || real time clock
|-
| '''0x48''' || da_timestamp || write timestamp mode
|-
| '''0x74''' || da_xjta0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync || control of external sync module 0x78 - 0x7b
|-
|}

=== Interrupts ===

{|border="1" cellpadding="2"
! irq_in !! Signal !! Comments
|-
| '''15..8''' || GND || Extra
|-
| '''7''' || compressor_done_compress || single-cycle pulse when the compressed frame is sent out
|-
| '''6''' || compressor_reset_compress || reset compressor done interrupt (writing any compressor command)
|-
| '''5''' || GND || dcc_rdy was tied to GND in the 333 design
|-
| '''4''' || GND || eot irq was tied to GND in the 333 design
|-
| '''3''' || sr_sensortrig[2] || (sync to pclk) - level, reset by writing to sensor triggering command register
|-
| '''2''' || xfer_over_irq || (sync to pclk) - frame acquisition over
|-
| '''1''' || trig_irq || (sync to pclk) - external trigger
|-
| '''0''' || vacts || (sync to pclk) - frame sync
|-
|}

=== DMA FIFOs ===
A single DMA FIFO from the 333 design will be instanciated.

=== FPGA -> CPU data out MUX ===

{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || '''0''' || '''x''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''x''' || '''x''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''x''' || '''0''' || '''x''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''x''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''x''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''x''' || '''x''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''x''' || '''x''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

{|border="1" cellpadding="2"
! Address !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' Status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C data
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2..10''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''11''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''12''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''17..18''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)

, 01 - clock is too late , 10 - clock is too early , 11 - OK (some measurements show too late, some - too early)
|-
| '''19''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''20''' || dcm_locked || SDRAM DCM overflow
|-
| '''21..22''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''23''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''24''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''25''' || clockios_locked || dcm locked
|-
| '''26''' || clockios_status[1] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''27''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''28''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''29''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''30''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''31''' || took_frame_num_wr || Odd/even frame of tokens written
|-
|}

=== Control register ===
{|border="1" cellpadding="2"
! bit # !! Signal || Destination block !! Comments
|-
| '''0''' || || Not used ||
|-
| '''1..2''' || cb_bayer_phase || compressor, sensorpix, histogram ||
|-
| '''3''' || || sensorpads || Inverts idclk phase (Not used)
|-
| '''4''' || cb_fillfactory || sensorpads || fillfactory sensor mode
|-
| '''5''' || cb_dlyhact || sensorpads || delay hact pulse by 1
|-
| '''6''' || cb_zoran || sensorpads || ''cb_zoran''
|-
| '''7''' || cb_skipline || sensorpads || skip first scan line from the sensor
|-
| '''8''' || cb_xt_pol || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || iarst || sensorpads || ''iarst''
|-
| '''10''' || iaro || sensorpads || ''iaro''
|-
| '''11''' || cb_encnvclk || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || cb_sensor_trigger || sensorpads || sensor trigger
|-
| '''13''' || imrst || sensorpads || ''imrst''
|-
| '''14''' || cb_scl0_o || iobuf || XRST (output pin)
|-
| '''15''' || cb_scl0_o || i2cpads || scl0 out
|-
| '''16''' || cb_scl0_en || i2cpads || scl0 enable
|-
| '''17''' || cb_sda0_o || i2cpads || sda0 out
|-
| '''18''' || cb_sda0_en || i2cpads || sda0 enable
|-
| '''19''' || cb_dclkmode || sensorpads || dclkmode
|-
| '''20''' || cb_pxd14 || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || cb_latehact || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || || Not used ||
|-
| '''24..25''' || cb_pclksrc || BUFGMUX || pclk source
|-
| '''28..30''' || || Not used ||
|-
| '''31''' || || Not used ||
|-
|}

=== Others ===

== See also ==

*[http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ 353 Theora CVS]
*[[Theora]]
*[[FPGA_Development_in_Elphel_cameras|FPGA Development in Elphel cameras]]
*[[Design Ideas|FPGA Theora Encoder for Videoconferencing]]
*[[10353]]

File:Writetabs.jpg

2008-04-09T15:15:54Z

JeremViewsurf: Writing zerobin and quantization tables in 353 theora design

Writing zerobin and quantization tables in 353 theora design

Porting Theora to 353 cameras

2008-04-09T15:09:52Z

JeremViewsurf: /* Compressor */

Elphel model 333 cameras were able to encode and stream Ogg Theora with 6.3.9 firmware. However, this model is no longer produced by Elphel. The goal of this project is to use the full potential of 353 cameras (larger FPGA, faster CPU) in order to port the Ogg Theora feature on the new hardware. First, the camera should be able to upload small Theora clips via FTP.

Different solutions are possible as previously mentioned in the [[Theora]] page :
* Instantiate both the Theora compressor and the MJPEG compressor in the FPGA since the new Spartan 3E seems to be large enough to handle the two features.
* Replace the existing MJPEG compressor with the Theora compressor and implement software Theora to JPEG conversion if JPEG is needed.
* Replace the existing MJPEG compressor in the 353 camera with the Theora compressor and keep two configuration files on the camera filesystem (one for Theora the other for MJPEG). FPGA code could be changed at run-time according to the needs.

Dealing with the last solution seems to be a good start for this project as the other features mentioned can be added later. In all cases, both FPGA code and software code will need to be adapted.

The source code of this project is available at [http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/]
== Hardware updates ==

=== Compressor ===
[[Image:Schematic.png|frame|[[Media:Schematic.png|333 Theora design with the 2 stage compressor and the 8-channel memory controller]]]]
Replace the MJPEG compressor in the 353 with the 333 Theora compressor ([http://elphel.cvs.sourceforge.net/elphel/camera333/fpga/x333 333 Theora FPGA code]). Maybe some adaptations need to be done within the Theora compressor itself. However, assuming that the compressor worked in 333 cameras a simple instantiation should suffice.

=== Memory controller ===
Replace the 4-channel memory controller with an 8 channel memory interface as in the 333 model in order to handle Theora specific data.

{|border="1" cellpadding="2"
! Channel !! 333 Theora !! 353
|-
| '''0''' || 8/16 bit data from sensor to SDRAM || Data from the sensor (it can be combined with FPN correction data) to the SDRAM in either 8-bit mode or 16-bit
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module || Reads FPN data from SDRAM (8bit - subtract, 8 bit - scale) and feeds it to FPGA for FPN correction of the data on the way from sensor to SDRAM (through channel 0)
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor || Provides data to JPEG encoder in 16x16x8bit MCUs. It can also provide data directly to CPU through DMA bypassing any compression
|-
| '''3''' || PIO read/write of SDRAM data || Provides bidirectional access from CPU through 8x32 bit window.
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM ||
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM ||
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63] ||
|-
| '''7''' || reading 12-bit pre-tokens from SDRAM in indexed coded order ||
|-
|}

=== Sensor interface ===
''sensorpix'' block must be adapted in order to provide a coherent interface between the memory controller and the sensor (channels 0 and 1)

=== System Interface ===
Adapt the system interface to assure communication between FPGA and its environment.

A feature of the system interface is to establish communication between the system CPU and the different blocks within the FPGA (compressor, memory controller etc). This is done by selecting a block with the address bus ''a[12:0]'' connected to the internal address bus ''ial[7:0]'':

'''x353.v'''
always @ (posedge cwr) begin
a0[7:0]<=ial[7:0]; // may want to change to just ia if ia will be late enough;
wnr0 <= ~irnw;
da_ctl0 <= (ial[7:0]==8'h00); // 0x00 WE to control 32-bit register (1 loc)
da_dmamode0 <= (ial[7:0]==8'h01); // 0x01 select writing to dma_cntr/dma_raw (1 loc)
da_sensormode0 <= (ial[7:0]==8'h02); // 0x02 select writing to sensorpix (1 loc)
...
da_compressor0 <= (ial[7:1]==7'h06); // 0x0c..0x0d - will be farther decoded in the compressor module
...

Since memory controller and compressor are to be replaced these addresses have to be adapted.

''353 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x09''' || da_saturation0 || write color saturation values
|-
| '''0x0a''' || da_framesync_dly0 || write frame sync interrupt delay (in scan lines)
|-
| '''0x0c..0x0d''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x0e''' || da_table_a0 || write tables address
|-
| '''0x0f''' || twr0 || write tables data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts0 || interrupt control
|-
| '''0x20..0x2f''' || da_dswe0 || select reading/writing to mcontr (16 locations)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist0 || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc0 || real time clock
|-
| '''0x48''' || da_timestamp0 || write timestamp mode
|-
| '''0x74''' || da_xjtag0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync0 || control of external sync module 0x78 - 0x7b
|-
|}

''333 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or aftre trigger)
|-
| '''0x06''' || da_interrupts0 || interrupt mask
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x10''' || da_debug || write 0x10 any - load debug shift, read (through cs4) -shift
|-
| '''0x20..0x27''' || da_mcontr0 || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table0 || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
|}

Addresses 0x01,2,3,4,5,6,8 and 0x30 can be kept in the 353 system interface. The interrupt mask address 0x06 in the 333 sys interface is no longer used (353 uses interrupt vectors). The Theora compressor and the new memory controller addresses have to be mapped again in the new design (addresses 0x0c..0x0d and 0x20 to 0x2f in the 353 sys interface).

=== Interrupts ===
Adapt the Theora compressor interrupts to the 353 interrupt vector .

The 353 interrupt vector can handle up to 16 different irq. However, only irq 0 to 7 are used :
'''x353.v'''

assign irq_in= {8'b0, // extra
compressor_done_compress, // 7 - will go high after all data is sent out (reset by compressor)
compressor_done_input, // 6 - will go high after EOT and persist until DCT is enabled (reset by compressor)
dcc_rdy, // 5 - obsolete in 333 - channel3 has 128 more dc coefficients (or some if the compression is finished)
compressor_eot, // 4 - compressor read in the last MCU (predictable time to end of transfer)
sr_sensortrig[2], // 3 - (sync to pclk) - level, reset by writing to sensor triggering command register
xfer_over_irq, // 2 - (sync to pclk) - frame acquisition over
trig_irq, // 1 - (sync to pclk) - external trigger
vacts}; // 0 - (sync to pclk) - frame sync

353 MJPEG compressor triggers irqs 4, 6 and 7. 333 Theora compressor is the source of two irqs :
'''compressor_all.v'''

done, // single-cycle pulse when the compressed frame is sent out (IRQ source).
reset_compress, // reset compressor done interrupt (writing any compressor command)

Adaptation should consist of assigning Theora compressor irq sources to vectors 6 and 7 for example if the MJPEG compressor is to be replaced.

=== DMA FIFOs ===
353 design uses 2 DMA FIFOs between the compressor and the system interface instead of one for the 333 Theora compressor. The two DMA FIFOs have also slight differences between the two design. Maybe a single 333 FIFO should be kept for the final design (?)

=== FPGA -> CPU data out MUX ===
The purpose of this MUX is to route data out from the different FPGA blocks to the system interface and then to the data bus to the CPU. The selection is made with the internal address bus ''ia''.
_
--| \
--| |
--| |
--| |--- iod[31:0] -> to system interface
--| |
--| |
|_/
from system interface -> ia[7:0]__|

'' 333 MUX ''
{|border="1" cellpadding="2"
! Adress range !! ia(5) !! ia(4) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''1''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''1''' || '''0''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''1''' || '''1''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0.. (even)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''0''' || dma_d0[31:0] || DMA 0 data
|-
| '''0x0.. (odd)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''1''' || dma_d1[31:0] || DMA 1 data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''X''' || '''X''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''X''' || '''X''' || dsdo[31:0] || Data out from descriptor memory
|-
| '''0x3..''' || '''0''' || '''1''' || '''1''' || '''X''' || '''X''' || bdo[31:0] || 32-bit data from SDRAM channel3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''X''' || '''0''' || '''X''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''X''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''X''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''X''' || '''X''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''X''' || '''X''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

'' 333 MUX ''
{|border="1" cellpadding="2"
! Address || ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || {24'b0,irqr[7:0]} || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(2) !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''0''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''0''' || '''1''' || '''1''' || MODELREV || Model revision
|-
| '''0x14''' || '''1''' || '''X''' || '''0''' || {8'h0,imgptr[23:0]} || Image pointer in 32-byte chunks
|-
| '''0x15''' || '''1''' || '''X''' || '''1''' || hifreq[31:0] || Accumulated high-freq components
|-
|}

'' 333 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock0
|-
| '''2''' || sr_sda1 || I2C
|-
| '''3''' || sr_scl1 || I2C clock1
|-
| '''4..12''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''17''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''18''' || 1'b0 || 0x0
|-
| '''19''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''20''' || itrig || TRIG input
|-
| '''21..22''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)
, 01 - clock is too late
, 10 - clock is too early
, 11 - OK (some measurements show too late, some - too early)
|-
| '''23''' || dcm_done ||
|-
| '''24''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''25''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''26''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''27''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''28''' || tok_frame_num_wr || Odd/even frame of tokens written
|-
| '''29''' || 1'b0 || 0x0
|-
| '''30''' || debug_out || Debug shift register output
|-
| '''31''' || 'b0 || 0x0
|-
|}

'' 353 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2''' || sr_ch0rdy || Ready to write next page (channel 0) SENSOR->SDRAM
|-
| '''3''' || sr_ch1rdy || Ready to read next page (channel 1) SDRAM->FPN(SENSOR)
|-
| '''4''' || sr_ch2rdy || Ready to read next page (channel 2) SDRAM->DMA
|-
| '''5''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''6''' || sr_wrempty || CPU write buffer empty (valid only in write mode). May reprogram channel3.
|-
| '''7..10''' || sr_nextFrame[3:0] || (level) generated before actual block is filled - needed to be combined with the pulse from buffer control
|-
| '''11..13''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''14''' || dcc_rdy || 128 of DC components from JPEG encoder are available (same as interrupt)
|-
| '''15''' || compressor_done_input || will go high after EOT and persist until DCT is enabled
|-
| '''16''' || compressor_done_compress || will go high after all data is sent out
|-
| '''17''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''19..18''' || dcm_err[1:0] || SDRAM DCM phase error
|-
| '''20''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''21''' || dcm_locked || SDRAM DCM overflow
|-
| '''22''' || dcm_status[0] || SDRAM DCM overflow
|-
| '''24..23''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''25''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''26''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''27''' || sens_dcm_status[0] || Sensor DCM overflow
|-
| '''28''' || clockios_locked || dcm locked
|-
| '''29..30''' || clockios_status[1:0] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''31''' || 1'b0 || 0x0
|-
|}

=== Control register ===
The dcr[31:0] bus is used to control the different blocks according to the control register values. The control register can be directly written by the CPU at the address 0x00.

''333 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0..2''' || Not used ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || iobuf || EXPS (output pin)
|-
| '''12''' || iobuf || EXPS (output pin)
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || i2cpads || scl1 out
|-
| '''20''' || i2cpads || scl1 enable
|-
| '''21''' || i2cpads || sda1 out
|-
| '''22''' || i2cpads || sda1 enable
|-
| '''23''' || Not used ||
|-
| '''24..27''' || clock_pclk || pclk source
|-
| '''28..30''' || Not used ||
|-
| '''31''' || clock_pclk || clk enable
|-
|}

''353 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0''' || Not used ||
|-
| '''1..2''' || compressor, sensorpix, histogram ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || sensorpads || sensor trigger
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || sensorpads || dclkmode
|-
| '''20''' || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || Not used ||
|-
| '''24..25''' || BUFGMUX || pclk source
|-
| '''28..30''' || compressor ||
|-
| '''31''' || clock_pclk ||
|-
|}

=== Others ===
* Looks like Theora compressor requires 90° phase clock that was abandoned in the 353 design.
Using different phases reduces AC component of the current through the power/ground lines of the FPGA by spreading register transitions. Theora has larger core so it may help spreading phases.--[[User:Andrey.filippov|Andrey.filippov]] 13:45, 25 February 2008 (CST)
* ...?

== Software updates ==

* Adapt FPGA definitions ([http://elphel.cvs.sourceforge.net/elphel/elphel353/elphel353/os/linux-2.6-tag--devboard-R2_01-1/arch/cris/arch-v32/drivers/elphel/x353.h?revision=1.8&view=markup&sortdir=down x353.h]) and most likely some other FPGA drivers.
* ...?

These lists of update are obviously incomplete. They need to be more detailed in order to make an exhaustive list of the changes that have to be done.

== 353 Theora new design ==
=== Compressor ===

Writing tables in compressor (and mcontr8ch) is the same than the 333 design :
* ia = 0x2d and idi = table address
then
* ia = 0x2c and idi = table data

=== Sensorpix ===

Most of the 353 design was used for the new design. Writing procedure for gamma tables in sensorpix block is the same than in 353 (ie with ta bus and twr_gamma signal).

=== Memory controller ===

{|border="1" cellpadding="2"
! Channel !! Description
|-
| '''0''' || 8/16 bit data from sensor to SDRAM
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor
|-
| '''3''' || PIO read/write of SDRAM data
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63]
|-
| '''7''' || Reading 12-bit pre-tokens from SDRAM in indexed coded order
|-
|}

=== System interface ===

{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm || tune SDRAM clock phase
|-
| '''0x0a''' || da_framesync_dly || write frame sync interrupt delay (in scan lines)
|-
| '''0x0e''' || da_table_a0 || write gamma table address
|-
| '''0x0f''' || twr0 || write gamma table data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts || interrupt control
|-
| '''0x20..0x27''' || da_mcontr || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc || real time clock
|-
| '''0x48''' || da_timestamp || write timestamp mode
|-
| '''0x74''' || da_xjta0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync || control of external sync module 0x78 - 0x7b
|-
|}

=== Interrupts ===

{|border="1" cellpadding="2"
! irq_in !! Signal !! Comments
|-
| '''15..8''' || GND || Extra
|-
| '''7''' || compressor_done_compress || single-cycle pulse when the compressed frame is sent out
|-
| '''6''' || compressor_reset_compress || reset compressor done interrupt (writing any compressor command)
|-
| '''5''' || GND || dcc_rdy was tied to GND in the 333 design
|-
| '''4''' || GND || eot irq was tied to GND in the 333 design
|-
| '''3''' || sr_sensortrig[2] || (sync to pclk) - level, reset by writing to sensor triggering command register
|-
| '''2''' || xfer_over_irq || (sync to pclk) - frame acquisition over
|-
| '''1''' || trig_irq || (sync to pclk) - external trigger
|-
| '''0''' || vacts || (sync to pclk) - frame sync
|-
|}

=== DMA FIFOs ===
A single DMA FIFO from the 333 design will be instanciated.

=== FPGA -> CPU data out MUX ===

{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || '''0''' || '''x''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''x''' || '''x''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''x''' || '''0''' || '''x''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''x''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''x''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''x''' || '''x''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''x''' || '''x''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

{|border="1" cellpadding="2"
! Address !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' Status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C data
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2..10''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''11''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''12''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''17..18''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)

, 01 - clock is too late , 10 - clock is too early , 11 - OK (some measurements show too late, some - too early)
|-
| '''19''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''20''' || dcm_locked || SDRAM DCM overflow
|-
| '''21..22''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''23''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''24''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''25''' || clockios_locked || dcm locked
|-
| '''26''' || clockios_status[1] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''27''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''28''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''29''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''30''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''31''' || took_frame_num_wr || Odd/even frame of tokens written
|-
|}

=== Control register ===
{|border="1" cellpadding="2"
! bit # !! Signal || Destination block !! Comments
|-
| '''0''' || || Not used ||
|-
| '''1..2''' || cb_bayer_phase || compressor, sensorpix, histogram ||
|-
| '''3''' || || sensorpads || Inverts idclk phase (Not used)
|-
| '''4''' || cb_fillfactory || sensorpads || fillfactory sensor mode
|-
| '''5''' || cb_dlyhact || sensorpads || delay hact pulse by 1
|-
| '''6''' || cb_zoran || sensorpads || ''cb_zoran''
|-
| '''7''' || cb_skipline || sensorpads || skip first scan line from the sensor
|-
| '''8''' || cb_xt_pol || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || iarst || sensorpads || ''iarst''
|-
| '''10''' || iaro || sensorpads || ''iaro''
|-
| '''11''' || cb_encnvclk || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || cb_sensor_trigger || sensorpads || sensor trigger
|-
| '''13''' || imrst || sensorpads || ''imrst''
|-
| '''14''' || cb_scl0_o || iobuf || XRST (output pin)
|-
| '''15''' || cb_scl0_o || i2cpads || scl0 out
|-
| '''16''' || cb_scl0_en || i2cpads || scl0 enable
|-
| '''17''' || cb_sda0_o || i2cpads || sda0 out
|-
| '''18''' || cb_sda0_en || i2cpads || sda0 enable
|-
| '''19''' || cb_dclkmode || sensorpads || dclkmode
|-
| '''20''' || cb_pxd14 || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || cb_latehact || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || || Not used ||
|-
| '''24..25''' || cb_pclksrc || BUFGMUX || pclk source
|-
| '''28..30''' || || Not used ||
|-
| '''31''' || || Not used ||
|-
|}

=== Others ===

== See also ==

*[http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ 353 Theora CVS]
*[[Theora]]
*[[FPGA_Development_in_Elphel_cameras|FPGA Development in Elphel cameras]]
*[[Design Ideas|FPGA Theora Encoder for Videoconferencing]]
*[[10353]]

Porting Theora to 353 cameras

2008-04-09T15:09:09Z

JeremViewsurf: /* Compressor */

Elphel model 333 cameras were able to encode and stream Ogg Theora with 6.3.9 firmware. However, this model is no longer produced by Elphel. The goal of this project is to use the full potential of 353 cameras (larger FPGA, faster CPU) in order to port the Ogg Theora feature on the new hardware. First, the camera should be able to upload small Theora clips via FTP.

Different solutions are possible as previously mentioned in the [[Theora]] page :
* Instantiate both the Theora compressor and the MJPEG compressor in the FPGA since the new Spartan 3E seems to be large enough to handle the two features.
* Replace the existing MJPEG compressor with the Theora compressor and implement software Theora to JPEG conversion if JPEG is needed.
* Replace the existing MJPEG compressor in the 353 camera with the Theora compressor and keep two configuration files on the camera filesystem (one for Theora the other for MJPEG). FPGA code could be changed at run-time according to the needs.

Dealing with the last solution seems to be a good start for this project as the other features mentioned can be added later. In all cases, both FPGA code and software code will need to be adapted.

The source code of this project is available at [http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/]
== Hardware updates ==

=== Compressor ===
[[Image:Schematic.png|frame|[[Media:Schematic.png|333 Theora design with the 2 stage compressor and the 8-channel memory controller]]]]
Replace the MJPEG compressor in the 353 with the 333 Theora compressor ([http://elphel.cvs.sourceforge.net/elphel/camera333/fpga/x333 333 Theora FPGA code]). Maybe some adaptations need to be done within the Theora compressor itself. However, assuming that the compressor worked in 333 cameras a simple instantiation should suffice.

=== Memory controller ===
Replace the 4-channel memory controller with an 8 channel memory interface as in the 333 model in order to handle Theora specific data.

{|border="1" cellpadding="2"
! Channel !! 333 Theora !! 353
|-
| '''0''' || 8/16 bit data from sensor to SDRAM || Data from the sensor (it can be combined with FPN correction data) to the SDRAM in either 8-bit mode or 16-bit
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module || Reads FPN data from SDRAM (8bit - subtract, 8 bit - scale) and feeds it to FPGA for FPN correction of the data on the way from sensor to SDRAM (through channel 0)
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor || Provides data to JPEG encoder in 16x16x8bit MCUs. It can also provide data directly to CPU through DMA bypassing any compression
|-
| '''3''' || PIO read/write of SDRAM data || Provides bidirectional access from CPU through 8x32 bit window.
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM ||
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM ||
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63] ||
|-
| '''7''' || reading 12-bit pre-tokens from SDRAM in indexed coded order ||
|-
|}

=== Sensor interface ===
''sensorpix'' block must be adapted in order to provide a coherent interface between the memory controller and the sensor (channels 0 and 1)

=== System Interface ===
Adapt the system interface to assure communication between FPGA and its environment.

A feature of the system interface is to establish communication between the system CPU and the different blocks within the FPGA (compressor, memory controller etc). This is done by selecting a block with the address bus ''a[12:0]'' connected to the internal address bus ''ial[7:0]'':

'''x353.v'''
always @ (posedge cwr) begin
a0[7:0]<=ial[7:0]; // may want to change to just ia if ia will be late enough;
wnr0 <= ~irnw;
da_ctl0 <= (ial[7:0]==8'h00); // 0x00 WE to control 32-bit register (1 loc)
da_dmamode0 <= (ial[7:0]==8'h01); // 0x01 select writing to dma_cntr/dma_raw (1 loc)
da_sensormode0 <= (ial[7:0]==8'h02); // 0x02 select writing to sensorpix (1 loc)
...
da_compressor0 <= (ial[7:1]==7'h06); // 0x0c..0x0d - will be farther decoded in the compressor module
...

Since memory controller and compressor are to be replaced these addresses have to be adapted.

''353 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x09''' || da_saturation0 || write color saturation values
|-
| '''0x0a''' || da_framesync_dly0 || write frame sync interrupt delay (in scan lines)
|-
| '''0x0c..0x0d''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x0e''' || da_table_a0 || write tables address
|-
| '''0x0f''' || twr0 || write tables data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts0 || interrupt control
|-
| '''0x20..0x2f''' || da_dswe0 || select reading/writing to mcontr (16 locations)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist0 || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc0 || real time clock
|-
| '''0x48''' || da_timestamp0 || write timestamp mode
|-
| '''0x74''' || da_xjtag0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync0 || control of external sync module 0x78 - 0x7b
|-
|}

''333 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or aftre trigger)
|-
| '''0x06''' || da_interrupts0 || interrupt mask
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x10''' || da_debug || write 0x10 any - load debug shift, read (through cs4) -shift
|-
| '''0x20..0x27''' || da_mcontr0 || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table0 || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
|}

Addresses 0x01,2,3,4,5,6,8 and 0x30 can be kept in the 353 system interface. The interrupt mask address 0x06 in the 333 sys interface is no longer used (353 uses interrupt vectors). The Theora compressor and the new memory controller addresses have to be mapped again in the new design (addresses 0x0c..0x0d and 0x20 to 0x2f in the 353 sys interface).

=== Interrupts ===
Adapt the Theora compressor interrupts to the 353 interrupt vector .

The 353 interrupt vector can handle up to 16 different irq. However, only irq 0 to 7 are used :
'''x353.v'''

assign irq_in= {8'b0, // extra
compressor_done_compress, // 7 - will go high after all data is sent out (reset by compressor)
compressor_done_input, // 6 - will go high after EOT and persist until DCT is enabled (reset by compressor)
dcc_rdy, // 5 - obsolete in 333 - channel3 has 128 more dc coefficients (or some if the compression is finished)
compressor_eot, // 4 - compressor read in the last MCU (predictable time to end of transfer)
sr_sensortrig[2], // 3 - (sync to pclk) - level, reset by writing to sensor triggering command register
xfer_over_irq, // 2 - (sync to pclk) - frame acquisition over
trig_irq, // 1 - (sync to pclk) - external trigger
vacts}; // 0 - (sync to pclk) - frame sync

353 MJPEG compressor triggers irqs 4, 6 and 7. 333 Theora compressor is the source of two irqs :
'''compressor_all.v'''

done, // single-cycle pulse when the compressed frame is sent out (IRQ source).
reset_compress, // reset compressor done interrupt (writing any compressor command)

Adaptation should consist of assigning Theora compressor irq sources to vectors 6 and 7 for example if the MJPEG compressor is to be replaced.

=== DMA FIFOs ===
353 design uses 2 DMA FIFOs between the compressor and the system interface instead of one for the 333 Theora compressor. The two DMA FIFOs have also slight differences between the two design. Maybe a single 333 FIFO should be kept for the final design (?)

=== FPGA -> CPU data out MUX ===
The purpose of this MUX is to route data out from the different FPGA blocks to the system interface and then to the data bus to the CPU. The selection is made with the internal address bus ''ia''.
_
--| \
--| |
--| |
--| |--- iod[31:0] -> to system interface
--| |
--| |
|_/
from system interface -> ia[7:0]__|

'' 333 MUX ''
{|border="1" cellpadding="2"
! Adress range !! ia(5) !! ia(4) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''1''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''1''' || '''0''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''1''' || '''1''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0.. (even)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''0''' || dma_d0[31:0] || DMA 0 data
|-
| '''0x0.. (odd)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''1''' || dma_d1[31:0] || DMA 1 data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''X''' || '''X''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''X''' || '''X''' || dsdo[31:0] || Data out from descriptor memory
|-
| '''0x3..''' || '''0''' || '''1''' || '''1''' || '''X''' || '''X''' || bdo[31:0] || 32-bit data from SDRAM channel3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''X''' || '''0''' || '''X''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''X''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''X''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''X''' || '''X''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''X''' || '''X''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

'' 333 MUX ''
{|border="1" cellpadding="2"
! Address || ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || {24'b0,irqr[7:0]} || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(2) !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''0''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''0''' || '''1''' || '''1''' || MODELREV || Model revision
|-
| '''0x14''' || '''1''' || '''X''' || '''0''' || {8'h0,imgptr[23:0]} || Image pointer in 32-byte chunks
|-
| '''0x15''' || '''1''' || '''X''' || '''1''' || hifreq[31:0] || Accumulated high-freq components
|-
|}

'' 333 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock0
|-
| '''2''' || sr_sda1 || I2C
|-
| '''3''' || sr_scl1 || I2C clock1
|-
| '''4..12''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''17''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''18''' || 1'b0 || 0x0
|-
| '''19''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''20''' || itrig || TRIG input
|-
| '''21..22''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)
, 01 - clock is too late
, 10 - clock is too early
, 11 - OK (some measurements show too late, some - too early)
|-
| '''23''' || dcm_done ||
|-
| '''24''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''25''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''26''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''27''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''28''' || tok_frame_num_wr || Odd/even frame of tokens written
|-
| '''29''' || 1'b0 || 0x0
|-
| '''30''' || debug_out || Debug shift register output
|-
| '''31''' || 'b0 || 0x0
|-
|}

'' 353 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2''' || sr_ch0rdy || Ready to write next page (channel 0) SENSOR->SDRAM
|-
| '''3''' || sr_ch1rdy || Ready to read next page (channel 1) SDRAM->FPN(SENSOR)
|-
| '''4''' || sr_ch2rdy || Ready to read next page (channel 2) SDRAM->DMA
|-
| '''5''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''6''' || sr_wrempty || CPU write buffer empty (valid only in write mode). May reprogram channel3.
|-
| '''7..10''' || sr_nextFrame[3:0] || (level) generated before actual block is filled - needed to be combined with the pulse from buffer control
|-
| '''11..13''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''14''' || dcc_rdy || 128 of DC components from JPEG encoder are available (same as interrupt)
|-
| '''15''' || compressor_done_input || will go high after EOT and persist until DCT is enabled
|-
| '''16''' || compressor_done_compress || will go high after all data is sent out
|-
| '''17''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''19..18''' || dcm_err[1:0] || SDRAM DCM phase error
|-
| '''20''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''21''' || dcm_locked || SDRAM DCM overflow
|-
| '''22''' || dcm_status[0] || SDRAM DCM overflow
|-
| '''24..23''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''25''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''26''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''27''' || sens_dcm_status[0] || Sensor DCM overflow
|-
| '''28''' || clockios_locked || dcm locked
|-
| '''29..30''' || clockios_status[1:0] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''31''' || 1'b0 || 0x0
|-
|}

=== Control register ===
The dcr[31:0] bus is used to control the different blocks according to the control register values. The control register can be directly written by the CPU at the address 0x00.

''333 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0..2''' || Not used ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || iobuf || EXPS (output pin)
|-
| '''12''' || iobuf || EXPS (output pin)
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || i2cpads || scl1 out
|-
| '''20''' || i2cpads || scl1 enable
|-
| '''21''' || i2cpads || sda1 out
|-
| '''22''' || i2cpads || sda1 enable
|-
| '''23''' || Not used ||
|-
| '''24..27''' || clock_pclk || pclk source
|-
| '''28..30''' || Not used ||
|-
| '''31''' || clock_pclk || clk enable
|-
|}

''353 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0''' || Not used ||
|-
| '''1..2''' || compressor, sensorpix, histogram ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || sensorpads || sensor trigger
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || sensorpads || dclkmode
|-
| '''20''' || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || Not used ||
|-
| '''24..25''' || BUFGMUX || pclk source
|-
| '''28..30''' || compressor ||
|-
| '''31''' || clock_pclk ||
|-
|}

=== Others ===
* Looks like Theora compressor requires 90° phase clock that was abandoned in the 353 design.
Using different phases reduces AC component of the current through the power/ground lines of the FPGA by spreading register transitions. Theora has larger core so it may help spreading phases.--[[User:Andrey.filippov|Andrey.filippov]] 13:45, 25 February 2008 (CST)
* ...?

== Software updates ==

* Adapt FPGA definitions ([http://elphel.cvs.sourceforge.net/elphel/elphel353/elphel353/os/linux-2.6-tag--devboard-R2_01-1/arch/cris/arch-v32/drivers/elphel/x353.h?revision=1.8&view=markup&sortdir=down x353.h]) and most likely some other FPGA drivers.
* ...?

These lists of update are obviously incomplete. They need to be more detailed in order to make an exhaustive list of the changes that have to be done.

== 353 Theora new design ==
=== Compressor ===

Writing tables in compressor (and mcontr8ch) is the same than the 333 design :
* ia = 0x2d and idi = table address
* ia = 0x2c and idi = table data

=== Sensorpix ===

Most of the 353 design was used for the new design. Writing procedure for gamma tables in sensorpix block is the same than in 353 (ie with ta bus and twr_gamma signal).

=== Memory controller ===

{|border="1" cellpadding="2"
! Channel !! Description
|-
| '''0''' || 8/16 bit data from sensor to SDRAM
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor
|-
| '''3''' || PIO read/write of SDRAM data
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63]
|-
| '''7''' || Reading 12-bit pre-tokens from SDRAM in indexed coded order
|-
|}

=== System interface ===

{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm || tune SDRAM clock phase
|-
| '''0x0a''' || da_framesync_dly || write frame sync interrupt delay (in scan lines)
|-
| '''0x0e''' || da_table_a0 || write gamma table address
|-
| '''0x0f''' || twr0 || write gamma table data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts || interrupt control
|-
| '''0x20..0x27''' || da_mcontr || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc || real time clock
|-
| '''0x48''' || da_timestamp || write timestamp mode
|-
| '''0x74''' || da_xjta0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync || control of external sync module 0x78 - 0x7b
|-
|}

=== Interrupts ===

{|border="1" cellpadding="2"
! irq_in !! Signal !! Comments
|-
| '''15..8''' || GND || Extra
|-
| '''7''' || compressor_done_compress || single-cycle pulse when the compressed frame is sent out
|-
| '''6''' || compressor_reset_compress || reset compressor done interrupt (writing any compressor command)
|-
| '''5''' || GND || dcc_rdy was tied to GND in the 333 design
|-
| '''4''' || GND || eot irq was tied to GND in the 333 design
|-
| '''3''' || sr_sensortrig[2] || (sync to pclk) - level, reset by writing to sensor triggering command register
|-
| '''2''' || xfer_over_irq || (sync to pclk) - frame acquisition over
|-
| '''1''' || trig_irq || (sync to pclk) - external trigger
|-
| '''0''' || vacts || (sync to pclk) - frame sync
|-
|}

=== DMA FIFOs ===
A single DMA FIFO from the 333 design will be instanciated.

=== FPGA -> CPU data out MUX ===

{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || '''0''' || '''x''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''x''' || '''x''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''x''' || '''0''' || '''x''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''x''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''x''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''x''' || '''x''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''x''' || '''x''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

{|border="1" cellpadding="2"
! Address !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' Status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C data
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2..10''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''11''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''12''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''17..18''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)

, 01 - clock is too late , 10 - clock is too early , 11 - OK (some measurements show too late, some - too early)
|-
| '''19''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''20''' || dcm_locked || SDRAM DCM overflow
|-
| '''21..22''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''23''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''24''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''25''' || clockios_locked || dcm locked
|-
| '''26''' || clockios_status[1] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''27''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''28''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''29''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''30''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''31''' || took_frame_num_wr || Odd/even frame of tokens written
|-
|}

=== Control register ===
{|border="1" cellpadding="2"
! bit # !! Signal || Destination block !! Comments
|-
| '''0''' || || Not used ||
|-
| '''1..2''' || cb_bayer_phase || compressor, sensorpix, histogram ||
|-
| '''3''' || || sensorpads || Inverts idclk phase (Not used)
|-
| '''4''' || cb_fillfactory || sensorpads || fillfactory sensor mode
|-
| '''5''' || cb_dlyhact || sensorpads || delay hact pulse by 1
|-
| '''6''' || cb_zoran || sensorpads || ''cb_zoran''
|-
| '''7''' || cb_skipline || sensorpads || skip first scan line from the sensor
|-
| '''8''' || cb_xt_pol || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || iarst || sensorpads || ''iarst''
|-
| '''10''' || iaro || sensorpads || ''iaro''
|-
| '''11''' || cb_encnvclk || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || cb_sensor_trigger || sensorpads || sensor trigger
|-
| '''13''' || imrst || sensorpads || ''imrst''
|-
| '''14''' || cb_scl0_o || iobuf || XRST (output pin)
|-
| '''15''' || cb_scl0_o || i2cpads || scl0 out
|-
| '''16''' || cb_scl0_en || i2cpads || scl0 enable
|-
| '''17''' || cb_sda0_o || i2cpads || sda0 out
|-
| '''18''' || cb_sda0_en || i2cpads || sda0 enable
|-
| '''19''' || cb_dclkmode || sensorpads || dclkmode
|-
| '''20''' || cb_pxd14 || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || cb_latehact || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || || Not used ||
|-
| '''24..25''' || cb_pclksrc || BUFGMUX || pclk source
|-
| '''28..30''' || || Not used ||
|-
| '''31''' || || Not used ||
|-
|}

=== Others ===

== See also ==

*[http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ 353 Theora CVS]
*[[Theora]]
*[[FPGA_Development_in_Elphel_cameras|FPGA Development in Elphel cameras]]
*[[Design Ideas|FPGA Theora Encoder for Videoconferencing]]
*[[10353]]

Porting Theora to 353 cameras

2008-04-09T15:00:33Z

JeremViewsurf: /* Sensorpix */

Elphel model 333 cameras were able to encode and stream Ogg Theora with 6.3.9 firmware. However, this model is no longer produced by Elphel. The goal of this project is to use the full potential of 353 cameras (larger FPGA, faster CPU) in order to port the Ogg Theora feature on the new hardware. First, the camera should be able to upload small Theora clips via FTP.

Different solutions are possible as previously mentioned in the [[Theora]] page :
* Instantiate both the Theora compressor and the MJPEG compressor in the FPGA since the new Spartan 3E seems to be large enough to handle the two features.
* Replace the existing MJPEG compressor with the Theora compressor and implement software Theora to JPEG conversion if JPEG is needed.
* Replace the existing MJPEG compressor in the 353 camera with the Theora compressor and keep two configuration files on the camera filesystem (one for Theora the other for MJPEG). FPGA code could be changed at run-time according to the needs.

Dealing with the last solution seems to be a good start for this project as the other features mentioned can be added later. In all cases, both FPGA code and software code will need to be adapted.

The source code of this project is available at [http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/]
== Hardware updates ==

=== Compressor ===
[[Image:Schematic.png|frame|[[Media:Schematic.png|333 Theora design with the 2 stage compressor and the 8-channel memory controller]]]]
Replace the MJPEG compressor in the 353 with the 333 Theora compressor ([http://elphel.cvs.sourceforge.net/elphel/camera333/fpga/x333 333 Theora FPGA code]). Maybe some adaptations need to be done within the Theora compressor itself. However, assuming that the compressor worked in 333 cameras a simple instantiation should suffice.

=== Memory controller ===
Replace the 4-channel memory controller with an 8 channel memory interface as in the 333 model in order to handle Theora specific data.

{|border="1" cellpadding="2"
! Channel !! 333 Theora !! 353
|-
| '''0''' || 8/16 bit data from sensor to SDRAM || Data from the sensor (it can be combined with FPN correction data) to the SDRAM in either 8-bit mode or 16-bit
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module || Reads FPN data from SDRAM (8bit - subtract, 8 bit - scale) and feeds it to FPGA for FPN correction of the data on the way from sensor to SDRAM (through channel 0)
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor || Provides data to JPEG encoder in 16x16x8bit MCUs. It can also provide data directly to CPU through DMA bypassing any compression
|-
| '''3''' || PIO read/write of SDRAM data || Provides bidirectional access from CPU through 8x32 bit window.
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM ||
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM ||
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63] ||
|-
| '''7''' || reading 12-bit pre-tokens from SDRAM in indexed coded order ||
|-
|}

=== Sensor interface ===
''sensorpix'' block must be adapted in order to provide a coherent interface between the memory controller and the sensor (channels 0 and 1)

=== System Interface ===
Adapt the system interface to assure communication between FPGA and its environment.

A feature of the system interface is to establish communication between the system CPU and the different blocks within the FPGA (compressor, memory controller etc). This is done by selecting a block with the address bus ''a[12:0]'' connected to the internal address bus ''ial[7:0]'':

'''x353.v'''
always @ (posedge cwr) begin
a0[7:0]<=ial[7:0]; // may want to change to just ia if ia will be late enough;
wnr0 <= ~irnw;
da_ctl0 <= (ial[7:0]==8'h00); // 0x00 WE to control 32-bit register (1 loc)
da_dmamode0 <= (ial[7:0]==8'h01); // 0x01 select writing to dma_cntr/dma_raw (1 loc)
da_sensormode0 <= (ial[7:0]==8'h02); // 0x02 select writing to sensorpix (1 loc)
...
da_compressor0 <= (ial[7:1]==7'h06); // 0x0c..0x0d - will be farther decoded in the compressor module
...

Since memory controller and compressor are to be replaced these addresses have to be adapted.

''353 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x09''' || da_saturation0 || write color saturation values
|-
| '''0x0a''' || da_framesync_dly0 || write frame sync interrupt delay (in scan lines)
|-
| '''0x0c..0x0d''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x0e''' || da_table_a0 || write tables address
|-
| '''0x0f''' || twr0 || write tables data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts0 || interrupt control
|-
| '''0x20..0x2f''' || da_dswe0 || select reading/writing to mcontr (16 locations)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist0 || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc0 || real time clock
|-
| '''0x48''' || da_timestamp0 || write timestamp mode
|-
| '''0x74''' || da_xjtag0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync0 || control of external sync module 0x78 - 0x7b
|-
|}

''333 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or aftre trigger)
|-
| '''0x06''' || da_interrupts0 || interrupt mask
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x10''' || da_debug || write 0x10 any - load debug shift, read (through cs4) -shift
|-
| '''0x20..0x27''' || da_mcontr0 || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table0 || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
|}

Addresses 0x01,2,3,4,5,6,8 and 0x30 can be kept in the 353 system interface. The interrupt mask address 0x06 in the 333 sys interface is no longer used (353 uses interrupt vectors). The Theora compressor and the new memory controller addresses have to be mapped again in the new design (addresses 0x0c..0x0d and 0x20 to 0x2f in the 353 sys interface).

=== Interrupts ===
Adapt the Theora compressor interrupts to the 353 interrupt vector .

The 353 interrupt vector can handle up to 16 different irq. However, only irq 0 to 7 are used :
'''x353.v'''

assign irq_in= {8'b0, // extra
compressor_done_compress, // 7 - will go high after all data is sent out (reset by compressor)
compressor_done_input, // 6 - will go high after EOT and persist until DCT is enabled (reset by compressor)
dcc_rdy, // 5 - obsolete in 333 - channel3 has 128 more dc coefficients (or some if the compression is finished)
compressor_eot, // 4 - compressor read in the last MCU (predictable time to end of transfer)
sr_sensortrig[2], // 3 - (sync to pclk) - level, reset by writing to sensor triggering command register
xfer_over_irq, // 2 - (sync to pclk) - frame acquisition over
trig_irq, // 1 - (sync to pclk) - external trigger
vacts}; // 0 - (sync to pclk) - frame sync

353 MJPEG compressor triggers irqs 4, 6 and 7. 333 Theora compressor is the source of two irqs :
'''compressor_all.v'''

done, // single-cycle pulse when the compressed frame is sent out (IRQ source).
reset_compress, // reset compressor done interrupt (writing any compressor command)

Adaptation should consist of assigning Theora compressor irq sources to vectors 6 and 7 for example if the MJPEG compressor is to be replaced.

=== DMA FIFOs ===
353 design uses 2 DMA FIFOs between the compressor and the system interface instead of one for the 333 Theora compressor. The two DMA FIFOs have also slight differences between the two design. Maybe a single 333 FIFO should be kept for the final design (?)

=== FPGA -> CPU data out MUX ===
The purpose of this MUX is to route data out from the different FPGA blocks to the system interface and then to the data bus to the CPU. The selection is made with the internal address bus ''ia''.
_
--| \
--| |
--| |
--| |--- iod[31:0] -> to system interface
--| |
--| |
|_/
from system interface -> ia[7:0]__|

'' 333 MUX ''
{|border="1" cellpadding="2"
! Adress range !! ia(5) !! ia(4) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''1''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''1''' || '''0''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''1''' || '''1''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0.. (even)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''0''' || dma_d0[31:0] || DMA 0 data
|-
| '''0x0.. (odd)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''1''' || dma_d1[31:0] || DMA 1 data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''X''' || '''X''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''X''' || '''X''' || dsdo[31:0] || Data out from descriptor memory
|-
| '''0x3..''' || '''0''' || '''1''' || '''1''' || '''X''' || '''X''' || bdo[31:0] || 32-bit data from SDRAM channel3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''X''' || '''0''' || '''X''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''X''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''X''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''X''' || '''X''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''X''' || '''X''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

'' 333 MUX ''
{|border="1" cellpadding="2"
! Address || ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || {24'b0,irqr[7:0]} || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(2) !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''0''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''0''' || '''1''' || '''1''' || MODELREV || Model revision
|-
| '''0x14''' || '''1''' || '''X''' || '''0''' || {8'h0,imgptr[23:0]} || Image pointer in 32-byte chunks
|-
| '''0x15''' || '''1''' || '''X''' || '''1''' || hifreq[31:0] || Accumulated high-freq components
|-
|}

'' 333 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock0
|-
| '''2''' || sr_sda1 || I2C
|-
| '''3''' || sr_scl1 || I2C clock1
|-
| '''4..12''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''17''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''18''' || 1'b0 || 0x0
|-
| '''19''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''20''' || itrig || TRIG input
|-
| '''21..22''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)
, 01 - clock is too late
, 10 - clock is too early
, 11 - OK (some measurements show too late, some - too early)
|-
| '''23''' || dcm_done ||
|-
| '''24''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''25''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''26''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''27''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''28''' || tok_frame_num_wr || Odd/even frame of tokens written
|-
| '''29''' || 1'b0 || 0x0
|-
| '''30''' || debug_out || Debug shift register output
|-
| '''31''' || 'b0 || 0x0
|-
|}

'' 353 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2''' || sr_ch0rdy || Ready to write next page (channel 0) SENSOR->SDRAM
|-
| '''3''' || sr_ch1rdy || Ready to read next page (channel 1) SDRAM->FPN(SENSOR)
|-
| '''4''' || sr_ch2rdy || Ready to read next page (channel 2) SDRAM->DMA
|-
| '''5''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''6''' || sr_wrempty || CPU write buffer empty (valid only in write mode). May reprogram channel3.
|-
| '''7..10''' || sr_nextFrame[3:0] || (level) generated before actual block is filled - needed to be combined with the pulse from buffer control
|-
| '''11..13''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''14''' || dcc_rdy || 128 of DC components from JPEG encoder are available (same as interrupt)
|-
| '''15''' || compressor_done_input || will go high after EOT and persist until DCT is enabled
|-
| '''16''' || compressor_done_compress || will go high after all data is sent out
|-
| '''17''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''19..18''' || dcm_err[1:0] || SDRAM DCM phase error
|-
| '''20''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''21''' || dcm_locked || SDRAM DCM overflow
|-
| '''22''' || dcm_status[0] || SDRAM DCM overflow
|-
| '''24..23''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''25''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''26''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''27''' || sens_dcm_status[0] || Sensor DCM overflow
|-
| '''28''' || clockios_locked || dcm locked
|-
| '''29..30''' || clockios_status[1:0] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''31''' || 1'b0 || 0x0
|-
|}

=== Control register ===
The dcr[31:0] bus is used to control the different blocks according to the control register values. The control register can be directly written by the CPU at the address 0x00.

''333 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0..2''' || Not used ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || iobuf || EXPS (output pin)
|-
| '''12''' || iobuf || EXPS (output pin)
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || i2cpads || scl1 out
|-
| '''20''' || i2cpads || scl1 enable
|-
| '''21''' || i2cpads || sda1 out
|-
| '''22''' || i2cpads || sda1 enable
|-
| '''23''' || Not used ||
|-
| '''24..27''' || clock_pclk || pclk source
|-
| '''28..30''' || Not used ||
|-
| '''31''' || clock_pclk || clk enable
|-
|}

''353 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0''' || Not used ||
|-
| '''1..2''' || compressor, sensorpix, histogram ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || sensorpads || sensor trigger
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || sensorpads || dclkmode
|-
| '''20''' || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || Not used ||
|-
| '''24..25''' || BUFGMUX || pclk source
|-
| '''28..30''' || compressor ||
|-
| '''31''' || clock_pclk ||
|-
|}

=== Others ===
* Looks like Theora compressor requires 90° phase clock that was abandoned in the 353 design.
Using different phases reduces AC component of the current through the power/ground lines of the FPGA by spreading register transitions. Theora has larger core so it may help spreading phases.--[[User:Andrey.filippov|Andrey.filippov]] 13:45, 25 February 2008 (CST)
* ...?

== Software updates ==

* Adapt FPGA definitions ([http://elphel.cvs.sourceforge.net/elphel/elphel353/elphel353/os/linux-2.6-tag--devboard-R2_01-1/arch/cris/arch-v32/drivers/elphel/x353.h?revision=1.8&view=markup&sortdir=down x353.h]) and most likely some other FPGA drivers.
* ...?

These lists of update are obviously incomplete. They need to be more detailed in order to make an exhaustive list of the changes that have to be done.

== 353 Theora new design ==
=== Compressor ===

=== Sensorpix ===

Most of the 353 design was used for the new design. Writing procedure for gamma tables in sensorpix block is the same than in 353 (ie with ta bus and twr_gamma signal).

=== Memory controller ===

{|border="1" cellpadding="2"
! Channel !! Description
|-
| '''0''' || 8/16 bit data from sensor to SDRAM
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor
|-
| '''3''' || PIO read/write of SDRAM data
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63]
|-
| '''7''' || Reading 12-bit pre-tokens from SDRAM in indexed coded order
|-
|}

=== System interface ===

{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm || tune SDRAM clock phase
|-
| '''0x0a''' || da_framesync_dly || write frame sync interrupt delay (in scan lines)
|-
| '''0x0e''' || da_table_a0 || write gamma table address
|-
| '''0x0f''' || twr0 || write gamma table data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts || interrupt control
|-
| '''0x20..0x27''' || da_mcontr || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc || real time clock
|-
| '''0x48''' || da_timestamp || write timestamp mode
|-
| '''0x74''' || da_xjta0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync || control of external sync module 0x78 - 0x7b
|-
|}

=== Interrupts ===

{|border="1" cellpadding="2"
! irq_in !! Signal !! Comments
|-
| '''15..8''' || GND || Extra
|-
| '''7''' || compressor_done_compress || single-cycle pulse when the compressed frame is sent out
|-
| '''6''' || compressor_reset_compress || reset compressor done interrupt (writing any compressor command)
|-
| '''5''' || GND || dcc_rdy was tied to GND in the 333 design
|-
| '''4''' || GND || eot irq was tied to GND in the 333 design
|-
| '''3''' || sr_sensortrig[2] || (sync to pclk) - level, reset by writing to sensor triggering command register
|-
| '''2''' || xfer_over_irq || (sync to pclk) - frame acquisition over
|-
| '''1''' || trig_irq || (sync to pclk) - external trigger
|-
| '''0''' || vacts || (sync to pclk) - frame sync
|-
|}

=== DMA FIFOs ===
A single DMA FIFO from the 333 design will be instanciated.

=== FPGA -> CPU data out MUX ===

{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || '''0''' || '''x''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''x''' || '''x''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''x''' || '''0''' || '''x''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''x''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''x''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''x''' || '''x''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''x''' || '''x''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

{|border="1" cellpadding="2"
! Address !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' Status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C data
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2..10''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''11''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''12''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''17..18''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)

, 01 - clock is too late , 10 - clock is too early , 11 - OK (some measurements show too late, some - too early)
|-
| '''19''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''20''' || dcm_locked || SDRAM DCM overflow
|-
| '''21..22''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''23''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''24''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''25''' || clockios_locked || dcm locked
|-
| '''26''' || clockios_status[1] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''27''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''28''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''29''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''30''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''31''' || took_frame_num_wr || Odd/even frame of tokens written
|-
|}

=== Control register ===
{|border="1" cellpadding="2"
! bit # !! Signal || Destination block !! Comments
|-
| '''0''' || || Not used ||
|-
| '''1..2''' || cb_bayer_phase || compressor, sensorpix, histogram ||
|-
| '''3''' || || sensorpads || Inverts idclk phase (Not used)
|-
| '''4''' || cb_fillfactory || sensorpads || fillfactory sensor mode
|-
| '''5''' || cb_dlyhact || sensorpads || delay hact pulse by 1
|-
| '''6''' || cb_zoran || sensorpads || ''cb_zoran''
|-
| '''7''' || cb_skipline || sensorpads || skip first scan line from the sensor
|-
| '''8''' || cb_xt_pol || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || iarst || sensorpads || ''iarst''
|-
| '''10''' || iaro || sensorpads || ''iaro''
|-
| '''11''' || cb_encnvclk || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || cb_sensor_trigger || sensorpads || sensor trigger
|-
| '''13''' || imrst || sensorpads || ''imrst''
|-
| '''14''' || cb_scl0_o || iobuf || XRST (output pin)
|-
| '''15''' || cb_scl0_o || i2cpads || scl0 out
|-
| '''16''' || cb_scl0_en || i2cpads || scl0 enable
|-
| '''17''' || cb_sda0_o || i2cpads || sda0 out
|-
| '''18''' || cb_sda0_en || i2cpads || sda0 enable
|-
| '''19''' || cb_dclkmode || sensorpads || dclkmode
|-
| '''20''' || cb_pxd14 || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || cb_latehact || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || || Not used ||
|-
| '''24..25''' || cb_pclksrc || BUFGMUX || pclk source
|-
| '''28..30''' || || Not used ||
|-
| '''31''' || || Not used ||
|-
|}

=== Others ===

== See also ==

*[http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ 353 Theora CVS]
*[[Theora]]
*[[FPGA_Development_in_Elphel_cameras|FPGA Development in Elphel cameras]]
*[[Design Ideas|FPGA Theora Encoder for Videoconferencing]]
*[[10353]]

Talk:Porting Theora to 353 cameras

2008-04-09T09:50:00Z

JeremViewsurf:

Ok, I started a new page on the Theora project in 353 cameras. I started with a global approach and a list of modules that need to be changed or replaced on the 353 model. Feel free to correct me or add suggestions as I'm not (yet...) an expert on Elphel cameras. I think the first step is to make an exhaustive list of the hardware blocks that need modifications and then detail what need to be done in each block. --[[User:JeremViewsurf|JeremViewsurf]] 03:48, 19 February 2008 (CST)

As I understand your first need is not a streaming but producing a small video clip to be uploaded via FTP. This can be done more easy with minimal non FPGA modifications.

We will probably create a CVS branch for your port, to be able to test it we need to compile a standard 7.1.x firmware disabling everything sensor or FPGA related and change the FPGA bitstream. --[[User:Polto|Alexandre.Poltorak]] 07:53, 19 February 2008 (CST)

You mean that it should be possible that the system can handle software Ogg Theora encoding for a non real-time application such as producing small video clips ? I'm aware that it depends on the output resolution, framerate and length of the clip but does a 1 min 1024x768 @ 25fps clip for example can be processed in a reasonable delay ? I'll discuss with Viewsurf's development team in order to obtain more precise specs concerning video output (in terms of length, resolution, framerate and encoding delay acceptable) but if you can give me an idea of what the software part can handle, I would consider spending more time in soft Theora transcoding instead of FPGA design. --[[User:JeremViewsurf|JeremViewsurf]] 03:37, 20 February 2008 (CST)

No, sorry i was not speaking of transcoding. It would take too much calculation power and is not possible on the camera's CPU. The Theora encoding should be done in FPGA. What i was speaking about is the software part.. I think you do not need a streamer for the first steps. You only need to generate a clip in the FPGA memory, and upload it to a FTP. --[[User:Polto|Alexandre.Poltorak]] 08:32, 20 February 2008 (CST)

----

Some questions concerning changes in the FPGA :
* Is it necessary to keep histogram and timestamp blocks in a design which supports Theora only ?
** I believe the camera will be rather crippled w/o those features--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
* Is it possible to keep channel 0, 1 and 3 design without changes in the memory controller ?
** Theora implementation used different (more advanced) memory controller that the JPEG, it was getting 95% efficiency at Theora data structure, so you need Theora memory controller. But if you mean by "Channel 0 design" the gamma tables and histograms - yes, they probably could be ported (with some changes, of course). As for channels 1 and 3 - similar are available in Theora 333 also--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
* The 353 design uses 2 DMA fifos between the compressor and the system interface instead of one in the 333 design. Is it possible to keep only one 333 DMA fifo in the final design ?
** Yes, of course - but this is so minor difference. The more important is that in Theora that FIFO could make the compressor wait if ETRAX DMA is not ready - at the beginning of the frame in theora there is a data "burst".--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
* In the 353 design, all signals and blocks I/O concerning 90° phase clock are commented. Is it possible to uncomment them in order to restore the clock ?
** Maybe yes, more likely no. 353 and 333 use different FPGAs.--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
* Motion compensation seems not to be implemented in the Theora compressor yet. Is it possible to add this feature later in the compressor block without major changes in the final design ?
** No, I'm afraid that is not possible - I believe we need faster FPGA for that and likely faster/wider memory.--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
--[[User:JeremViewsurf|JeremViewsurf]] 02:43, 25 February 2008 (CST)

----

I'm currently working on the FPGA control register and I have a question concerning the I2C pads controlled by the control register (via dcr[16:21]). In the 333 design there are 2 I2C "channels" : (sda0,scl0) and (sda1,scl1) and only one on the 353 design. Is it possible to keep a single i2c channel on the new design ? In other ways, what is the purpose of the i2c "channels" in each device ? --[[User:JeremViewsurf|JeremViewsurf]] 03:19, 3 March 2008 (CST)

The later 353 software also has 2 I2C channels, similar to 333. One channel is designed to communicate to the sensor (and goes through 30-pin flex cable), the other - to additional boards that sit on top of the 353, that I2C bus uses 2 bits (0,1) of the 12-bit GPIO of the 353 FPGA. It is currently used by multiple I2C peripherals on teh 10369 board (IDE bus configuration, clock/calendar, temperature sensor/fan control, EEPROM, USB hub configuration --[[User:Andrey.filippov|Andrey.filippov]] 12:27, 5 March 2008 (CST)

----

I tried to implement the new design according to the specs I proposed on this article. I instantiated the Theora compressor and the 8-channel memory controller in the place of the former jpeg compressor and memory controller and adapted registers and addresses (see article). The synthesis of this design with ISE is completed without error but I expect more issues with the place & route procedure. It would be great if I could share this work on a CVS to have some critics and some support, we had a discussion about that with Alexandre but I'm still waiting for an account. Before going farther, I'm trying to run the simulation with Icarus but I'm experiencing some issues with the compilation :

channel0.v:154: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+('sd1)
channel1.v:152: error: operand of concatenation has indefinite width: (ntile_x[3:0])+('sd1)
channel1.v:155: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+('sd1)

I would appreciate some support concerning how to test and debug the new design since this seems to be a tough issue to deal with.

When simulating Theora I used Silos III simulator on Windows, some work is needed to make it work with Icarus. First step - patch Xilinx unisim library, then - go through code (maybe it needs width for sd1?. The other problem that will come out - in Silos tasks were reenterable, each instance having it's own set of local variables (I used it when simulating CPU interrupts), in Icarus - they all share the same.--[[User:Andrey.filippov|Andrey.filippov]] 12:27, 5 March 2008 (CST)
--[[User:JeremViewsurf|JeremViewsurf]] 08:57, 5 March 2008 (CST)

I fixed the previous compilation error in Icarus, in channel0.v and channel1.v replace
channel0.v:154: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+1
channel1.v:152: error: operand of concatenation has indefinite width: (ntile_x[3:0])+1
channel1.v:155: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+1

with

channel0.v:154: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+11'h1
channel1.v:152: error: operand of concatenation has indefinite width: (ntile_x[3:0])+4'h1
channel1.v:155: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+11'h1

I can finally visualize some chronograms in gtkwave however I'm using the old 353 testbench... Time to understand how the testbench is structured and to think about a smarter one to test the new design. --[[User:JeremViewsurf|JeremViewsurf]] 03:13, 6 March 2008 (CST)

----

I'm working on the simulation of the 333 Theora design (x333t.tf) and it looks like there are three simulation modes for this design that can be switched with 'define : MASTERMODE, MASTERMODE1,SINGLE_ST. What is the difference between these modes and how does each work in summary ? --[[User:JeremViewsurf|JeremViewsurf]] 10:45, 10 March 2008 (CDT)

The source code is now available on the Elphel CVS : [http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ | http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/]. The synthesis of this code is OK but it still have to be tested. I split the testbench between the main simulation sequence and the different tasks. The x353_sim.sh script is up to date but the simulation itself (x353_1.tf) is inadequate to test the design (it is still the old MJPEG testbench). The testbench in the 6.3.9 firmware (333 Theora) seems to fit better but I still need to know how it works precisely in order to adapt it to the 353 design. --[[User:JeremViewsurf|JeremViewsurf]] 09:22, 11 March 2008 (CDT)

----

Some news concerning the simulation of Theora on the 353 :
* I instantiated the x353t module with the sensor and the sdram.
* I'm trying to go through the initialization sequence
* The global initialization works (with glbl.v)
* The DCM reset works (SDRAM clocks SDCLK_D and SDNCLK_D are working)
* I didn't check if the tables programmation is ok yet
* The sdram initialization sequence works :

Initialize SDRAM

>> 214455.000 ns >> cpu_wr(21, 00017fff)
At time 214556.000 ns PRE : Addr[10] = 1, Bank = 11

>> 214605.000 ns >> cpu_wr(21, 00002002)
At time 214708.000 ns EMR : Extended Mode Register
At time 214708.000 ns EMR : Enable DLL

>> 214755.000 ns >> cpu_wr(21, 00000163)
At time 214860.000 ns LMR : Load Mode Register
At time 214860.000 ns LMR : Burst Length = 8
At time 214860.000 ns LMR : CAS Latency = 2.5

>> 214905.000 ns >> cpu_wr(21, 00017fff)
At time 215004.000 ns PRE : Addr[10] = 1, Bank = 11

>> 215055.000 ns >> cpu_wr(21, 00008000)
At time 215156.000 ns AREF : Auto Refresh

>> 215205.000 ns >> cpu_wr(21, 00008000)
At time 215308.000 ns AREF : Auto Refresh
testbench353t.i_mt46v16m16fg: at time 215308.000 ns MEMORY: Power Up and Initialization Sequence is complete

>> 215355.000 ns >> cpu_wr(21, 00000063)
At time 215460.000 ns LMR : Load Mode Register
At time 215460.000 ns LMR : Burst Length = 8
At time 215460.000 ns LMR : CAS Latency = 2.5

Initialize SDRAM done

I committed the changes to the CVS. --[[User:JeremViewsurf|JeremViewsurf]] 05:20, 19 March 2008 (CDT)

I checked the table programming (quantization, huffman, etc), the procedure seems ok. I finally have data output on the SDA and SDD ports after having replace the sensorpix and sensortrig blocks in the 353 with those that were in the 333 Theora (with some modifications in the width of some signals). However, the timings seems completely different between the two sensors and I experience memory overflow during the simulation :

...
At time 1498748.000 ns WRITE: Bank = 3, Row = 0034, Col = 06d, Data = 0000
At time 1498748.000 ns ERROR: Memory overflow.
Write to Address 180d06d with Data 0000 will be lost.
You must increase the part_mem_bits parameter or define FULL_MEM.
At time 1498748.000 ns WRITE: Bank = 3, Col = 070
At time 1498752.000 ns WRITE: Bank = 3, Row = 0034, Col = 06e, Data = 0000
At time 1498752.000 ns ERROR: Memory overflow.
Write to Address 180d06e with Data 0000 will be lost.
You must increase the part_mem_bits parameter or define FULL_MEM.
...

--[[User:JeremViewsurf|JeremViewsurf]] 11:46, 26 March 2008 (CDT)

Have you tried to increase "part_mem_bits"? It's in ddr_parameters.v
--[[User:Oleg|Oleg]] 20:06, 26 March 2008 (CDT)

I defined FULL_MEM in ddr.v to be sure, there is no more memory overflow error. However is the simulation still representative of reality ? --[[User:JeremViewsurf|JeremViewsurf]] 03:32, 27 March 2008 (CDT)

----

I have a question concerning the sensor in both 333 and 353 design. In the 333 the sensor has a 10 bit output that goes directly to the sensorpix module (through sensorpads) to a 10 bit input. However In the 353, the sensor has a 12 bit output that goes to the sensorpads module and is treated to produce a 16 bit output that goes to the sensorpix module. What is the purpose of the extra bits in the 353 design ? Is it possible to extract a 10 bit output from the 353 sensorpad module to feed a 333 sensorpix block ? It looks like that the higher 10 bits of the ipxd[15:0] signal are different from the lower 6 bits (the latter can be forced to 0 with the cnven signal). Are these 10 bits similar to the 10 bits output of the 333 sensor ?

'''sensorpads353.v'''
...
ipxd_pre[ 5:0] <= cnven?6'b0:{ipxded[3:2],pxd14?ipxded[1:0]:2'h0,2'h0};
ipxd_pre[15:6] <= ipxded[15:6];
ipxd[15:0] <= ipxd_pre[15:0];
...

--[[User:JeremViewsurf|JeremViewsurf]] 03:37, 31 March 2008 (CDT)

The 5MPix sensor does have 12 bit output and all the bits are used during "gamma"-table conversion to 8 bits. Even more - the same FPGA code now supports 10347 boards (for Kodak KAI-11002/16000 CCD sensors) that produce 14-bit data.

After the data (10-12-14 bits) reaches the FPGA, it can go two ways - through the LUT (with linear interpolation) conversion to 8 bits and raw - 2 bytes/pixel format, where pixel data is MSB-aligned (actually bit 14 being the highest, bit 15 is left 0 to allow subtraction without overflow). I believe you should use that part (from the sensor interface to the SDRAM - including gamma tables and histograms) the same for Theora as it is now in 353 (for JPEG)--[[User:Andrey.filippov|Andrey.filippov]] 12:09, 31 March 2008 (CDT)

----

I restored the sensorpix353 and sensortrig353 in the Theora design and tested the data path from the sensor to the dma output. Looks like there is no data coming out of the mcontr channel 7 (after the token read buffer). Same issue with the 333 Theora simulation although the design is obviously correct. This might be a flaw in the testbench (?) as I used somehow the same for the two designs. Moreover I can't simulated over 2ms and I can't figure out why the simulations stops at that time. Maybe the second stage of the compressor processes data after 2 ms so it is never reached by the simulator (?)

[[Image:Datapath.jpg]]

--[[User:JeremViewsurf|JeremViewsurf]] 05:17, 7 April 2008 (CDT)

"simulation over 2ms" - $stop in line 639 of x353t.tf finishes the simulation. And there's one file is missing in cvs - linear1028rgb.dat - Jeremy, could you upload it.--[[User:Oleg|Oleg]] 11:44, 8 April 2008 (CDT)

The missing file is now on the cvs, let me know if something else is missing. If you want to check the set of signals in my simulation above, use pxdpath.sav in gtkwave. Before $stop in line 639 of x353t.tf there is now a 5ms delay (#5000000) to let the simulation run, it stops at 700µs... --[[User:JeremViewsurf|JeremViewsurf]] 02:24, 9 April 2008 (CDT)

I'm now trying with a 5 ms delay and without $stop after the delay, the simulation is currently at 2.3 ms and is still running ! I looked at the waves, still no output after ch7. --[[User:JeremViewsurf|JeremViewsurf]] 03:44, 9 April 2008 (CDT)

Talk:Porting Theora to 353 cameras

2008-04-09T08:44:21Z

JeremViewsurf:

Ok, I started a new page on the Theora project in 353 cameras. I started with a global approach and a list of modules that need to be changed or replaced on the 353 model. Feel free to correct me or add suggestions as I'm not (yet...) an expert on Elphel cameras. I think the first step is to make an exhaustive list of the hardware blocks that need modifications and then detail what need to be done in each block. --[[User:JeremViewsurf|JeremViewsurf]] 03:48, 19 February 2008 (CST)

As I understand your first need is not a streaming but producing a small video clip to be uploaded via FTP. This can be done more easy with minimal non FPGA modifications.

We will probably create a CVS branch for your port, to be able to test it we need to compile a standard 7.1.x firmware disabling everything sensor or FPGA related and change the FPGA bitstream. --[[User:Polto|Alexandre.Poltorak]] 07:53, 19 February 2008 (CST)

You mean that it should be possible that the system can handle software Ogg Theora encoding for a non real-time application such as producing small video clips ? I'm aware that it depends on the output resolution, framerate and length of the clip but does a 1 min 1024x768 @ 25fps clip for example can be processed in a reasonable delay ? I'll discuss with Viewsurf's development team in order to obtain more precise specs concerning video output (in terms of length, resolution, framerate and encoding delay acceptable) but if you can give me an idea of what the software part can handle, I would consider spending more time in soft Theora transcoding instead of FPGA design. --[[User:JeremViewsurf|JeremViewsurf]] 03:37, 20 February 2008 (CST)

No, sorry i was not speaking of transcoding. It would take too much calculation power and is not possible on the camera's CPU. The Theora encoding should be done in FPGA. What i was speaking about is the software part.. I think you do not need a streamer for the first steps. You only need to generate a clip in the FPGA memory, and upload it to a FTP. --[[User:Polto|Alexandre.Poltorak]] 08:32, 20 February 2008 (CST)

----

Some questions concerning changes in the FPGA :
* Is it necessary to keep histogram and timestamp blocks in a design which supports Theora only ?
** I believe the camera will be rather crippled w/o those features--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
* Is it possible to keep channel 0, 1 and 3 design without changes in the memory controller ?
** Theora implementation used different (more advanced) memory controller that the JPEG, it was getting 95% efficiency at Theora data structure, so you need Theora memory controller. But if you mean by "Channel 0 design" the gamma tables and histograms - yes, they probably could be ported (with some changes, of course). As for channels 1 and 3 - similar are available in Theora 333 also--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
* The 353 design uses 2 DMA fifos between the compressor and the system interface instead of one in the 333 design. Is it possible to keep only one 333 DMA fifo in the final design ?
** Yes, of course - but this is so minor difference. The more important is that in Theora that FIFO could make the compressor wait if ETRAX DMA is not ready - at the beginning of the frame in theora there is a data "burst".--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
* In the 353 design, all signals and blocks I/O concerning 90° phase clock are commented. Is it possible to uncomment them in order to restore the clock ?
** Maybe yes, more likely no. 353 and 333 use different FPGAs.--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
* Motion compensation seems not to be implemented in the Theora compressor yet. Is it possible to add this feature later in the compressor block without major changes in the final design ?
** No, I'm afraid that is not possible - I believe we need faster FPGA for that and likely faster/wider memory.--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
--[[User:JeremViewsurf|JeremViewsurf]] 02:43, 25 February 2008 (CST)

----

I'm currently working on the FPGA control register and I have a question concerning the I2C pads controlled by the control register (via dcr[16:21]). In the 333 design there are 2 I2C "channels" : (sda0,scl0) and (sda1,scl1) and only one on the 353 design. Is it possible to keep a single i2c channel on the new design ? In other ways, what is the purpose of the i2c "channels" in each device ? --[[User:JeremViewsurf|JeremViewsurf]] 03:19, 3 March 2008 (CST)

The later 353 software also has 2 I2C channels, similar to 333. One channel is designed to communicate to the sensor (and goes through 30-pin flex cable), the other - to additional boards that sit on top of the 353, that I2C bus uses 2 bits (0,1) of the 12-bit GPIO of the 353 FPGA. It is currently used by multiple I2C peripherals on teh 10369 board (IDE bus configuration, clock/calendar, temperature sensor/fan control, EEPROM, USB hub configuration --[[User:Andrey.filippov|Andrey.filippov]] 12:27, 5 March 2008 (CST)

----

I tried to implement the new design according to the specs I proposed on this article. I instantiated the Theora compressor and the 8-channel memory controller in the place of the former jpeg compressor and memory controller and adapted registers and addresses (see article). The synthesis of this design with ISE is completed without error but I expect more issues with the place & route procedure. It would be great if I could share this work on a CVS to have some critics and some support, we had a discussion about that with Alexandre but I'm still waiting for an account. Before going farther, I'm trying to run the simulation with Icarus but I'm experiencing some issues with the compilation :

channel0.v:154: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+('sd1)
channel1.v:152: error: operand of concatenation has indefinite width: (ntile_x[3:0])+('sd1)
channel1.v:155: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+('sd1)

I would appreciate some support concerning how to test and debug the new design since this seems to be a tough issue to deal with.

When simulating Theora I used Silos III simulator on Windows, some work is needed to make it work with Icarus. First step - patch Xilinx unisim library, then - go through code (maybe it needs width for sd1?. The other problem that will come out - in Silos tasks were reenterable, each instance having it's own set of local variables (I used it when simulating CPU interrupts), in Icarus - they all share the same.--[[User:Andrey.filippov|Andrey.filippov]] 12:27, 5 March 2008 (CST)
--[[User:JeremViewsurf|JeremViewsurf]] 08:57, 5 March 2008 (CST)

I fixed the previous compilation error in Icarus, in channel0.v and channel1.v replace
channel0.v:154: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+1
channel1.v:152: error: operand of concatenation has indefinite width: (ntile_x[3:0])+1
channel1.v:155: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+1

with

channel0.v:154: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+11'h1
channel1.v:152: error: operand of concatenation has indefinite width: (ntile_x[3:0])+4'h1
channel1.v:155: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+11'h1

I can finally visualize some chronograms in gtkwave however I'm using the old 353 testbench... Time to understand how the testbench is structured and to think about a smarter one to test the new design. --[[User:JeremViewsurf|JeremViewsurf]] 03:13, 6 March 2008 (CST)

----

I'm working on the simulation of the 333 Theora design (x333t.tf) and it looks like there are three simulation modes for this design that can be switched with 'define : MASTERMODE, MASTERMODE1,SINGLE_ST. What is the difference between these modes and how does each work in summary ? --[[User:JeremViewsurf|JeremViewsurf]] 10:45, 10 March 2008 (CDT)

The source code is now available on the Elphel CVS : [http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ | http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/]. The synthesis of this code is OK but it still have to be tested. I split the testbench between the main simulation sequence and the different tasks. The x353_sim.sh script is up to date but the simulation itself (x353_1.tf) is inadequate to test the design (it is still the old MJPEG testbench). The testbench in the 6.3.9 firmware (333 Theora) seems to fit better but I still need to know how it works precisely in order to adapt it to the 353 design. --[[User:JeremViewsurf|JeremViewsurf]] 09:22, 11 March 2008 (CDT)

----

Some news concerning the simulation of Theora on the 353 :
* I instantiated the x353t module with the sensor and the sdram.
* I'm trying to go through the initialization sequence
* The global initialization works (with glbl.v)
* The DCM reset works (SDRAM clocks SDCLK_D and SDNCLK_D are working)
* I didn't check if the tables programmation is ok yet
* The sdram initialization sequence works :

Initialize SDRAM

>> 214455.000 ns >> cpu_wr(21, 00017fff)
At time 214556.000 ns PRE : Addr[10] = 1, Bank = 11

>> 214605.000 ns >> cpu_wr(21, 00002002)
At time 214708.000 ns EMR : Extended Mode Register
At time 214708.000 ns EMR : Enable DLL

>> 214755.000 ns >> cpu_wr(21, 00000163)
At time 214860.000 ns LMR : Load Mode Register
At time 214860.000 ns LMR : Burst Length = 8
At time 214860.000 ns LMR : CAS Latency = 2.5

>> 214905.000 ns >> cpu_wr(21, 00017fff)
At time 215004.000 ns PRE : Addr[10] = 1, Bank = 11

>> 215055.000 ns >> cpu_wr(21, 00008000)
At time 215156.000 ns AREF : Auto Refresh

>> 215205.000 ns >> cpu_wr(21, 00008000)
At time 215308.000 ns AREF : Auto Refresh
testbench353t.i_mt46v16m16fg: at time 215308.000 ns MEMORY: Power Up and Initialization Sequence is complete

>> 215355.000 ns >> cpu_wr(21, 00000063)
At time 215460.000 ns LMR : Load Mode Register
At time 215460.000 ns LMR : Burst Length = 8
At time 215460.000 ns LMR : CAS Latency = 2.5

Initialize SDRAM done

I committed the changes to the CVS. --[[User:JeremViewsurf|JeremViewsurf]] 05:20, 19 March 2008 (CDT)

I checked the table programming (quantization, huffman, etc), the procedure seems ok. I finally have data output on the SDA and SDD ports after having replace the sensorpix and sensortrig blocks in the 353 with those that were in the 333 Theora (with some modifications in the width of some signals). However, the timings seems completely different between the two sensors and I experience memory overflow during the simulation :

...
At time 1498748.000 ns WRITE: Bank = 3, Row = 0034, Col = 06d, Data = 0000
At time 1498748.000 ns ERROR: Memory overflow.
Write to Address 180d06d with Data 0000 will be lost.
You must increase the part_mem_bits parameter or define FULL_MEM.
At time 1498748.000 ns WRITE: Bank = 3, Col = 070
At time 1498752.000 ns WRITE: Bank = 3, Row = 0034, Col = 06e, Data = 0000
At time 1498752.000 ns ERROR: Memory overflow.
Write to Address 180d06e with Data 0000 will be lost.
You must increase the part_mem_bits parameter or define FULL_MEM.
...

--[[User:JeremViewsurf|JeremViewsurf]] 11:46, 26 March 2008 (CDT)

Have you tried to increase "part_mem_bits"? It's in ddr_parameters.v
--[[User:Oleg|Oleg]] 20:06, 26 March 2008 (CDT)

I defined FULL_MEM in ddr.v to be sure, there is no more memory overflow error. However is the simulation still representative of reality ? --[[User:JeremViewsurf|JeremViewsurf]] 03:32, 27 March 2008 (CDT)

----

I have a question concerning the sensor in both 333 and 353 design. In the 333 the sensor has a 10 bit output that goes directly to the sensorpix module (through sensorpads) to a 10 bit input. However In the 353, the sensor has a 12 bit output that goes to the sensorpads module and is treated to produce a 16 bit output that goes to the sensorpix module. What is the purpose of the extra bits in the 353 design ? Is it possible to extract a 10 bit output from the 353 sensorpad module to feed a 333 sensorpix block ? It looks like that the higher 10 bits of the ipxd[15:0] signal are different from the lower 6 bits (the latter can be forced to 0 with the cnven signal). Are these 10 bits similar to the 10 bits output of the 333 sensor ?

'''sensorpads353.v'''
...
ipxd_pre[ 5:0] <= cnven?6'b0:{ipxded[3:2],pxd14?ipxded[1:0]:2'h0,2'h0};
ipxd_pre[15:6] <= ipxded[15:6];
ipxd[15:0] <= ipxd_pre[15:0];
...

--[[User:JeremViewsurf|JeremViewsurf]] 03:37, 31 March 2008 (CDT)

The 5MPix sensor does have 12 bit output and all the bits are used during "gamma"-table conversion to 8 bits. Even more - the same FPGA code now supports 10347 boards (for Kodak KAI-11002/16000 CCD sensors) that produce 14-bit data.

After the data (10-12-14 bits) reaches the FPGA, it can go two ways - through the LUT (with linear interpolation) conversion to 8 bits and raw - 2 bytes/pixel format, where pixel data is MSB-aligned (actually bit 14 being the highest, bit 15 is left 0 to allow subtraction without overflow). I believe you should use that part (from the sensor interface to the SDRAM - including gamma tables and histograms) the same for Theora as it is now in 353 (for JPEG)--[[User:Andrey.filippov|Andrey.filippov]] 12:09, 31 March 2008 (CDT)

----

I restored the sensorpix353 and sensortrig353 in the Theora design and tested the data path from the sensor to the dma output. Looks like there is no data coming out of the mcontr channel 7 (after the token read buffer). Same issue with the 333 Theora simulation although the design is obviously correct. This might be a flaw in the testbench (?) as I used somehow the same for the two designs. Moreover I can't simulated over 2ms and I can't figure out why the simulations stops at that time. Maybe the second stage of the compressor processes data after 2 ms so it is never reached by the simulator (?)

[[Image:Datapath.jpg]]

--[[User:JeremViewsurf|JeremViewsurf]] 05:17, 7 April 2008 (CDT)

"simulation over 2ms" - $stop in line 639 of x353t.tf finishes the simulation. And there's one file is missing in cvs - linear1028rgb.dat - Jeremy, could you upload it.--[[User:Oleg|Oleg]] 11:44, 8 April 2008 (CDT)

The missing file is now on the cvs, let me know if something else is missing. If you want to check the set of signals in my simulation above, use pxdpath.sav in gtkwave. Before $stop in line 639 of x353t.tf there is now a 5ms delay (#5000000) to let the simulation run, it stops at 700µs... --[[User:JeremViewsurf|JeremViewsurf]] 02:24, 9 April 2008 (CDT)

I'm now trying with a 5 ms delay and without $stop after the delay, the simulation is currently at 2.3 ms and is still running ! --[[User:JeremViewsurf|JeremViewsurf]] 03:44, 9 April 2008 (CDT)

Talk:Porting Theora to 353 cameras

2008-04-09T08:43:30Z

JeremViewsurf:

Talk:Porting Theora to 353 cameras

2008-04-09T07:24:48Z

JeremViewsurf:

Ok, I started a new page on the Theora project in 353 cameras. I started with a global approach and a list of modules that need to be changed or replaced on the 353 model. Feel free to correct me or add suggestions as I'm not (yet...) an expert on Elphel cameras. I think the first step is to make an exhaustive list of the hardware blocks that need modifications and then detail what need to be done in each block. --[[User:JeremViewsurf|JeremViewsurf]] 03:48, 19 February 2008 (CST)

As I understand your first need is not a streaming but producing a small video clip to be uploaded via FTP. This can be done more easy with minimal non FPGA modifications.

We will probably create a CVS branch for your port, to be able to test it we need to compile a standard 7.1.x firmware disabling everything sensor or FPGA related and change the FPGA bitstream. --[[User:Polto|Alexandre.Poltorak]] 07:53, 19 February 2008 (CST)

You mean that it should be possible that the system can handle software Ogg Theora encoding for a non real-time application such as producing small video clips ? I'm aware that it depends on the output resolution, framerate and length of the clip but does a 1 min 1024x768 @ 25fps clip for example can be processed in a reasonable delay ? I'll discuss with Viewsurf's development team in order to obtain more precise specs concerning video output (in terms of length, resolution, framerate and encoding delay acceptable) but if you can give me an idea of what the software part can handle, I would consider spending more time in soft Theora transcoding instead of FPGA design. --[[User:JeremViewsurf|JeremViewsurf]] 03:37, 20 February 2008 (CST)

No, sorry i was not speaking of transcoding. It would take too much calculation power and is not possible on the camera's CPU. The Theora encoding should be done in FPGA. What i was speaking about is the software part.. I think you do not need a streamer for the first steps. You only need to generate a clip in the FPGA memory, and upload it to a FTP. --[[User:Polto|Alexandre.Poltorak]] 08:32, 20 February 2008 (CST)

----

Some questions concerning changes in the FPGA :
* Is it necessary to keep histogram and timestamp blocks in a design which supports Theora only ?
** I believe the camera will be rather crippled w/o those features--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
* Is it possible to keep channel 0, 1 and 3 design without changes in the memory controller ?
** Theora implementation used different (more advanced) memory controller that the JPEG, it was getting 95% efficiency at Theora data structure, so you need Theora memory controller. But if you mean by "Channel 0 design" the gamma tables and histograms - yes, they probably could be ported (with some changes, of course). As for channels 1 and 3 - similar are available in Theora 333 also--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
* The 353 design uses 2 DMA fifos between the compressor and the system interface instead of one in the 333 design. Is it possible to keep only one 333 DMA fifo in the final design ?
** Yes, of course - but this is so minor difference. The more important is that in Theora that FIFO could make the compressor wait if ETRAX DMA is not ready - at the beginning of the frame in theora there is a data "burst".--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
* In the 353 design, all signals and blocks I/O concerning 90° phase clock are commented. Is it possible to uncomment them in order to restore the clock ?
** Maybe yes, more likely no. 353 and 333 use different FPGAs.--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
* Motion compensation seems not to be implemented in the Theora compressor yet. Is it possible to add this feature later in the compressor block without major changes in the final design ?
** No, I'm afraid that is not possible - I believe we need faster FPGA for that and likely faster/wider memory.--[[User:Andrey.filippov|Andrey.filippov]] 10:24, 25 February 2008 (CST)
--[[User:JeremViewsurf|JeremViewsurf]] 02:43, 25 February 2008 (CST)

----

I'm currently working on the FPGA control register and I have a question concerning the I2C pads controlled by the control register (via dcr[16:21]). In the 333 design there are 2 I2C "channels" : (sda0,scl0) and (sda1,scl1) and only one on the 353 design. Is it possible to keep a single i2c channel on the new design ? In other ways, what is the purpose of the i2c "channels" in each device ? --[[User:JeremViewsurf|JeremViewsurf]] 03:19, 3 March 2008 (CST)

The later 353 software also has 2 I2C channels, similar to 333. One channel is designed to communicate to the sensor (and goes through 30-pin flex cable), the other - to additional boards that sit on top of the 353, that I2C bus uses 2 bits (0,1) of the 12-bit GPIO of the 353 FPGA. It is currently used by multiple I2C peripherals on teh 10369 board (IDE bus configuration, clock/calendar, temperature sensor/fan control, EEPROM, USB hub configuration --[[User:Andrey.filippov|Andrey.filippov]] 12:27, 5 March 2008 (CST)

----

I tried to implement the new design according to the specs I proposed on this article. I instantiated the Theora compressor and the 8-channel memory controller in the place of the former jpeg compressor and memory controller and adapted registers and addresses (see article). The synthesis of this design with ISE is completed without error but I expect more issues with the place & route procedure. It would be great if I could share this work on a CVS to have some critics and some support, we had a discussion about that with Alexandre but I'm still waiting for an account. Before going farther, I'm trying to run the simulation with Icarus but I'm experiencing some issues with the compilation :

channel0.v:154: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+('sd1)
channel1.v:152: error: operand of concatenation has indefinite width: (ntile_x[3:0])+('sd1)
channel1.v:155: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+('sd1)

I would appreciate some support concerning how to test and debug the new design since this seems to be a tough issue to deal with.

When simulating Theora I used Silos III simulator on Windows, some work is needed to make it work with Icarus. First step - patch Xilinx unisim library, then - go through code (maybe it needs width for sd1?. The other problem that will come out - in Silos tasks were reenterable, each instance having it's own set of local variables (I used it when simulating CPU interrupts), in Icarus - they all share the same.--[[User:Andrey.filippov|Andrey.filippov]] 12:27, 5 March 2008 (CST)
--[[User:JeremViewsurf|JeremViewsurf]] 08:57, 5 March 2008 (CST)

I fixed the previous compilation error in Icarus, in channel0.v and channel1.v replace
channel0.v:154: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+1
channel1.v:152: error: operand of concatenation has indefinite width: (ntile_x[3:0])+1
channel1.v:155: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+1

with

channel0.v:154: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+11'h1
channel1.v:152: error: operand of concatenation has indefinite width: (ntile_x[3:0])+4'h1
channel1.v:155: error: operand of concatenation has indefinite width: ({1'b0, ntile_y[9:0]})+11'h1

I can finally visualize some chronograms in gtkwave however I'm using the old 353 testbench... Time to understand how the testbench is structured and to think about a smarter one to test the new design. --[[User:JeremViewsurf|JeremViewsurf]] 03:13, 6 March 2008 (CST)

----

I'm working on the simulation of the 333 Theora design (x333t.tf) and it looks like there are three simulation modes for this design that can be switched with 'define : MASTERMODE, MASTERMODE1,SINGLE_ST. What is the difference between these modes and how does each work in summary ? --[[User:JeremViewsurf|JeremViewsurf]] 10:45, 10 March 2008 (CDT)

The source code is now available on the Elphel CVS : [http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ | http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/]. The synthesis of this code is OK but it still have to be tested. I split the testbench between the main simulation sequence and the different tasks. The x353_sim.sh script is up to date but the simulation itself (x353_1.tf) is inadequate to test the design (it is still the old MJPEG testbench). The testbench in the 6.3.9 firmware (333 Theora) seems to fit better but I still need to know how it works precisely in order to adapt it to the 353 design. --[[User:JeremViewsurf|JeremViewsurf]] 09:22, 11 March 2008 (CDT)

----

Some news concerning the simulation of Theora on the 353 :
* I instantiated the x353t module with the sensor and the sdram.
* I'm trying to go through the initialization sequence
* The global initialization works (with glbl.v)
* The DCM reset works (SDRAM clocks SDCLK_D and SDNCLK_D are working)
* I didn't check if the tables programmation is ok yet
* The sdram initialization sequence works :

Initialize SDRAM

>> 214455.000 ns >> cpu_wr(21, 00017fff)
At time 214556.000 ns PRE : Addr[10] = 1, Bank = 11

>> 214605.000 ns >> cpu_wr(21, 00002002)
At time 214708.000 ns EMR : Extended Mode Register
At time 214708.000 ns EMR : Enable DLL

>> 214755.000 ns >> cpu_wr(21, 00000163)
At time 214860.000 ns LMR : Load Mode Register
At time 214860.000 ns LMR : Burst Length = 8
At time 214860.000 ns LMR : CAS Latency = 2.5

>> 214905.000 ns >> cpu_wr(21, 00017fff)
At time 215004.000 ns PRE : Addr[10] = 1, Bank = 11

>> 215055.000 ns >> cpu_wr(21, 00008000)
At time 215156.000 ns AREF : Auto Refresh

>> 215205.000 ns >> cpu_wr(21, 00008000)
At time 215308.000 ns AREF : Auto Refresh
testbench353t.i_mt46v16m16fg: at time 215308.000 ns MEMORY: Power Up and Initialization Sequence is complete

>> 215355.000 ns >> cpu_wr(21, 00000063)
At time 215460.000 ns LMR : Load Mode Register
At time 215460.000 ns LMR : Burst Length = 8
At time 215460.000 ns LMR : CAS Latency = 2.5

Initialize SDRAM done

I committed the changes to the CVS. --[[User:JeremViewsurf|JeremViewsurf]] 05:20, 19 March 2008 (CDT)

I checked the table programming (quantization, huffman, etc), the procedure seems ok. I finally have data output on the SDA and SDD ports after having replace the sensorpix and sensortrig blocks in the 353 with those that were in the 333 Theora (with some modifications in the width of some signals). However, the timings seems completely different between the two sensors and I experience memory overflow during the simulation :

...
At time 1498748.000 ns WRITE: Bank = 3, Row = 0034, Col = 06d, Data = 0000
At time 1498748.000 ns ERROR: Memory overflow.
Write to Address 180d06d with Data 0000 will be lost.
You must increase the part_mem_bits parameter or define FULL_MEM.
At time 1498748.000 ns WRITE: Bank = 3, Col = 070
At time 1498752.000 ns WRITE: Bank = 3, Row = 0034, Col = 06e, Data = 0000
At time 1498752.000 ns ERROR: Memory overflow.
Write to Address 180d06e with Data 0000 will be lost.
You must increase the part_mem_bits parameter or define FULL_MEM.
...

--[[User:JeremViewsurf|JeremViewsurf]] 11:46, 26 March 2008 (CDT)

Have you tried to increase "part_mem_bits"? It's in ddr_parameters.v
--[[User:Oleg|Oleg]] 20:06, 26 March 2008 (CDT)

I defined FULL_MEM in ddr.v to be sure, there is no more memory overflow error. However is the simulation still representative of reality ? --[[User:JeremViewsurf|JeremViewsurf]] 03:32, 27 March 2008 (CDT)

----

I have a question concerning the sensor in both 333 and 353 design. In the 333 the sensor has a 10 bit output that goes directly to the sensorpix module (through sensorpads) to a 10 bit input. However In the 353, the sensor has a 12 bit output that goes to the sensorpads module and is treated to produce a 16 bit output that goes to the sensorpix module. What is the purpose of the extra bits in the 353 design ? Is it possible to extract a 10 bit output from the 353 sensorpad module to feed a 333 sensorpix block ? It looks like that the higher 10 bits of the ipxd[15:0] signal are different from the lower 6 bits (the latter can be forced to 0 with the cnven signal). Are these 10 bits similar to the 10 bits output of the 333 sensor ?

'''sensorpads353.v'''
...
ipxd_pre[ 5:0] <= cnven?6'b0:{ipxded[3:2],pxd14?ipxded[1:0]:2'h0,2'h0};
ipxd_pre[15:6] <= ipxded[15:6];
ipxd[15:0] <= ipxd_pre[15:0];
...

--[[User:JeremViewsurf|JeremViewsurf]] 03:37, 31 March 2008 (CDT)

The 5MPix sensor does have 12 bit output and all the bits are used during "gamma"-table conversion to 8 bits. Even more - the same FPGA code now supports 10347 boards (for Kodak KAI-11002/16000 CCD sensors) that produce 14-bit data.

After the data (10-12-14 bits) reaches the FPGA, it can go two ways - through the LUT (with linear interpolation) conversion to 8 bits and raw - 2 bytes/pixel format, where pixel data is MSB-aligned (actually bit 14 being the highest, bit 15 is left 0 to allow subtraction without overflow). I believe you should use that part (from the sensor interface to the SDRAM - including gamma tables and histograms) the same for Theora as it is now in 353 (for JPEG)--[[User:Andrey.filippov|Andrey.filippov]] 12:09, 31 March 2008 (CDT)

----

I restored the sensorpix353 and sensortrig353 in the Theora design and tested the data path from the sensor to the dma output. Looks like there is no data coming out of the mcontr channel 7 (after the token read buffer). Same issue with the 333 Theora simulation although the design is obviously correct. This might be a flaw in the testbench (?) as I used somehow the same for the two designs. Moreover I can't simulated over 2ms and I can't figure out why the simulations stops at that time. Maybe the second stage of the compressor processes data after 2 ms so it is never reached by the simulator (?)

[[Image:Datapath.jpg]]

--[[User:JeremViewsurf|JeremViewsurf]] 05:17, 7 April 2008 (CDT)

"simulation over 2ms" - $stop in line 639 of x353t.tf finishes the simulation. And there's one file is missing in cvs - linear1028rgb.dat - Jeremy, could you upload it.--[[User:Oleg|Oleg]] 11:44, 8 April 2008 (CDT)

The missing file is now on the cvs, let me know if something else is missing. If you want to check the set of signals in my simulation above, use pxdpath.sav in gtkwave. Before $stop in line 639 of x353t.tf there is a 5ms delay (#5000000) to let the simulation run, I don't understand why it stops at 2ms... --[[User:JeremViewsurf|JeremViewsurf]] 02:24, 9 April 2008 (CDT)

Talk:Porting Theora to 353 cameras

2008-04-07T12:35:58Z

JeremViewsurf:

Talk:Porting Theora to 353 cameras

2008-04-07T10:17:30Z

JeremViewsurf:

File:Datapath.jpg

2008-04-07T10:16:08Z

JeremViewsurf: Theora on 353 simulation. Overview of the data path from the sensor to the dma output. No more data after channel 7 of the memory controller.

Theora on 353 simulation. Overview of the data path from the sensor to the dma output. No more data after channel 7 of the memory controller.

Porting Theora to 353 cameras

2008-04-02T14:37:36Z

JeremViewsurf: /* System interface */

Elphel model 333 cameras were able to encode and stream Ogg Theora with 6.3.9 firmware. However, this model is no longer produced by Elphel. The goal of this project is to use the full potential of 353 cameras (larger FPGA, faster CPU) in order to port the Ogg Theora feature on the new hardware. First, the camera should be able to upload small Theora clips via FTP.

Different solutions are possible as previously mentioned in the [[Theora]] page :
* Instantiate both the Theora compressor and the MJPEG compressor in the FPGA since the new Spartan 3E seems to be large enough to handle the two features.
* Replace the existing MJPEG compressor with the Theora compressor and implement software Theora to JPEG conversion if JPEG is needed.
* Replace the existing MJPEG compressor in the 353 camera with the Theora compressor and keep two configuration files on the camera filesystem (one for Theora the other for MJPEG). FPGA code could be changed at run-time according to the needs.

Dealing with the last solution seems to be a good start for this project as the other features mentioned can be added later. In all cases, both FPGA code and software code will need to be adapted.

The source code of this project is available at [http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/]
== Hardware updates ==

=== Compressor ===
[[Image:Schematic.png|frame|[[Media:Schematic.png|333 Theora design with the 2 stage compressor and the 8-channel memory controller]]]]
Replace the MJPEG compressor in the 353 with the 333 Theora compressor ([http://elphel.cvs.sourceforge.net/elphel/camera333/fpga/x333 333 Theora FPGA code]). Maybe some adaptations need to be done within the Theora compressor itself. However, assuming that the compressor worked in 333 cameras a simple instantiation should suffice.

=== Memory controller ===
Replace the 4-channel memory controller with an 8 channel memory interface as in the 333 model in order to handle Theora specific data.

{|border="1" cellpadding="2"
! Channel !! 333 Theora !! 353
|-
| '''0''' || 8/16 bit data from sensor to SDRAM || Data from the sensor (it can be combined with FPN correction data) to the SDRAM in either 8-bit mode or 16-bit
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module || Reads FPN data from SDRAM (8bit - subtract, 8 bit - scale) and feeds it to FPGA for FPN correction of the data on the way from sensor to SDRAM (through channel 0)
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor || Provides data to JPEG encoder in 16x16x8bit MCUs. It can also provide data directly to CPU through DMA bypassing any compression
|-
| '''3''' || PIO read/write of SDRAM data || Provides bidirectional access from CPU through 8x32 bit window.
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM ||
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM ||
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63] ||
|-
| '''7''' || reading 12-bit pre-tokens from SDRAM in indexed coded order ||
|-
|}

=== Sensor interface ===
''sensorpix'' block must be adapted in order to provide a coherent interface between the memory controller and the sensor (channels 0 and 1)

=== System Interface ===
Adapt the system interface to assure communication between FPGA and its environment.

A feature of the system interface is to establish communication between the system CPU and the different blocks within the FPGA (compressor, memory controller etc). This is done by selecting a block with the address bus ''a[12:0]'' connected to the internal address bus ''ial[7:0]'':

'''x353.v'''
always @ (posedge cwr) begin
a0[7:0]<=ial[7:0]; // may want to change to just ia if ia will be late enough;
wnr0 <= ~irnw;
da_ctl0 <= (ial[7:0]==8'h00); // 0x00 WE to control 32-bit register (1 loc)
da_dmamode0 <= (ial[7:0]==8'h01); // 0x01 select writing to dma_cntr/dma_raw (1 loc)
da_sensormode0 <= (ial[7:0]==8'h02); // 0x02 select writing to sensorpix (1 loc)
...
da_compressor0 <= (ial[7:1]==7'h06); // 0x0c..0x0d - will be farther decoded in the compressor module
...

Since memory controller and compressor are to be replaced these addresses have to be adapted.

''353 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x09''' || da_saturation0 || write color saturation values
|-
| '''0x0a''' || da_framesync_dly0 || write frame sync interrupt delay (in scan lines)
|-
| '''0x0c..0x0d''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x0e''' || da_table_a0 || write tables address
|-
| '''0x0f''' || twr0 || write tables data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts0 || interrupt control
|-
| '''0x20..0x2f''' || da_dswe0 || select reading/writing to mcontr (16 locations)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist0 || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc0 || real time clock
|-
| '''0x48''' || da_timestamp0 || write timestamp mode
|-
| '''0x74''' || da_xjtag0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync0 || control of external sync module 0x78 - 0x7b
|-
|}

''333 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or aftre trigger)
|-
| '''0x06''' || da_interrupts0 || interrupt mask
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x10''' || da_debug || write 0x10 any - load debug shift, read (through cs4) -shift
|-
| '''0x20..0x27''' || da_mcontr0 || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table0 || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
|}

Addresses 0x01,2,3,4,5,6,8 and 0x30 can be kept in the 353 system interface. The interrupt mask address 0x06 in the 333 sys interface is no longer used (353 uses interrupt vectors). The Theora compressor and the new memory controller addresses have to be mapped again in the new design (addresses 0x0c..0x0d and 0x20 to 0x2f in the 353 sys interface).

=== Interrupts ===
Adapt the Theora compressor interrupts to the 353 interrupt vector .

The 353 interrupt vector can handle up to 16 different irq. However, only irq 0 to 7 are used :
'''x353.v'''

assign irq_in= {8'b0, // extra
compressor_done_compress, // 7 - will go high after all data is sent out (reset by compressor)
compressor_done_input, // 6 - will go high after EOT and persist until DCT is enabled (reset by compressor)
dcc_rdy, // 5 - obsolete in 333 - channel3 has 128 more dc coefficients (or some if the compression is finished)
compressor_eot, // 4 - compressor read in the last MCU (predictable time to end of transfer)
sr_sensortrig[2], // 3 - (sync to pclk) - level, reset by writing to sensor triggering command register
xfer_over_irq, // 2 - (sync to pclk) - frame acquisition over
trig_irq, // 1 - (sync to pclk) - external trigger
vacts}; // 0 - (sync to pclk) - frame sync

353 MJPEG compressor triggers irqs 4, 6 and 7. 333 Theora compressor is the source of two irqs :
'''compressor_all.v'''

done, // single-cycle pulse when the compressed frame is sent out (IRQ source).
reset_compress, // reset compressor done interrupt (writing any compressor command)

Adaptation should consist of assigning Theora compressor irq sources to vectors 6 and 7 for example if the MJPEG compressor is to be replaced.

=== DMA FIFOs ===
353 design uses 2 DMA FIFOs between the compressor and the system interface instead of one for the 333 Theora compressor. The two DMA FIFOs have also slight differences between the two design. Maybe a single 333 FIFO should be kept for the final design (?)

=== FPGA -> CPU data out MUX ===
The purpose of this MUX is to route data out from the different FPGA blocks to the system interface and then to the data bus to the CPU. The selection is made with the internal address bus ''ia''.
_
--| \
--| |
--| |
--| |--- iod[31:0] -> to system interface
--| |
--| |
|_/
from system interface -> ia[7:0]__|

'' 333 MUX ''
{|border="1" cellpadding="2"
! Adress range !! ia(5) !! ia(4) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''1''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''1''' || '''0''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''1''' || '''1''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0.. (even)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''0''' || dma_d0[31:0] || DMA 0 data
|-
| '''0x0.. (odd)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''1''' || dma_d1[31:0] || DMA 1 data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''X''' || '''X''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''X''' || '''X''' || dsdo[31:0] || Data out from descriptor memory
|-
| '''0x3..''' || '''0''' || '''1''' || '''1''' || '''X''' || '''X''' || bdo[31:0] || 32-bit data from SDRAM channel3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''X''' || '''0''' || '''X''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''X''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''X''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''X''' || '''X''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''X''' || '''X''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

'' 333 MUX ''
{|border="1" cellpadding="2"
! Address || ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || {24'b0,irqr[7:0]} || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(2) !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''0''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''0''' || '''1''' || '''1''' || MODELREV || Model revision
|-
| '''0x14''' || '''1''' || '''X''' || '''0''' || {8'h0,imgptr[23:0]} || Image pointer in 32-byte chunks
|-
| '''0x15''' || '''1''' || '''X''' || '''1''' || hifreq[31:0] || Accumulated high-freq components
|-
|}

'' 333 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock0
|-
| '''2''' || sr_sda1 || I2C
|-
| '''3''' || sr_scl1 || I2C clock1
|-
| '''4..12''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''17''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''18''' || 1'b0 || 0x0
|-
| '''19''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''20''' || itrig || TRIG input
|-
| '''21..22''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)
, 01 - clock is too late
, 10 - clock is too early
, 11 - OK (some measurements show too late, some - too early)
|-
| '''23''' || dcm_done ||
|-
| '''24''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''25''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''26''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''27''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''28''' || tok_frame_num_wr || Odd/even frame of tokens written
|-
| '''29''' || 1'b0 || 0x0
|-
| '''30''' || debug_out || Debug shift register output
|-
| '''31''' || 'b0 || 0x0
|-
|}

'' 353 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2''' || sr_ch0rdy || Ready to write next page (channel 0) SENSOR->SDRAM
|-
| '''3''' || sr_ch1rdy || Ready to read next page (channel 1) SDRAM->FPN(SENSOR)
|-
| '''4''' || sr_ch2rdy || Ready to read next page (channel 2) SDRAM->DMA
|-
| '''5''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''6''' || sr_wrempty || CPU write buffer empty (valid only in write mode). May reprogram channel3.
|-
| '''7..10''' || sr_nextFrame[3:0] || (level) generated before actual block is filled - needed to be combined with the pulse from buffer control
|-
| '''11..13''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''14''' || dcc_rdy || 128 of DC components from JPEG encoder are available (same as interrupt)
|-
| '''15''' || compressor_done_input || will go high after EOT and persist until DCT is enabled
|-
| '''16''' || compressor_done_compress || will go high after all data is sent out
|-
| '''17''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''19..18''' || dcm_err[1:0] || SDRAM DCM phase error
|-
| '''20''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''21''' || dcm_locked || SDRAM DCM overflow
|-
| '''22''' || dcm_status[0] || SDRAM DCM overflow
|-
| '''24..23''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''25''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''26''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''27''' || sens_dcm_status[0] || Sensor DCM overflow
|-
| '''28''' || clockios_locked || dcm locked
|-
| '''29..30''' || clockios_status[1:0] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''31''' || 1'b0 || 0x0
|-
|}

=== Control register ===
The dcr[31:0] bus is used to control the different blocks according to the control register values. The control register can be directly written by the CPU at the address 0x00.

''333 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0..2''' || Not used ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || iobuf || EXPS (output pin)
|-
| '''12''' || iobuf || EXPS (output pin)
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || i2cpads || scl1 out
|-
| '''20''' || i2cpads || scl1 enable
|-
| '''21''' || i2cpads || sda1 out
|-
| '''22''' || i2cpads || sda1 enable
|-
| '''23''' || Not used ||
|-
| '''24..27''' || clock_pclk || pclk source
|-
| '''28..30''' || Not used ||
|-
| '''31''' || clock_pclk || clk enable
|-
|}

''353 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0''' || Not used ||
|-
| '''1..2''' || compressor, sensorpix, histogram ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || sensorpads || sensor trigger
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || sensorpads || dclkmode
|-
| '''20''' || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || Not used ||
|-
| '''24..25''' || BUFGMUX || pclk source
|-
| '''28..30''' || compressor ||
|-
| '''31''' || clock_pclk ||
|-
|}

=== Others ===
* Looks like Theora compressor requires 90° phase clock that was abandoned in the 353 design.
Using different phases reduces AC component of the current through the power/ground lines of the FPGA by spreading register transitions. Theora has larger core so it may help spreading phases.--[[User:Andrey.filippov|Andrey.filippov]] 13:45, 25 February 2008 (CST)
* ...?

== Software updates ==

* Adapt FPGA definitions ([http://elphel.cvs.sourceforge.net/elphel/elphel353/elphel353/os/linux-2.6-tag--devboard-R2_01-1/arch/cris/arch-v32/drivers/elphel/x353.h?revision=1.8&view=markup&sortdir=down x353.h]) and most likely some other FPGA drivers.
* ...?

These lists of update are obviously incomplete. They need to be more detailed in order to make an exhaustive list of the changes that have to be done.

== 353 Theora new design ==
=== Compressor ===

=== Sensorpix ===

Some changes have to be done in this block to interface the sensor and the memory controller (ch0 and 1).

=== Memory controller ===

{|border="1" cellpadding="2"
! Channel !! Description
|-
| '''0''' || 8/16 bit data from sensor to SDRAM
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor
|-
| '''3''' || PIO read/write of SDRAM data
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63]
|-
| '''7''' || Reading 12-bit pre-tokens from SDRAM in indexed coded order
|-
|}

=== System interface ===

{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm || tune SDRAM clock phase
|-
| '''0x0a''' || da_framesync_dly || write frame sync interrupt delay (in scan lines)
|-
| '''0x0e''' || da_table_a0 || write gamma table address
|-
| '''0x0f''' || twr0 || write gamma table data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts || interrupt control
|-
| '''0x20..0x27''' || da_mcontr || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc || real time clock
|-
| '''0x48''' || da_timestamp || write timestamp mode
|-
| '''0x74''' || da_xjta0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync || control of external sync module 0x78 - 0x7b
|-
|}

=== Interrupts ===

{|border="1" cellpadding="2"
! irq_in !! Signal !! Comments
|-
| '''15..8''' || GND || Extra
|-
| '''7''' || compressor_done_compress || single-cycle pulse when the compressed frame is sent out
|-
| '''6''' || compressor_reset_compress || reset compressor done interrupt (writing any compressor command)
|-
| '''5''' || GND || dcc_rdy was tied to GND in the 333 design
|-
| '''4''' || GND || eot irq was tied to GND in the 333 design
|-
| '''3''' || sr_sensortrig[2] || (sync to pclk) - level, reset by writing to sensor triggering command register
|-
| '''2''' || xfer_over_irq || (sync to pclk) - frame acquisition over
|-
| '''1''' || trig_irq || (sync to pclk) - external trigger
|-
| '''0''' || vacts || (sync to pclk) - frame sync
|-
|}

=== DMA FIFOs ===
A single DMA FIFO from the 333 design will be instanciated.

=== FPGA -> CPU data out MUX ===

{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || '''0''' || '''x''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''x''' || '''x''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''x''' || '''0''' || '''x''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''x''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''x''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''x''' || '''x''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''x''' || '''x''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

{|border="1" cellpadding="2"
! Address !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' Status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C data
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2..10''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''11''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''12''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''17..18''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)

, 01 - clock is too late , 10 - clock is too early , 11 - OK (some measurements show too late, some - too early)
|-
| '''19''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''20''' || dcm_locked || SDRAM DCM overflow
|-
| '''21..22''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''23''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''24''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''25''' || clockios_locked || dcm locked
|-
| '''26''' || clockios_status[1] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''27''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''28''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''29''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''30''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''31''' || took_frame_num_wr || Odd/even frame of tokens written
|-
|}

=== Control register ===
{|border="1" cellpadding="2"
! bit # !! Signal || Destination block !! Comments
|-
| '''0''' || || Not used ||
|-
| '''1..2''' || cb_bayer_phase || compressor, sensorpix, histogram ||
|-
| '''3''' || || sensorpads || Inverts idclk phase (Not used)
|-
| '''4''' || cb_fillfactory || sensorpads || fillfactory sensor mode
|-
| '''5''' || cb_dlyhact || sensorpads || delay hact pulse by 1
|-
| '''6''' || cb_zoran || sensorpads || ''cb_zoran''
|-
| '''7''' || cb_skipline || sensorpads || skip first scan line from the sensor
|-
| '''8''' || cb_xt_pol || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || iarst || sensorpads || ''iarst''
|-
| '''10''' || iaro || sensorpads || ''iaro''
|-
| '''11''' || cb_encnvclk || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || cb_sensor_trigger || sensorpads || sensor trigger
|-
| '''13''' || imrst || sensorpads || ''imrst''
|-
| '''14''' || cb_scl0_o || iobuf || XRST (output pin)
|-
| '''15''' || cb_scl0_o || i2cpads || scl0 out
|-
| '''16''' || cb_scl0_en || i2cpads || scl0 enable
|-
| '''17''' || cb_sda0_o || i2cpads || sda0 out
|-
| '''18''' || cb_sda0_en || i2cpads || sda0 enable
|-
| '''19''' || cb_dclkmode || sensorpads || dclkmode
|-
| '''20''' || cb_pxd14 || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || cb_latehact || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || || Not used ||
|-
| '''24..25''' || cb_pclksrc || BUFGMUX || pclk source
|-
| '''28..30''' || || Not used ||
|-
| '''31''' || || Not used ||
|-
|}

=== Others ===

== See also ==

*[http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ 353 Theora CVS]
*[[Theora]]
*[[FPGA_Development_in_Elphel_cameras|FPGA Development in Elphel cameras]]
*[[Design Ideas|FPGA Theora Encoder for Videoconferencing]]
*[[10353]]

Porting Theora to 353 cameras

2008-04-02T14:37:18Z

JeremViewsurf: /* System interface */

Elphel model 333 cameras were able to encode and stream Ogg Theora with 6.3.9 firmware. However, this model is no longer produced by Elphel. The goal of this project is to use the full potential of 353 cameras (larger FPGA, faster CPU) in order to port the Ogg Theora feature on the new hardware. First, the camera should be able to upload small Theora clips via FTP.

Different solutions are possible as previously mentioned in the [[Theora]] page :
* Instantiate both the Theora compressor and the MJPEG compressor in the FPGA since the new Spartan 3E seems to be large enough to handle the two features.
* Replace the existing MJPEG compressor with the Theora compressor and implement software Theora to JPEG conversion if JPEG is needed.
* Replace the existing MJPEG compressor in the 353 camera with the Theora compressor and keep two configuration files on the camera filesystem (one for Theora the other for MJPEG). FPGA code could be changed at run-time according to the needs.

Dealing with the last solution seems to be a good start for this project as the other features mentioned can be added later. In all cases, both FPGA code and software code will need to be adapted.

The source code of this project is available at [http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/]
== Hardware updates ==

=== Compressor ===
[[Image:Schematic.png|frame|[[Media:Schematic.png|333 Theora design with the 2 stage compressor and the 8-channel memory controller]]]]
Replace the MJPEG compressor in the 353 with the 333 Theora compressor ([http://elphel.cvs.sourceforge.net/elphel/camera333/fpga/x333 333 Theora FPGA code]). Maybe some adaptations need to be done within the Theora compressor itself. However, assuming that the compressor worked in 333 cameras a simple instantiation should suffice.

=== Memory controller ===
Replace the 4-channel memory controller with an 8 channel memory interface as in the 333 model in order to handle Theora specific data.

{|border="1" cellpadding="2"
! Channel !! 333 Theora !! 353
|-
| '''0''' || 8/16 bit data from sensor to SDRAM || Data from the sensor (it can be combined with FPN correction data) to the SDRAM in either 8-bit mode or 16-bit
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module || Reads FPN data from SDRAM (8bit - subtract, 8 bit - scale) and feeds it to FPGA for FPN correction of the data on the way from sensor to SDRAM (through channel 0)
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor || Provides data to JPEG encoder in 16x16x8bit MCUs. It can also provide data directly to CPU through DMA bypassing any compression
|-
| '''3''' || PIO read/write of SDRAM data || Provides bidirectional access from CPU through 8x32 bit window.
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM ||
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM ||
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63] ||
|-
| '''7''' || reading 12-bit pre-tokens from SDRAM in indexed coded order ||
|-
|}

=== Sensor interface ===
''sensorpix'' block must be adapted in order to provide a coherent interface between the memory controller and the sensor (channels 0 and 1)

=== System Interface ===
Adapt the system interface to assure communication between FPGA and its environment.

A feature of the system interface is to establish communication between the system CPU and the different blocks within the FPGA (compressor, memory controller etc). This is done by selecting a block with the address bus ''a[12:0]'' connected to the internal address bus ''ial[7:0]'':

'''x353.v'''
always @ (posedge cwr) begin
a0[7:0]<=ial[7:0]; // may want to change to just ia if ia will be late enough;
wnr0 <= ~irnw;
da_ctl0 <= (ial[7:0]==8'h00); // 0x00 WE to control 32-bit register (1 loc)
da_dmamode0 <= (ial[7:0]==8'h01); // 0x01 select writing to dma_cntr/dma_raw (1 loc)
da_sensormode0 <= (ial[7:0]==8'h02); // 0x02 select writing to sensorpix (1 loc)
...
da_compressor0 <= (ial[7:1]==7'h06); // 0x0c..0x0d - will be farther decoded in the compressor module
...

Since memory controller and compressor are to be replaced these addresses have to be adapted.

''353 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x09''' || da_saturation0 || write color saturation values
|-
| '''0x0a''' || da_framesync_dly0 || write frame sync interrupt delay (in scan lines)
|-
| '''0x0c..0x0d''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x0e''' || da_table_a0 || write tables address
|-
| '''0x0f''' || twr0 || write tables data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts0 || interrupt control
|-
| '''0x20..0x2f''' || da_dswe0 || select reading/writing to mcontr (16 locations)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist0 || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc0 || real time clock
|-
| '''0x48''' || da_timestamp0 || write timestamp mode
|-
| '''0x74''' || da_xjtag0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync0 || control of external sync module 0x78 - 0x7b
|-
|}

''333 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or aftre trigger)
|-
| '''0x06''' || da_interrupts0 || interrupt mask
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x10''' || da_debug || write 0x10 any - load debug shift, read (through cs4) -shift
|-
| '''0x20..0x27''' || da_mcontr0 || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table0 || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
|}

Addresses 0x01,2,3,4,5,6,8 and 0x30 can be kept in the 353 system interface. The interrupt mask address 0x06 in the 333 sys interface is no longer used (353 uses interrupt vectors). The Theora compressor and the new memory controller addresses have to be mapped again in the new design (addresses 0x0c..0x0d and 0x20 to 0x2f in the 353 sys interface).

=== Interrupts ===
Adapt the Theora compressor interrupts to the 353 interrupt vector .

The 353 interrupt vector can handle up to 16 different irq. However, only irq 0 to 7 are used :
'''x353.v'''

assign irq_in= {8'b0, // extra
compressor_done_compress, // 7 - will go high after all data is sent out (reset by compressor)
compressor_done_input, // 6 - will go high after EOT and persist until DCT is enabled (reset by compressor)
dcc_rdy, // 5 - obsolete in 333 - channel3 has 128 more dc coefficients (or some if the compression is finished)
compressor_eot, // 4 - compressor read in the last MCU (predictable time to end of transfer)
sr_sensortrig[2], // 3 - (sync to pclk) - level, reset by writing to sensor triggering command register
xfer_over_irq, // 2 - (sync to pclk) - frame acquisition over
trig_irq, // 1 - (sync to pclk) - external trigger
vacts}; // 0 - (sync to pclk) - frame sync

353 MJPEG compressor triggers irqs 4, 6 and 7. 333 Theora compressor is the source of two irqs :
'''compressor_all.v'''

done, // single-cycle pulse when the compressed frame is sent out (IRQ source).
reset_compress, // reset compressor done interrupt (writing any compressor command)

Adaptation should consist of assigning Theora compressor irq sources to vectors 6 and 7 for example if the MJPEG compressor is to be replaced.

=== DMA FIFOs ===
353 design uses 2 DMA FIFOs between the compressor and the system interface instead of one for the 333 Theora compressor. The two DMA FIFOs have also slight differences between the two design. Maybe a single 333 FIFO should be kept for the final design (?)

=== FPGA -> CPU data out MUX ===
The purpose of this MUX is to route data out from the different FPGA blocks to the system interface and then to the data bus to the CPU. The selection is made with the internal address bus ''ia''.
_
--| \
--| |
--| |
--| |--- iod[31:0] -> to system interface
--| |
--| |
|_/
from system interface -> ia[7:0]__|

'' 333 MUX ''
{|border="1" cellpadding="2"
! Adress range !! ia(5) !! ia(4) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''1''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''1''' || '''0''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''1''' || '''1''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0.. (even)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''0''' || dma_d0[31:0] || DMA 0 data
|-
| '''0x0.. (odd)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''1''' || dma_d1[31:0] || DMA 1 data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''X''' || '''X''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''X''' || '''X''' || dsdo[31:0] || Data out from descriptor memory
|-
| '''0x3..''' || '''0''' || '''1''' || '''1''' || '''X''' || '''X''' || bdo[31:0] || 32-bit data from SDRAM channel3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''X''' || '''0''' || '''X''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''X''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''X''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''X''' || '''X''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''X''' || '''X''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

'' 333 MUX ''
{|border="1" cellpadding="2"
! Address || ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || {24'b0,irqr[7:0]} || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(2) !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''0''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''0''' || '''1''' || '''1''' || MODELREV || Model revision
|-
| '''0x14''' || '''1''' || '''X''' || '''0''' || {8'h0,imgptr[23:0]} || Image pointer in 32-byte chunks
|-
| '''0x15''' || '''1''' || '''X''' || '''1''' || hifreq[31:0] || Accumulated high-freq components
|-
|}

'' 333 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock0
|-
| '''2''' || sr_sda1 || I2C
|-
| '''3''' || sr_scl1 || I2C clock1
|-
| '''4..12''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''17''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''18''' || 1'b0 || 0x0
|-
| '''19''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''20''' || itrig || TRIG input
|-
| '''21..22''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)
, 01 - clock is too late
, 10 - clock is too early
, 11 - OK (some measurements show too late, some - too early)
|-
| '''23''' || dcm_done ||
|-
| '''24''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''25''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''26''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''27''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''28''' || tok_frame_num_wr || Odd/even frame of tokens written
|-
| '''29''' || 1'b0 || 0x0
|-
| '''30''' || debug_out || Debug shift register output
|-
| '''31''' || 'b0 || 0x0
|-
|}

'' 353 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2''' || sr_ch0rdy || Ready to write next page (channel 0) SENSOR->SDRAM
|-
| '''3''' || sr_ch1rdy || Ready to read next page (channel 1) SDRAM->FPN(SENSOR)
|-
| '''4''' || sr_ch2rdy || Ready to read next page (channel 2) SDRAM->DMA
|-
| '''5''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''6''' || sr_wrempty || CPU write buffer empty (valid only in write mode). May reprogram channel3.
|-
| '''7..10''' || sr_nextFrame[3:0] || (level) generated before actual block is filled - needed to be combined with the pulse from buffer control
|-
| '''11..13''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''14''' || dcc_rdy || 128 of DC components from JPEG encoder are available (same as interrupt)
|-
| '''15''' || compressor_done_input || will go high after EOT and persist until DCT is enabled
|-
| '''16''' || compressor_done_compress || will go high after all data is sent out
|-
| '''17''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''19..18''' || dcm_err[1:0] || SDRAM DCM phase error
|-
| '''20''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''21''' || dcm_locked || SDRAM DCM overflow
|-
| '''22''' || dcm_status[0] || SDRAM DCM overflow
|-
| '''24..23''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''25''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''26''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''27''' || sens_dcm_status[0] || Sensor DCM overflow
|-
| '''28''' || clockios_locked || dcm locked
|-
| '''29..30''' || clockios_status[1:0] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''31''' || 1'b0 || 0x0
|-
|}

=== Control register ===
The dcr[31:0] bus is used to control the different blocks according to the control register values. The control register can be directly written by the CPU at the address 0x00.

''333 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0..2''' || Not used ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || iobuf || EXPS (output pin)
|-
| '''12''' || iobuf || EXPS (output pin)
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || i2cpads || scl1 out
|-
| '''20''' || i2cpads || scl1 enable
|-
| '''21''' || i2cpads || sda1 out
|-
| '''22''' || i2cpads || sda1 enable
|-
| '''23''' || Not used ||
|-
| '''24..27''' || clock_pclk || pclk source
|-
| '''28..30''' || Not used ||
|-
| '''31''' || clock_pclk || clk enable
|-
|}

''353 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0''' || Not used ||
|-
| '''1..2''' || compressor, sensorpix, histogram ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || sensorpads || sensor trigger
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || sensorpads || dclkmode
|-
| '''20''' || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || Not used ||
|-
| '''24..25''' || BUFGMUX || pclk source
|-
| '''28..30''' || compressor ||
|-
| '''31''' || clock_pclk ||
|-
|}

=== Others ===
* Looks like Theora compressor requires 90° phase clock that was abandoned in the 353 design.
Using different phases reduces AC component of the current through the power/ground lines of the FPGA by spreading register transitions. Theora has larger core so it may help spreading phases.--[[User:Andrey.filippov|Andrey.filippov]] 13:45, 25 February 2008 (CST)
* ...?

== Software updates ==

* Adapt FPGA definitions ([http://elphel.cvs.sourceforge.net/elphel/elphel353/elphel353/os/linux-2.6-tag--devboard-R2_01-1/arch/cris/arch-v32/drivers/elphel/x353.h?revision=1.8&view=markup&sortdir=down x353.h]) and most likely some other FPGA drivers.
* ...?

These lists of update are obviously incomplete. They need to be more detailed in order to make an exhaustive list of the changes that have to be done.

== 353 Theora new design ==
=== Compressor ===

=== Sensorpix ===

Some changes have to be done in this block to interface the sensor and the memory controller (ch0 and 1).

=== Memory controller ===

{|border="1" cellpadding="2"
! Channel !! Description
|-
| '''0''' || 8/16 bit data from sensor to SDRAM
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor
|-
| '''3''' || PIO read/write of SDRAM data
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63]
|-
| '''7''' || Reading 12-bit pre-tokens from SDRAM in indexed coded order
|-
|}

=== System interface ===

{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm || tune SDRAM clock phase
|-
| '''0x0a''' || da_framesync_dly || write frame sync interrupt delay (in scan lines)
|-
| '''0x0e''' || da_table_a0 || write gamma table address
|-
| '''0x0f''' || twr0 || write gamma table data
| -
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts || interrupt control
|-
| '''0x20..0x27''' || da_mcontr || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc || real time clock
|-
| '''0x48''' || da_timestamp || write timestamp mode
|-
| '''0x74''' || da_xjta0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync || control of external sync module 0x78 - 0x7b
|-
|}

=== Interrupts ===

{|border="1" cellpadding="2"
! irq_in !! Signal !! Comments
|-
| '''15..8''' || GND || Extra
|-
| '''7''' || compressor_done_compress || single-cycle pulse when the compressed frame is sent out
|-
| '''6''' || compressor_reset_compress || reset compressor done interrupt (writing any compressor command)
|-
| '''5''' || GND || dcc_rdy was tied to GND in the 333 design
|-
| '''4''' || GND || eot irq was tied to GND in the 333 design
|-
| '''3''' || sr_sensortrig[2] || (sync to pclk) - level, reset by writing to sensor triggering command register
|-
| '''2''' || xfer_over_irq || (sync to pclk) - frame acquisition over
|-
| '''1''' || trig_irq || (sync to pclk) - external trigger
|-
| '''0''' || vacts || (sync to pclk) - frame sync
|-
|}

=== DMA FIFOs ===
A single DMA FIFO from the 333 design will be instanciated.

=== FPGA -> CPU data out MUX ===

{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || '''0''' || '''x''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''x''' || '''x''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''x''' || '''0''' || '''x''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''x''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''x''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''x''' || '''x''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''x''' || '''x''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

{|border="1" cellpadding="2"
! Address !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' Status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C data
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2..10''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''11''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''12''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''17..18''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)

, 01 - clock is too late , 10 - clock is too early , 11 - OK (some measurements show too late, some - too early)
|-
| '''19''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''20''' || dcm_locked || SDRAM DCM overflow
|-
| '''21..22''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''23''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''24''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''25''' || clockios_locked || dcm locked
|-
| '''26''' || clockios_status[1] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''27''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''28''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''29''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''30''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''31''' || took_frame_num_wr || Odd/even frame of tokens written
|-
|}

=== Control register ===
{|border="1" cellpadding="2"
! bit # !! Signal || Destination block !! Comments
|-
| '''0''' || || Not used ||
|-
| '''1..2''' || cb_bayer_phase || compressor, sensorpix, histogram ||
|-
| '''3''' || || sensorpads || Inverts idclk phase (Not used)
|-
| '''4''' || cb_fillfactory || sensorpads || fillfactory sensor mode
|-
| '''5''' || cb_dlyhact || sensorpads || delay hact pulse by 1
|-
| '''6''' || cb_zoran || sensorpads || ''cb_zoran''
|-
| '''7''' || cb_skipline || sensorpads || skip first scan line from the sensor
|-
| '''8''' || cb_xt_pol || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || iarst || sensorpads || ''iarst''
|-
| '''10''' || iaro || sensorpads || ''iaro''
|-
| '''11''' || cb_encnvclk || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || cb_sensor_trigger || sensorpads || sensor trigger
|-
| '''13''' || imrst || sensorpads || ''imrst''
|-
| '''14''' || cb_scl0_o || iobuf || XRST (output pin)
|-
| '''15''' || cb_scl0_o || i2cpads || scl0 out
|-
| '''16''' || cb_scl0_en || i2cpads || scl0 enable
|-
| '''17''' || cb_sda0_o || i2cpads || sda0 out
|-
| '''18''' || cb_sda0_en || i2cpads || sda0 enable
|-
| '''19''' || cb_dclkmode || sensorpads || dclkmode
|-
| '''20''' || cb_pxd14 || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || cb_latehact || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || || Not used ||
|-
| '''24..25''' || cb_pclksrc || BUFGMUX || pclk source
|-
| '''28..30''' || || Not used ||
|-
| '''31''' || || Not used ||
|-
|}

=== Others ===

== See also ==

*[http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ 353 Theora CVS]
*[[Theora]]
*[[FPGA_Development_in_Elphel_cameras|FPGA Development in Elphel cameras]]
*[[Design Ideas|FPGA Theora Encoder for Videoconferencing]]
*[[10353]]

Talk:Porting Theora to 353 cameras

2008-03-31T08:37:38Z

JeremViewsurf:

Talk:Porting Theora to 353 cameras

2008-03-27T08:32:18Z

JeremViewsurf:

Talk:Porting Theora to 353 cameras

2008-03-26T16:46:54Z

JeremViewsurf:

Porting Theora to 353 cameras

2008-03-21T08:49:21Z

JeremViewsurf: /* Hardware updates */

Elphel model 333 cameras were able to encode and stream Ogg Theora with 6.3.9 firmware. However, this model is no longer produced by Elphel. The goal of this project is to use the full potential of 353 cameras (larger FPGA, faster CPU) in order to port the Ogg Theora feature on the new hardware. First, the camera should be able to upload small Theora clips via FTP.

Different solutions are possible as previously mentioned in the [[Theora]] page :
* Instantiate both the Theora compressor and the MJPEG compressor in the FPGA since the new Spartan 3E seems to be large enough to handle the two features.
* Replace the existing MJPEG compressor with the Theora compressor and implement software Theora to JPEG conversion if JPEG is needed.
* Replace the existing MJPEG compressor in the 353 camera with the Theora compressor and keep two configuration files on the camera filesystem (one for Theora the other for MJPEG). FPGA code could be changed at run-time according to the needs.

Dealing with the last solution seems to be a good start for this project as the other features mentioned can be added later. In all cases, both FPGA code and software code will need to be adapted.

The source code of this project is available at [http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/]
== Hardware updates ==

=== Compressor ===
[[Image:Schematic.png|frame|[[Media:Schematic.png|333 Theora design with the 2 stage compressor and the 8-channel memory controller]]]]
Replace the MJPEG compressor in the 353 with the 333 Theora compressor ([http://elphel.cvs.sourceforge.net/elphel/camera333/fpga/x333 333 Theora FPGA code]). Maybe some adaptations need to be done within the Theora compressor itself. However, assuming that the compressor worked in 333 cameras a simple instantiation should suffice.

=== Memory controller ===
Replace the 4-channel memory controller with an 8 channel memory interface as in the 333 model in order to handle Theora specific data.

{|border="1" cellpadding="2"
! Channel !! 333 Theora !! 353
|-
| '''0''' || 8/16 bit data from sensor to SDRAM || Data from the sensor (it can be combined with FPN correction data) to the SDRAM in either 8-bit mode or 16-bit
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module || Reads FPN data from SDRAM (8bit - subtract, 8 bit - scale) and feeds it to FPGA for FPN correction of the data on the way from sensor to SDRAM (through channel 0)
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor || Provides data to JPEG encoder in 16x16x8bit MCUs. It can also provide data directly to CPU through DMA bypassing any compression
|-
| '''3''' || PIO read/write of SDRAM data || Provides bidirectional access from CPU through 8x32 bit window.
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM ||
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM ||
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63] ||
|-
| '''7''' || reading 12-bit pre-tokens from SDRAM in indexed coded order ||
|-
|}

=== Sensor interface ===
''sensorpix'' block must be adapted in order to provide a coherent interface between the memory controller and the sensor (channels 0 and 1)

=== System Interface ===
Adapt the system interface to assure communication between FPGA and its environment.

A feature of the system interface is to establish communication between the system CPU and the different blocks within the FPGA (compressor, memory controller etc). This is done by selecting a block with the address bus ''a[12:0]'' connected to the internal address bus ''ial[7:0]'':

'''x353.v'''
always @ (posedge cwr) begin
a0[7:0]<=ial[7:0]; // may want to change to just ia if ia will be late enough;
wnr0 <= ~irnw;
da_ctl0 <= (ial[7:0]==8'h00); // 0x00 WE to control 32-bit register (1 loc)
da_dmamode0 <= (ial[7:0]==8'h01); // 0x01 select writing to dma_cntr/dma_raw (1 loc)
da_sensormode0 <= (ial[7:0]==8'h02); // 0x02 select writing to sensorpix (1 loc)
...
da_compressor0 <= (ial[7:1]==7'h06); // 0x0c..0x0d - will be farther decoded in the compressor module
...

Since memory controller and compressor are to be replaced these addresses have to be adapted.

''353 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x09''' || da_saturation0 || write color saturation values
|-
| '''0x0a''' || da_framesync_dly0 || write frame sync interrupt delay (in scan lines)
|-
| '''0x0c..0x0d''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x0e''' || da_table_a0 || write tables address
|-
| '''0x0f''' || twr0 || write tables data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts0 || interrupt control
|-
| '''0x20..0x2f''' || da_dswe0 || select reading/writing to mcontr (16 locations)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist0 || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc0 || real time clock
|-
| '''0x48''' || da_timestamp0 || write timestamp mode
|-
| '''0x74''' || da_xjtag0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync0 || control of external sync module 0x78 - 0x7b
|-
|}

''333 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or aftre trigger)
|-
| '''0x06''' || da_interrupts0 || interrupt mask
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x10''' || da_debug || write 0x10 any - load debug shift, read (through cs4) -shift
|-
| '''0x20..0x27''' || da_mcontr0 || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table0 || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
|}

Addresses 0x01,2,3,4,5,6,8 and 0x30 can be kept in the 353 system interface. The interrupt mask address 0x06 in the 333 sys interface is no longer used (353 uses interrupt vectors). The Theora compressor and the new memory controller addresses have to be mapped again in the new design (addresses 0x0c..0x0d and 0x20 to 0x2f in the 353 sys interface).

=== Interrupts ===
Adapt the Theora compressor interrupts to the 353 interrupt vector .

The 353 interrupt vector can handle up to 16 different irq. However, only irq 0 to 7 are used :
'''x353.v'''

assign irq_in= {8'b0, // extra
compressor_done_compress, // 7 - will go high after all data is sent out (reset by compressor)
compressor_done_input, // 6 - will go high after EOT and persist until DCT is enabled (reset by compressor)
dcc_rdy, // 5 - obsolete in 333 - channel3 has 128 more dc coefficients (or some if the compression is finished)
compressor_eot, // 4 - compressor read in the last MCU (predictable time to end of transfer)
sr_sensortrig[2], // 3 - (sync to pclk) - level, reset by writing to sensor triggering command register
xfer_over_irq, // 2 - (sync to pclk) - frame acquisition over
trig_irq, // 1 - (sync to pclk) - external trigger
vacts}; // 0 - (sync to pclk) - frame sync

353 MJPEG compressor triggers irqs 4, 6 and 7. 333 Theora compressor is the source of two irqs :
'''compressor_all.v'''

done, // single-cycle pulse when the compressed frame is sent out (IRQ source).
reset_compress, // reset compressor done interrupt (writing any compressor command)

Adaptation should consist of assigning Theora compressor irq sources to vectors 6 and 7 for example if the MJPEG compressor is to be replaced.

=== DMA FIFOs ===
353 design uses 2 DMA FIFOs between the compressor and the system interface instead of one for the 333 Theora compressor. The two DMA FIFOs have also slight differences between the two design. Maybe a single 333 FIFO should be kept for the final design (?)

=== FPGA -> CPU data out MUX ===
The purpose of this MUX is to route data out from the different FPGA blocks to the system interface and then to the data bus to the CPU. The selection is made with the internal address bus ''ia''.
_
--| \
--| |
--| |
--| |--- iod[31:0] -> to system interface
--| |
--| |
|_/
from system interface -> ia[7:0]__|

'' 333 MUX ''
{|border="1" cellpadding="2"
! Adress range !! ia(5) !! ia(4) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''1''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''1''' || '''0''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''1''' || '''1''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0.. (even)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''0''' || dma_d0[31:0] || DMA 0 data
|-
| '''0x0.. (odd)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''1''' || dma_d1[31:0] || DMA 1 data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''X''' || '''X''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''X''' || '''X''' || dsdo[31:0] || Data out from descriptor memory
|-
| '''0x3..''' || '''0''' || '''1''' || '''1''' || '''X''' || '''X''' || bdo[31:0] || 32-bit data from SDRAM channel3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''X''' || '''0''' || '''X''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''X''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''X''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''X''' || '''X''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''X''' || '''X''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

'' 333 MUX ''
{|border="1" cellpadding="2"
! Address || ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || {24'b0,irqr[7:0]} || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(2) !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''0''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''0''' || '''1''' || '''1''' || MODELREV || Model revision
|-
| '''0x14''' || '''1''' || '''X''' || '''0''' || {8'h0,imgptr[23:0]} || Image pointer in 32-byte chunks
|-
| '''0x15''' || '''1''' || '''X''' || '''1''' || hifreq[31:0] || Accumulated high-freq components
|-
|}

'' 333 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock0
|-
| '''2''' || sr_sda1 || I2C
|-
| '''3''' || sr_scl1 || I2C clock1
|-
| '''4..12''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''17''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''18''' || 1'b0 || 0x0
|-
| '''19''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''20''' || itrig || TRIG input
|-
| '''21..22''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)
, 01 - clock is too late
, 10 - clock is too early
, 11 - OK (some measurements show too late, some - too early)
|-
| '''23''' || dcm_done ||
|-
| '''24''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''25''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''26''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''27''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''28''' || tok_frame_num_wr || Odd/even frame of tokens written
|-
| '''29''' || 1'b0 || 0x0
|-
| '''30''' || debug_out || Debug shift register output
|-
| '''31''' || 'b0 || 0x0
|-
|}

'' 353 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2''' || sr_ch0rdy || Ready to write next page (channel 0) SENSOR->SDRAM
|-
| '''3''' || sr_ch1rdy || Ready to read next page (channel 1) SDRAM->FPN(SENSOR)
|-
| '''4''' || sr_ch2rdy || Ready to read next page (channel 2) SDRAM->DMA
|-
| '''5''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''6''' || sr_wrempty || CPU write buffer empty (valid only in write mode). May reprogram channel3.
|-
| '''7..10''' || sr_nextFrame[3:0] || (level) generated before actual block is filled - needed to be combined with the pulse from buffer control
|-
| '''11..13''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''14''' || dcc_rdy || 128 of DC components from JPEG encoder are available (same as interrupt)
|-
| '''15''' || compressor_done_input || will go high after EOT and persist until DCT is enabled
|-
| '''16''' || compressor_done_compress || will go high after all data is sent out
|-
| '''17''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''19..18''' || dcm_err[1:0] || SDRAM DCM phase error
|-
| '''20''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''21''' || dcm_locked || SDRAM DCM overflow
|-
| '''22''' || dcm_status[0] || SDRAM DCM overflow
|-
| '''24..23''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''25''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''26''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''27''' || sens_dcm_status[0] || Sensor DCM overflow
|-
| '''28''' || clockios_locked || dcm locked
|-
| '''29..30''' || clockios_status[1:0] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''31''' || 1'b0 || 0x0
|-
|}

=== Control register ===
The dcr[31:0] bus is used to control the different blocks according to the control register values. The control register can be directly written by the CPU at the address 0x00.

''333 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0..2''' || Not used ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || iobuf || EXPS (output pin)
|-
| '''12''' || iobuf || EXPS (output pin)
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || i2cpads || scl1 out
|-
| '''20''' || i2cpads || scl1 enable
|-
| '''21''' || i2cpads || sda1 out
|-
| '''22''' || i2cpads || sda1 enable
|-
| '''23''' || Not used ||
|-
| '''24..27''' || clock_pclk || pclk source
|-
| '''28..30''' || Not used ||
|-
| '''31''' || clock_pclk || clk enable
|-
|}

''353 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0''' || Not used ||
|-
| '''1..2''' || compressor, sensorpix, histogram ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || sensorpads || sensor trigger
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || sensorpads || dclkmode
|-
| '''20''' || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || Not used ||
|-
| '''24..25''' || BUFGMUX || pclk source
|-
| '''28..30''' || compressor ||
|-
| '''31''' || clock_pclk ||
|-
|}

=== Others ===
* Looks like Theora compressor requires 90° phase clock that was abandoned in the 353 design.
Using different phases reduces AC component of the current through the power/ground lines of the FPGA by spreading register transitions. Theora has larger core so it may help spreading phases.--[[User:Andrey.filippov|Andrey.filippov]] 13:45, 25 February 2008 (CST)
* ...?

== Software updates ==

* Adapt FPGA definitions ([http://elphel.cvs.sourceforge.net/elphel/elphel353/elphel353/os/linux-2.6-tag--devboard-R2_01-1/arch/cris/arch-v32/drivers/elphel/x353.h?revision=1.8&view=markup&sortdir=down x353.h]) and most likely some other FPGA drivers.
* ...?

These lists of update are obviously incomplete. They need to be more detailed in order to make an exhaustive list of the changes that have to be done.

== 353 Theora new design ==
=== Compressor ===

=== Sensorpix ===

Some changes have to be done in this block to interface the sensor and the memory controller (ch0 and 1).

=== Memory controller ===

{|border="1" cellpadding="2"
! Channel !! Description
|-
| '''0''' || 8/16 bit data from sensor to SDRAM
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor
|-
| '''3''' || PIO read/write of SDRAM data
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63]
|-
| '''7''' || Reading 12-bit pre-tokens from SDRAM in indexed coded order
|-
|}

=== System interface ===

{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm || tune SDRAM clock phase
|-
| '''0x0a''' || da_framesync_dly || write frame sync interrupt delay (in scan lines)
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts || interrupt control
|-
| '''0x20..0x27''' || da_mcontr || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc || real time clock
|-
| '''0x48''' || da_timestamp || write timestamp mode
|-
| '''0x74''' || da_xjta0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync || control of external sync module 0x78 - 0x7b
|-
|}

=== Interrupts ===

{|border="1" cellpadding="2"
! irq_in !! Signal !! Comments
|-
| '''15..8''' || GND || Extra
|-
| '''7''' || compressor_done_compress || single-cycle pulse when the compressed frame is sent out
|-
| '''6''' || compressor_reset_compress || reset compressor done interrupt (writing any compressor command)
|-
| '''5''' || GND || dcc_rdy was tied to GND in the 333 design
|-
| '''4''' || GND || eot irq was tied to GND in the 333 design
|-
| '''3''' || sr_sensortrig[2] || (sync to pclk) - level, reset by writing to sensor triggering command register
|-
| '''2''' || xfer_over_irq || (sync to pclk) - frame acquisition over
|-
| '''1''' || trig_irq || (sync to pclk) - external trigger
|-
| '''0''' || vacts || (sync to pclk) - frame sync
|-
|}

=== DMA FIFOs ===
A single DMA FIFO from the 333 design will be instanciated.

=== FPGA -> CPU data out MUX ===

{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || '''0''' || '''x''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''x''' || '''x''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''x''' || '''0''' || '''x''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''x''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''x''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''x''' || '''x''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''x''' || '''x''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

{|border="1" cellpadding="2"
! Address !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' Status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C data
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2..10''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''11''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''12''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''17..18''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)

, 01 - clock is too late , 10 - clock is too early , 11 - OK (some measurements show too late, some - too early)
|-
| '''19''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''20''' || dcm_locked || SDRAM DCM overflow
|-
| '''21..22''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''23''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''24''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''25''' || clockios_locked || dcm locked
|-
| '''26''' || clockios_status[1] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''27''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''28''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''29''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''30''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''31''' || took_frame_num_wr || Odd/even frame of tokens written
|-
|}

=== Control register ===
{|border="1" cellpadding="2"
! bit # !! Signal || Destination block !! Comments
|-
| '''0''' || || Not used ||
|-
| '''1..2''' || cb_bayer_phase || compressor, sensorpix, histogram ||
|-
| '''3''' || || sensorpads || Inverts idclk phase (Not used)
|-
| '''4''' || cb_fillfactory || sensorpads || fillfactory sensor mode
|-
| '''5''' || cb_dlyhact || sensorpads || delay hact pulse by 1
|-
| '''6''' || cb_zoran || sensorpads || ''cb_zoran''
|-
| '''7''' || cb_skipline || sensorpads || skip first scan line from the sensor
|-
| '''8''' || cb_xt_pol || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || iarst || sensorpads || ''iarst''
|-
| '''10''' || iaro || sensorpads || ''iaro''
|-
| '''11''' || cb_encnvclk || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || cb_sensor_trigger || sensorpads || sensor trigger
|-
| '''13''' || imrst || sensorpads || ''imrst''
|-
| '''14''' || cb_scl0_o || iobuf || XRST (output pin)
|-
| '''15''' || cb_scl0_o || i2cpads || scl0 out
|-
| '''16''' || cb_scl0_en || i2cpads || scl0 enable
|-
| '''17''' || cb_sda0_o || i2cpads || sda0 out
|-
| '''18''' || cb_sda0_en || i2cpads || sda0 enable
|-
| '''19''' || cb_dclkmode || sensorpads || dclkmode
|-
| '''20''' || cb_pxd14 || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || cb_latehact || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || || Not used ||
|-
| '''24..25''' || cb_pclksrc || BUFGMUX || pclk source
|-
| '''28..30''' || || Not used ||
|-
| '''31''' || || Not used ||
|-
|}

=== Others ===

== See also ==

*[http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ 353 Theora CVS]
*[[Theora]]
*[[FPGA_Development_in_Elphel_cameras|FPGA Development in Elphel cameras]]
*[[Design Ideas|FPGA Theora Encoder for Videoconferencing]]
*[[10353]]

Talk:Porting Theora to 353 cameras

2008-03-19T10:20:52Z

JeremViewsurf:

Talk:Porting Theora to 353 cameras

2008-03-11T14:22:20Z

JeremViewsurf:

Porting Theora to 353 cameras

2008-03-11T13:18:39Z

JeremViewsurf:

Elphel model 333 cameras were able to encode and stream Ogg Theora with 6.3.9 firmware. However, this model is no longer produced by Elphel. The goal of this project is to use the full potential of 353 cameras (larger FPGA, faster CPU) in order to port the Ogg Theora feature on the new hardware. First, the camera should be able to upload small Theora clips via FTP.

Different solutions are possible as previously mentioned in the [[Theora]] page :
* Instantiate both the Theora compressor and the MJPEG compressor in the FPGA since the new Spartan 3E seems to be large enough to handle the two features.
* Replace the existing MJPEG compressor with the Theora compressor and implement software Theora to JPEG conversion if JPEG is needed.
* Replace the existing MJPEG compressor in the 353 camera with the Theora compressor and keep two configuration files on the camera filesystem (one for Theora the other for MJPEG). FPGA code could be changed at run-time according to the needs.

Dealing with the last solution seems to be a good start for this project as the other features mentioned can be added later. In all cases, both FPGA code and software code will need to be adapted.

The source code of this project is available at [http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/]
== Hardware updates ==

=== Compressor ===
Replace the MJPEG compressor in the 353 with the 333 Theora compressor ([http://elphel.cvs.sourceforge.net/elphel/camera333/fpga/x333 333 Theora FPGA code]). Maybe some adaptations need to be done within the Theora compressor itself. However, assuming that the compressor worked in 333 cameras a simple instantiation should suffice.

=== Memory controller ===
Replace the 4-channel memory controller with an 8-channel memory interface as in the 333 model in order to handle Theora specific data.

{|border="1" cellpadding="2"
! Channel !! 333 Theora !! 353
|-
| '''0''' || 8/16 bit data from sensor to SDRAM || Data from the sensor (it can be combined with FPN correction data) to the SDRAM in either 8-bit mode or 16-bit
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module || Reads FPN data from SDRAM (8bit - subtract, 8 bit - scale) and feeds it to FPGA for FPN correction of the data on the way from sensor to SDRAM (through channel 0)
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor || Provides data to JPEG encoder in 16x16x8bit MCUs. It can also provide data directly to CPU through DMA bypassing any compression
|-
| '''3''' || PIO read/write of SDRAM data || Provides bidirectional access from CPU through 8x32 bit window.
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM ||
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM ||
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63] ||
|-
| '''7''' || reading 12-bit pre-tokens from SDRAM in indexed coded order ||
|-
|}

=== Sensor interface ===
''sensorpix'' block must be adapted in order to provide a coherent interface between the memory controller and the sensor (channels 0 and 1)

=== System Interface ===
Adapt the system interface to assure communication between FPGA and its environment.

A feature of the system interface is to establish communication between the system CPU and the different blocks within the FPGA (compressor, memory controller etc). This is done by selecting a block with the address bus ''a[12:0]'' connected to the internal address bus ''ial[7:0]'':

'''x353.v'''
always @ (posedge cwr) begin
a0[7:0]<=ial[7:0]; // may want to change to just ia if ia will be late enough;
wnr0 <= ~irnw;
da_ctl0 <= (ial[7:0]==8'h00); // 0x00 WE to control 32-bit register (1 loc)
da_dmamode0 <= (ial[7:0]==8'h01); // 0x01 select writing to dma_cntr/dma_raw (1 loc)
da_sensormode0 <= (ial[7:0]==8'h02); // 0x02 select writing to sensorpix (1 loc)
...
da_compressor0 <= (ial[7:1]==7'h06); // 0x0c..0x0d - will be farther decoded in the compressor module
...

Since memory controller and compressor are to be replaced these addresses have to be adapted.

''353 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x09''' || da_saturation0 || write color saturation values
|-
| '''0x0a''' || da_framesync_dly0 || write frame sync interrupt delay (in scan lines)
|-
| '''0x0c..0x0d''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x0e''' || da_table_a0 || write tables address
|-
| '''0x0f''' || twr0 || write tables data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts0 || interrupt control
|-
| '''0x20..0x2f''' || da_dswe0 || select reading/writing to mcontr (16 locations)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist0 || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc0 || real time clock
|-
| '''0x48''' || da_timestamp0 || write timestamp mode
|-
| '''0x74''' || da_xjtag0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync0 || control of external sync module 0x78 - 0x7b
|-
|}

''333 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or aftre trigger)
|-
| '''0x06''' || da_interrupts0 || interrupt mask
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x10''' || da_debug || write 0x10 any - load debug shift, read (through cs4) -shift
|-
| '''0x20..0x27''' || da_mcontr0 || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table0 || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
|}

Addresses 0x01,2,3,4,5,6,8 and 0x30 can be kept in the 353 system interface. The interrupt mask address 0x06 in the 333 sys interface is no longer used (353 uses interrupt vectors). The Theora compressor and the new memory controller addresses have to be mapped again in the new design (addresses 0x0c..0x0d and 0x20 to 0x2f in the 353 sys interface).

=== Interrupts ===
Adapt the Theora compressor interrupts to the 353 interrupt vector .

The 353 interrupt vector can handle up to 16 different irq. However, only irq 0 to 7 are used :
'''x353.v'''

assign irq_in= {8'b0, // extra
compressor_done_compress, // 7 - will go high after all data is sent out (reset by compressor)
compressor_done_input, // 6 - will go high after EOT and persist until DCT is enabled (reset by compressor)
dcc_rdy, // 5 - obsolete in 333 - channel3 has 128 more dc coefficients (or some if the compression is finished)
compressor_eot, // 4 - compressor read in the last MCU (predictable time to end of transfer)
sr_sensortrig[2], // 3 - (sync to pclk) - level, reset by writing to sensor triggering command register
xfer_over_irq, // 2 - (sync to pclk) - frame acquisition over
trig_irq, // 1 - (sync to pclk) - external trigger
vacts}; // 0 - (sync to pclk) - frame sync

353 MJPEG compressor triggers irqs 4, 6 and 7. 333 Theora compressor is the source of two irqs :
'''compressor_all.v'''

done, // single-cycle pulse when the compressed frame is sent out (IRQ source).
reset_compress, // reset compressor done interrupt (writing any compressor command)

Adaptation should consist of assigning Theora compressor irq sources to vectors 6 and 7 for example if the MJPEG compressor is to be replaced.

=== DMA FIFOs ===
353 design uses 2 DMA FIFOs between the compressor and the system interface instead of one for the 333 Theora compressor. The two DMA FIFOs have also slight differences between the two design. Maybe a single 333 FIFO should be kept for the final design (?)

=== FPGA -> CPU data out MUX ===
The purpose of this MUX is to route data out from the different FPGA blocks to the system interface and then to the data bus to the CPU. The selection is made with the internal address bus ''ia''.
_
--| \
--| |
--| |
--| |--- iod[31:0] -> to system interface
--| |
--| |
|_/
from system interface -> ia[7:0]__|

'' 333 MUX ''
{|border="1" cellpadding="2"
! Adress range !! ia(5) !! ia(4) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''1''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''1''' || '''0''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''1''' || '''1''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0.. (even)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''0''' || dma_d0[31:0] || DMA 0 data
|-
| '''0x0.. (odd)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''1''' || dma_d1[31:0] || DMA 1 data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''X''' || '''X''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''X''' || '''X''' || dsdo[31:0] || Data out from descriptor memory
|-
| '''0x3..''' || '''0''' || '''1''' || '''1''' || '''X''' || '''X''' || bdo[31:0] || 32-bit data from SDRAM channel3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''X''' || '''0''' || '''X''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''X''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''X''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''X''' || '''X''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''X''' || '''X''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

'' 333 MUX ''
{|border="1" cellpadding="2"
! Address || ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || {24'b0,irqr[7:0]} || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(2) !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''0''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''0''' || '''1''' || '''1''' || MODELREV || Model revision
|-
| '''0x14''' || '''1''' || '''X''' || '''0''' || {8'h0,imgptr[23:0]} || Image pointer in 32-byte chunks
|-
| '''0x15''' || '''1''' || '''X''' || '''1''' || hifreq[31:0] || Accumulated high-freq components
|-
|}

'' 333 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock0
|-
| '''2''' || sr_sda1 || I2C
|-
| '''3''' || sr_scl1 || I2C clock1
|-
| '''4..12''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''17''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''18''' || 1'b0 || 0x0
|-
| '''19''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''20''' || itrig || TRIG input
|-
| '''21..22''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)
, 01 - clock is too late
, 10 - clock is too early
, 11 - OK (some measurements show too late, some - too early)
|-
| '''23''' || dcm_done ||
|-
| '''24''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''25''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''26''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''27''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''28''' || tok_frame_num_wr || Odd/even frame of tokens written
|-
| '''29''' || 1'b0 || 0x0
|-
| '''30''' || debug_out || Debug shift register output
|-
| '''31''' || 'b0 || 0x0
|-
|}

'' 353 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2''' || sr_ch0rdy || Ready to write next page (channel 0) SENSOR->SDRAM
|-
| '''3''' || sr_ch1rdy || Ready to read next page (channel 1) SDRAM->FPN(SENSOR)
|-
| '''4''' || sr_ch2rdy || Ready to read next page (channel 2) SDRAM->DMA
|-
| '''5''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''6''' || sr_wrempty || CPU write buffer empty (valid only in write mode). May reprogram channel3.
|-
| '''7..10''' || sr_nextFrame[3:0] || (level) generated before actual block is filled - needed to be combined with the pulse from buffer control
|-
| '''11..13''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''14''' || dcc_rdy || 128 of DC components from JPEG encoder are available (same as interrupt)
|-
| '''15''' || compressor_done_input || will go high after EOT and persist until DCT is enabled
|-
| '''16''' || compressor_done_compress || will go high after all data is sent out
|-
| '''17''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''19..18''' || dcm_err[1:0] || SDRAM DCM phase error
|-
| '''20''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''21''' || dcm_locked || SDRAM DCM overflow
|-
| '''22''' || dcm_status[0] || SDRAM DCM overflow
|-
| '''24..23''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''25''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''26''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''27''' || sens_dcm_status[0] || Sensor DCM overflow
|-
| '''28''' || clockios_locked || dcm locked
|-
| '''29..30''' || clockios_status[1:0] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''31''' || 1'b0 || 0x0
|-
|}

=== Control register ===
The dcr[31:0] bus is used to control the different blocks according to the control register values. The control register can be directly written by the CPU at the address 0x00.

''333 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0..2''' || Not used ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || iobuf || EXPS (output pin)
|-
| '''12''' || iobuf || EXPS (output pin)
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || i2cpads || scl1 out
|-
| '''20''' || i2cpads || scl1 enable
|-
| '''21''' || i2cpads || sda1 out
|-
| '''22''' || i2cpads || sda1 enable
|-
| '''23''' || Not used ||
|-
| '''24..27''' || clock_pclk || pclk source
|-
| '''28..30''' || Not used ||
|-
| '''31''' || clock_pclk || clk enable
|-
|}

''353 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0''' || Not used ||
|-
| '''1..2''' || compressor, sensorpix, histogram ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || sensorpads || sensor trigger
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || sensorpads || dclkmode
|-
| '''20''' || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || Not used ||
|-
| '''24..25''' || BUFGMUX || pclk source
|-
| '''28..30''' || compressor ||
|-
| '''31''' || clock_pclk ||
|-
|}

=== Others ===
* Looks like Theora compressor requires 90° phase clock that was abandoned in the 353 design.
Using different phases reduces AC component of the current through the power/ground lines of the FPGA by spreading register transitions. Theora has larger core so it may help spreading phases.--[[User:Andrey.filippov|Andrey.filippov]] 13:45, 25 February 2008 (CST)
* ...?

== Software updates ==

* Adapt FPGA definitions ([http://elphel.cvs.sourceforge.net/elphel/elphel353/elphel353/os/linux-2.6-tag--devboard-R2_01-1/arch/cris/arch-v32/drivers/elphel/x353.h?revision=1.8&view=markup&sortdir=down x353.h]) and most likely some other FPGA drivers.
* ...?

These lists of update are obviously incomplete. They need to be more detailed in order to make an exhaustive list of the changes that have to be done.

== 353 Theora new design ==
=== Compressor ===

=== Sensorpix ===

Some changes have to be done in this block to interface the sensor and the memory controller (ch0 and 1).

=== Memory controller ===

{|border="1" cellpadding="2"
! Channel !! Description
|-
| '''0''' || 8/16 bit data from sensor to SDRAM
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor
|-
| '''3''' || PIO read/write of SDRAM data
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63]
|-
| '''7''' || Reading 12-bit pre-tokens from SDRAM in indexed coded order
|-
|}

=== System interface ===

{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm || tune SDRAM clock phase
|-
| '''0x0a''' || da_framesync_dly || write frame sync interrupt delay (in scan lines)
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts || interrupt control
|-
| '''0x20..0x27''' || da_mcontr || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc || real time clock
|-
| '''0x48''' || da_timestamp || write timestamp mode
|-
| '''0x74''' || da_xjta0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync || control of external sync module 0x78 - 0x7b
|-
|}

=== Interrupts ===

{|border="1" cellpadding="2"
! irq_in !! Signal !! Comments
|-
| '''15..8''' || GND || Extra
|-
| '''7''' || compressor_done_compress || single-cycle pulse when the compressed frame is sent out
|-
| '''6''' || compressor_reset_compress || reset compressor done interrupt (writing any compressor command)
|-
| '''5''' || GND || dcc_rdy was tied to GND in the 333 design
|-
| '''4''' || GND || eot irq was tied to GND in the 333 design
|-
| '''3''' || sr_sensortrig[2] || (sync to pclk) - level, reset by writing to sensor triggering command register
|-
| '''2''' || xfer_over_irq || (sync to pclk) - frame acquisition over
|-
| '''1''' || trig_irq || (sync to pclk) - external trigger
|-
| '''0''' || vacts || (sync to pclk) - frame sync
|-
|}

=== DMA FIFOs ===
A single DMA FIFO from the 333 design will be instanciated.

=== FPGA -> CPU data out MUX ===

{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || '''0''' || '''x''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''x''' || '''x''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''x''' || '''0''' || '''x''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''x''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''x''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''x''' || '''x''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''x''' || '''x''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

{|border="1" cellpadding="2"
! Address !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' Status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C data
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2..10''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''11''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''12''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''17..18''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)

, 01 - clock is too late , 10 - clock is too early , 11 - OK (some measurements show too late, some - too early)
|-
| '''19''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''20''' || dcm_locked || SDRAM DCM overflow
|-
| '''21..22''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''23''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''24''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''25''' || clockios_locked || dcm locked
|-
| '''26''' || clockios_status[1] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''27''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''28''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''29''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''30''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''31''' || took_frame_num_wr || Odd/even frame of tokens written
|-
|}

=== Control register ===
{|border="1" cellpadding="2"
! bit # !! Signal || Destination block !! Comments
|-
| '''0''' || || Not used ||
|-
| '''1..2''' || cb_bayer_phase || compressor, sensorpix, histogram ||
|-
| '''3''' || || sensorpads || Inverts idclk phase (Not used)
|-
| '''4''' || cb_fillfactory || sensorpads || fillfactory sensor mode
|-
| '''5''' || cb_dlyhact || sensorpads || delay hact pulse by 1
|-
| '''6''' || cb_zoran || sensorpads || ''cb_zoran''
|-
| '''7''' || cb_skipline || sensorpads || skip first scan line from the sensor
|-
| '''8''' || cb_xt_pol || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || iarst || sensorpads || ''iarst''
|-
| '''10''' || iaro || sensorpads || ''iaro''
|-
| '''11''' || cb_encnvclk || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || cb_sensor_trigger || sensorpads || sensor trigger
|-
| '''13''' || imrst || sensorpads || ''imrst''
|-
| '''14''' || cb_scl0_o || iobuf || XRST (output pin)
|-
| '''15''' || cb_scl0_o || i2cpads || scl0 out
|-
| '''16''' || cb_scl0_en || i2cpads || scl0 enable
|-
| '''17''' || cb_sda0_o || i2cpads || sda0 out
|-
| '''18''' || cb_sda0_en || i2cpads || sda0 enable
|-
| '''19''' || cb_dclkmode || sensorpads || dclkmode
|-
| '''20''' || cb_pxd14 || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || cb_latehact || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || || Not used ||
|-
| '''24..25''' || cb_pclksrc || BUFGMUX || pclk source
|-
| '''28..30''' || || Not used ||
|-
| '''31''' || || Not used ||
|-
|}

=== Others ===

== See also ==

*[http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ 353 Theora CVS]
*[[Theora]]
*[[FPGA_Development_in_Elphel_cameras|FPGA Development in Elphel cameras]]
*[[Design Ideas|FPGA Theora Encoder for Videoconferencing]]
*[[10353]]

Porting Theora to 353 cameras

2008-03-11T13:18:05Z

JeremViewsurf:

Elphel model 333 cameras were able to encode and stream Ogg Theora with 6.3.9 firmware. However, this model is no longer produced by Elphel. The goal of this project is to use the full potential of 353 cameras (larger FPGA, faster CPU) in order to port the Ogg Theora feature on the new hardware. First, the camera should be able to upload small Theora clips via FTP.

Different solutions are possible as previously mentioned in the [[Theora]] page :
* Instantiate both the Theora compressor and the MJPEG compressor in the FPGA since the new Spartan 3E seems to be large enough to handle the two features.
* Replace the existing MJPEG compressor with the Theora compressor and implement software Theora to JPEG conversion if JPEG is needed.
* Replace the existing MJPEG compressor in the 353 camera with the Theora compressor and keep two configuration files on the camera filesystem (one for Theora the other for MJPEG). FPGA code could be changed at run-time according to the needs.

Dealing with the last solution seems to be a good start for this project as the other features mentioned can be added later. In all cases, both FPGA code and software code will need to be adapted.

The source code of this project is available at [http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/]
== Hardware updates ==

=== Compressor ===
Replace the MJPEG compressor in the 353 with the 333 Theora compressor ([http://elphel.cvs.sourceforge.net/elphel/camera333/fpga/x333 333 Theora FPGA code]). Maybe some adaptations need to be done within the Theora compressor itself. However, assuming that the compressor worked in 333 cameras a simple instantiation should suffice.

=== Memory controller ===
Replace the 4-channel memory controller with an 8-channel memory interface as in the 333 model in order to handle Theora specific data.

{|border="1" cellpadding="2"
! Channel !! 333 Theora !! 353
|-
| '''0''' || 8/16 bit data from sensor to SDRAM || Data from the sensor (it can be combined with FPN correction data) to the SDRAM in either 8-bit mode or 16-bit
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module || Reads FPN data from SDRAM (8bit - subtract, 8 bit - scale) and feeds it to FPGA for FPN correction of the data on the way from sensor to SDRAM (through channel 0)
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor || Provides data to JPEG encoder in 16x16x8bit MCUs. It can also provide data directly to CPU through DMA bypassing any compression
|-
| '''3''' || PIO read/write of SDRAM data || Provides bidirectional access from CPU through 8x32 bit window.
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM ||
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM ||
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63] ||
|-
| '''7''' || reading 12-bit pre-tokens from SDRAM in indexed coded order ||
|-
|}

=== Sensor interface ===
''sensorpix'' block must be adapted in order to provide a coherent interface between the memory controller and the sensor (channels 0 and 1)

=== System Interface ===
Adapt the system interface to assure communication between FPGA and its environment.

A feature of the system interface is to establish communication between the system CPU and the different blocks within the FPGA (compressor, memory controller etc). This is done by selecting a block with the address bus ''a[12:0]'' connected to the internal address bus ''ial[7:0]'':

'''x353.v'''
always @ (posedge cwr) begin
a0[7:0]<=ial[7:0]; // may want to change to just ia if ia will be late enough;
wnr0 <= ~irnw;
da_ctl0 <= (ial[7:0]==8'h00); // 0x00 WE to control 32-bit register (1 loc)
da_dmamode0 <= (ial[7:0]==8'h01); // 0x01 select writing to dma_cntr/dma_raw (1 loc)
da_sensormode0 <= (ial[7:0]==8'h02); // 0x02 select writing to sensorpix (1 loc)
...
da_compressor0 <= (ial[7:1]==7'h06); // 0x0c..0x0d - will be farther decoded in the compressor module
...

Since memory controller and compressor are to be replaced these addresses have to be adapted.

''353 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x09''' || da_saturation0 || write color saturation values
|-
| '''0x0a''' || da_framesync_dly0 || write frame sync interrupt delay (in scan lines)
|-
| '''0x0c..0x0d''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x0e''' || da_table_a0 || write tables address
|-
| '''0x0f''' || twr0 || write tables data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts0 || interrupt control
|-
| '''0x20..0x2f''' || da_dswe0 || select reading/writing to mcontr (16 locations)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist0 || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc0 || real time clock
|-
| '''0x48''' || da_timestamp0 || write timestamp mode
|-
| '''0x74''' || da_xjtag0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync0 || control of external sync module 0x78 - 0x7b
|-
|}

''333 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or aftre trigger)
|-
| '''0x06''' || da_interrupts0 || interrupt mask
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x10''' || da_debug || write 0x10 any - load debug shift, read (through cs4) -shift
|-
| '''0x20..0x27''' || da_mcontr0 || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table0 || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
|}

Addresses 0x01,2,3,4,5,6,8 and 0x30 can be kept in the 353 system interface. The interrupt mask address 0x06 in the 333 sys interface is no longer used (353 uses interrupt vectors). The Theora compressor and the new memory controller addresses have to be mapped again in the new design (addresses 0x0c..0x0d and 0x20 to 0x2f in the 353 sys interface).

=== Interrupts ===
Adapt the Theora compressor interrupts to the 353 interrupt vector .

The 353 interrupt vector can handle up to 16 different irq. However, only irq 0 to 7 are used :
'''x353.v'''

assign irq_in= {8'b0, // extra
compressor_done_compress, // 7 - will go high after all data is sent out (reset by compressor)
compressor_done_input, // 6 - will go high after EOT and persist until DCT is enabled (reset by compressor)
dcc_rdy, // 5 - obsolete in 333 - channel3 has 128 more dc coefficients (or some if the compression is finished)
compressor_eot, // 4 - compressor read in the last MCU (predictable time to end of transfer)
sr_sensortrig[2], // 3 - (sync to pclk) - level, reset by writing to sensor triggering command register
xfer_over_irq, // 2 - (sync to pclk) - frame acquisition over
trig_irq, // 1 - (sync to pclk) - external trigger
vacts}; // 0 - (sync to pclk) - frame sync

353 MJPEG compressor triggers irqs 4, 6 and 7. 333 Theora compressor is the source of two irqs :
'''compressor_all.v'''

done, // single-cycle pulse when the compressed frame is sent out (IRQ source).
reset_compress, // reset compressor done interrupt (writing any compressor command)

Adaptation should consist of assigning Theora compressor irq sources to vectors 6 and 7 for example if the MJPEG compressor is to be replaced.

=== DMA FIFOs ===
353 design uses 2 DMA FIFOs between the compressor and the system interface instead of one for the 333 Theora compressor. The two DMA FIFOs have also slight differences between the two design. Maybe a single 333 FIFO should be kept for the final design (?)

=== FPGA -> CPU data out MUX ===
The purpose of this MUX is to route data out from the different FPGA blocks to the system interface and then to the data bus to the CPU. The selection is made with the internal address bus ''ia''.
_
--| \
--| |
--| |
--| |--- iod[31:0] -> to system interface
--| |
--| |
|_/
from system interface -> ia[7:0]__|

'' 333 MUX ''
{|border="1" cellpadding="2"
! Adress range !! ia(5) !! ia(4) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''1''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''1''' || '''0''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''1''' || '''1''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0.. (even)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''0''' || dma_d0[31:0] || DMA 0 data
|-
| '''0x0.. (odd)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''1''' || dma_d1[31:0] || DMA 1 data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''X''' || '''X''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''X''' || '''X''' || dsdo[31:0] || Data out from descriptor memory
|-
| '''0x3..''' || '''0''' || '''1''' || '''1''' || '''X''' || '''X''' || bdo[31:0] || 32-bit data from SDRAM channel3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''X''' || '''0''' || '''X''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''X''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''X''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''X''' || '''X''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''X''' || '''X''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

'' 333 MUX ''
{|border="1" cellpadding="2"
! Address || ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || {24'b0,irqr[7:0]} || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(2) !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''0''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''0''' || '''1''' || '''1''' || MODELREV || Model revision
|-
| '''0x14''' || '''1''' || '''X''' || '''0''' || {8'h0,imgptr[23:0]} || Image pointer in 32-byte chunks
|-
| '''0x15''' || '''1''' || '''X''' || '''1''' || hifreq[31:0] || Accumulated high-freq components
|-
|}

'' 333 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock0
|-
| '''2''' || sr_sda1 || I2C
|-
| '''3''' || sr_scl1 || I2C clock1
|-
| '''4..12''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''17''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''18''' || 1'b0 || 0x0
|-
| '''19''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''20''' || itrig || TRIG input
|-
| '''21..22''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)
, 01 - clock is too late
, 10 - clock is too early
, 11 - OK (some measurements show too late, some - too early)
|-
| '''23''' || dcm_done ||
|-
| '''24''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''25''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''26''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''27''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''28''' || tok_frame_num_wr || Odd/even frame of tokens written
|-
| '''29''' || 1'b0 || 0x0
|-
| '''30''' || debug_out || Debug shift register output
|-
| '''31''' || 'b0 || 0x0
|-
|}

'' 353 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2''' || sr_ch0rdy || Ready to write next page (channel 0) SENSOR->SDRAM
|-
| '''3''' || sr_ch1rdy || Ready to read next page (channel 1) SDRAM->FPN(SENSOR)
|-
| '''4''' || sr_ch2rdy || Ready to read next page (channel 2) SDRAM->DMA
|-
| '''5''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''6''' || sr_wrempty || CPU write buffer empty (valid only in write mode). May reprogram channel3.
|-
| '''7..10''' || sr_nextFrame[3:0] || (level) generated before actual block is filled - needed to be combined with the pulse from buffer control
|-
| '''11..13''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''14''' || dcc_rdy || 128 of DC components from JPEG encoder are available (same as interrupt)
|-
| '''15''' || compressor_done_input || will go high after EOT and persist until DCT is enabled
|-
| '''16''' || compressor_done_compress || will go high after all data is sent out
|-
| '''17''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''19..18''' || dcm_err[1:0] || SDRAM DCM phase error
|-
| '''20''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''21''' || dcm_locked || SDRAM DCM overflow
|-
| '''22''' || dcm_status[0] || SDRAM DCM overflow
|-
| '''24..23''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''25''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''26''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''27''' || sens_dcm_status[0] || Sensor DCM overflow
|-
| '''28''' || clockios_locked || dcm locked
|-
| '''29..30''' || clockios_status[1:0] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''31''' || 1'b0 || 0x0
|-
|}

=== Control register ===
The dcr[31:0] bus is used to control the different blocks according to the control register values. The control register can be directly written by the CPU at the address 0x00.

''333 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0..2''' || Not used ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || iobuf || EXPS (output pin)
|-
| '''12''' || iobuf || EXPS (output pin)
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || i2cpads || scl1 out
|-
| '''20''' || i2cpads || scl1 enable
|-
| '''21''' || i2cpads || sda1 out
|-
| '''22''' || i2cpads || sda1 enable
|-
| '''23''' || Not used ||
|-
| '''24..27''' || clock_pclk || pclk source
|-
| '''28..30''' || Not used ||
|-
| '''31''' || clock_pclk || clk enable
|-
|}

''353 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0''' || Not used ||
|-
| '''1..2''' || compressor, sensorpix, histogram ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || sensorpads || sensor trigger
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || sensorpads || dclkmode
|-
| '''20''' || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || Not used ||
|-
| '''24..25''' || BUFGMUX || pclk source
|-
| '''28..30''' || compressor ||
|-
| '''31''' || clock_pclk ||
|-
|}

=== Others ===
* Looks like Theora compressor requires 90° phase clock that was abandoned in the 353 design.
Using different phases reduces AC component of the current through the power/ground lines of the FPGA by spreading register transitions. Theora has larger core so it may help spreading phases.--[[User:Andrey.filippov|Andrey.filippov]] 13:45, 25 February 2008 (CST)
* ...?

== Software updates ==

* Adapt FPGA definitions ([http://elphel.cvs.sourceforge.net/elphel/elphel353/elphel353/os/linux-2.6-tag--devboard-R2_01-1/arch/cris/arch-v32/drivers/elphel/x353.h?revision=1.8&view=markup&sortdir=down x353.h]) and most likely some other FPGA drivers.
* ...?

These lists of update are obviously incomplete. They need to be more detailed in order to make an exhaustive list of the changes that have to be done.

== 353 Theora new design ==
=== Compressor ===

=== Sensorpix ===

Some changes have to be done in this block to interface the sensor and the memory controller (ch0 and 1).

=== Memory controller ===

{|border="1" cellpadding="2"
! Channel !! Description
|-
| '''0''' || 8/16 bit data from sensor to SDRAM
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor
|-
| '''3''' || PIO read/write of SDRAM data
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63]
|-
| '''7''' || Reading 12-bit pre-tokens from SDRAM in indexed coded order
|-
|}

=== System interface ===

{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm || tune SDRAM clock phase
|-
| '''0x0a''' || da_framesync_dly || write frame sync interrupt delay (in scan lines)
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts || interrupt control
|-
| '''0x20..0x27''' || da_mcontr || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc || real time clock
|-
| '''0x48''' || da_timestamp || write timestamp mode
|-
| '''0x74''' || da_xjta0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync || control of external sync module 0x78 - 0x7b
|-
|}

=== Interrupts ===

{|border="1" cellpadding="2"
! irq_in !! Signal !! Comments
|-
| '''15..8''' || GND || Extra
|-
| '''7''' || compressor_done_compress || single-cycle pulse when the compressed frame is sent out
|-
| '''6''' || compressor_reset_compress || reset compressor done interrupt (writing any compressor command)
|-
| '''5''' || GND || dcc_rdy was tied to GND in the 333 design
|-
| '''4''' || GND || eot irq was tied to GND in the 333 design
|-
| '''3''' || sr_sensortrig[2] || (sync to pclk) - level, reset by writing to sensor triggering command register
|-
| '''2''' || xfer_over_irq || (sync to pclk) - frame acquisition over
|-
| '''1''' || trig_irq || (sync to pclk) - external trigger
|-
| '''0''' || vacts || (sync to pclk) - frame sync
|-
|}

=== DMA FIFOs ===
A single DMA FIFO from the 333 design will be instanciated.

=== FPGA -> CPU data out MUX ===

{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || '''0''' || '''x''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''x''' || '''x''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''x''' || '''0''' || '''x''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''x''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''x''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''x''' || '''x''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''x''' || '''x''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

{|border="1" cellpadding="2"
! Address !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' Status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C data
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2..10''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''11''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''12''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''17..18''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)

, 01 - clock is too late , 10 - clock is too early , 11 - OK (some measurements show too late, some - too early)
|-
| '''19''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''20''' || dcm_locked || SDRAM DCM overflow
|-
| '''21..22''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''23''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''24''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''25''' || clockios_locked || dcm locked
|-
| '''26''' || clockios_status[1] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''27''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''28''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''29''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''30''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''31''' || took_frame_num_wr || Odd/even frame of tokens written
|-
|}

=== Control register ===
{|border="1" cellpadding="2"
! bit # !! Signal || Destination block !! Comments
|-
| '''0''' || || Not used ||
|-
| '''1..2''' || cb_bayer_phase || compressor, sensorpix, histogram ||
|-
| '''3''' || || sensorpads || Inverts idclk phase (Not used)
|-
| '''4''' || cb_fillfactory || sensorpads || fillfactory sensor mode
|-
| '''5''' || cb_dlyhact || sensorpads || delay hact pulse by 1
|-
| '''6''' || cb_zoran || sensorpads || ''cb_zoran''
|-
| '''7''' || cb_skipline || sensorpads || skip first scan line from the sensor
|-
| '''8''' || cb_xt_pol || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || iarst || sensorpads || ''iarst''
|-
| '''10''' || iaro || sensorpads || ''iaro''
|-
| '''11''' || cb_encnvclk || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || cb_sensor_trigger || sensorpads || sensor trigger
|-
| '''13''' || imrst || sensorpads || ''imrst''
|-
| '''14''' || cb_scl0_o || iobuf || XRST (output pin)
|-
| '''15''' || cb_scl0_o || i2cpads || scl0 out
|-
| '''16''' || cb_scl0_en || i2cpads || scl0 enable
|-
| '''17''' || cb_sda0_o || i2cpads || sda0 out
|-
| '''18''' || cb_sda0_en || i2cpads || sda0 enable
|-
| '''19''' || cb_dclkmode || sensorpads || dclkmode
|-
| '''20''' || cb_pxd14 || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || cb_latehact || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || || Not used ||
|-
| '''24..25''' || cb_pclksrc || BUFGMUX || pclk source
|-
| '''28..30''' || || Not used ||
|-
| '''31''' || || Not used ||
|-
|}

=== Others ===

== See also ==

*[http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ 353 Theora CVS]
*[[Theora]]
*[[FPGA_Development_in_Elphel_cameras|FPGA Development in Elphel cameras]]
*[[Design Ideas|FPGA Theora Encoder for Videoconferencing]]
*[[10353]]

Porting Theora to 353 cameras

2008-03-11T13:17:28Z

JeremViewsurf: /* See also */

Elphel model 333 cameras were able to encode and stream Ogg Theora with 6.3.9 firmware. However, this model is no longer produced by Elphel. The goal of this project is to use the full potential of 353 cameras (larger FPGA, faster CPU) in order to port the Ogg Theora feature on the new hardware. First, the camera should be able to upload small Theora clips via FTP.

Different solutions are possible as previously mentioned in the [[Theora]] page :
* Instantiate both the Theora compressor and the MJPEG compressor in the FPGA since the new Spartan 3E seems to be large enough to handle the two features.
* Replace the existing MJPEG compressor with the Theora compressor and implement software Theora to JPEG conversion if JPEG is needed.
* Replace the existing MJPEG compressor in the 353 camera with the Theora compressor and keep two configuration files on the camera filesystem (one for Theora the other for MJPEG). FPGA code could be changed at run-time according to the needs.

Dealing with the last solution seems to be a good start for this project as the other features mentioned can be added later. In all cases, both FPGA code and software code will need to be adapted.

== Hardware updates ==

=== Compressor ===
Replace the MJPEG compressor in the 353 with the 333 Theora compressor ([http://elphel.cvs.sourceforge.net/elphel/camera333/fpga/x333 333 Theora FPGA code]). Maybe some adaptations need to be done within the Theora compressor itself. However, assuming that the compressor worked in 333 cameras a simple instantiation should suffice.

=== Memory controller ===
Replace the 4-channel memory controller with an 8-channel memory interface as in the 333 model in order to handle Theora specific data.

{|border="1" cellpadding="2"
! Channel !! 333 Theora !! 353
|-
| '''0''' || 8/16 bit data from sensor to SDRAM || Data from the sensor (it can be combined with FPN correction data) to the SDRAM in either 8-bit mode or 16-bit
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module || Reads FPN data from SDRAM (8bit - subtract, 8 bit - scale) and feeds it to FPGA for FPN correction of the data on the way from sensor to SDRAM (through channel 0)
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor || Provides data to JPEG encoder in 16x16x8bit MCUs. It can also provide data directly to CPU through DMA bypassing any compression
|-
| '''3''' || PIO read/write of SDRAM data || Provides bidirectional access from CPU through 8x32 bit window.
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM ||
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM ||
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63] ||
|-
| '''7''' || reading 12-bit pre-tokens from SDRAM in indexed coded order ||
|-
|}

=== Sensor interface ===
''sensorpix'' block must be adapted in order to provide a coherent interface between the memory controller and the sensor (channels 0 and 1)

=== System Interface ===
Adapt the system interface to assure communication between FPGA and its environment.

A feature of the system interface is to establish communication between the system CPU and the different blocks within the FPGA (compressor, memory controller etc). This is done by selecting a block with the address bus ''a[12:0]'' connected to the internal address bus ''ial[7:0]'':

'''x353.v'''
always @ (posedge cwr) begin
a0[7:0]<=ial[7:0]; // may want to change to just ia if ia will be late enough;
wnr0 <= ~irnw;
da_ctl0 <= (ial[7:0]==8'h00); // 0x00 WE to control 32-bit register (1 loc)
da_dmamode0 <= (ial[7:0]==8'h01); // 0x01 select writing to dma_cntr/dma_raw (1 loc)
da_sensormode0 <= (ial[7:0]==8'h02); // 0x02 select writing to sensorpix (1 loc)
...
da_compressor0 <= (ial[7:1]==7'h06); // 0x0c..0x0d - will be farther decoded in the compressor module
...

Since memory controller and compressor are to be replaced these addresses have to be adapted.

''353 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x09''' || da_saturation0 || write color saturation values
|-
| '''0x0a''' || da_framesync_dly0 || write frame sync interrupt delay (in scan lines)
|-
| '''0x0c..0x0d''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x0e''' || da_table_a0 || write tables address
|-
| '''0x0f''' || twr0 || write tables data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts0 || interrupt control
|-
| '''0x20..0x2f''' || da_dswe0 || select reading/writing to mcontr (16 locations)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist0 || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc0 || real time clock
|-
| '''0x48''' || da_timestamp0 || write timestamp mode
|-
| '''0x74''' || da_xjtag0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync0 || control of external sync module 0x78 - 0x7b
|-
|}

''333 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or aftre trigger)
|-
| '''0x06''' || da_interrupts0 || interrupt mask
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x10''' || da_debug || write 0x10 any - load debug shift, read (through cs4) -shift
|-
| '''0x20..0x27''' || da_mcontr0 || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table0 || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
|}

Addresses 0x01,2,3,4,5,6,8 and 0x30 can be kept in the 353 system interface. The interrupt mask address 0x06 in the 333 sys interface is no longer used (353 uses interrupt vectors). The Theora compressor and the new memory controller addresses have to be mapped again in the new design (addresses 0x0c..0x0d and 0x20 to 0x2f in the 353 sys interface).

=== Interrupts ===
Adapt the Theora compressor interrupts to the 353 interrupt vector .

The 353 interrupt vector can handle up to 16 different irq. However, only irq 0 to 7 are used :
'''x353.v'''

assign irq_in= {8'b0, // extra
compressor_done_compress, // 7 - will go high after all data is sent out (reset by compressor)
compressor_done_input, // 6 - will go high after EOT and persist until DCT is enabled (reset by compressor)
dcc_rdy, // 5 - obsolete in 333 - channel3 has 128 more dc coefficients (or some if the compression is finished)
compressor_eot, // 4 - compressor read in the last MCU (predictable time to end of transfer)
sr_sensortrig[2], // 3 - (sync to pclk) - level, reset by writing to sensor triggering command register
xfer_over_irq, // 2 - (sync to pclk) - frame acquisition over
trig_irq, // 1 - (sync to pclk) - external trigger
vacts}; // 0 - (sync to pclk) - frame sync

353 MJPEG compressor triggers irqs 4, 6 and 7. 333 Theora compressor is the source of two irqs :
'''compressor_all.v'''

done, // single-cycle pulse when the compressed frame is sent out (IRQ source).
reset_compress, // reset compressor done interrupt (writing any compressor command)

Adaptation should consist of assigning Theora compressor irq sources to vectors 6 and 7 for example if the MJPEG compressor is to be replaced.

=== DMA FIFOs ===
353 design uses 2 DMA FIFOs between the compressor and the system interface instead of one for the 333 Theora compressor. The two DMA FIFOs have also slight differences between the two design. Maybe a single 333 FIFO should be kept for the final design (?)

=== FPGA -> CPU data out MUX ===
The purpose of this MUX is to route data out from the different FPGA blocks to the system interface and then to the data bus to the CPU. The selection is made with the internal address bus ''ia''.
_
--| \
--| |
--| |
--| |--- iod[31:0] -> to system interface
--| |
--| |
|_/
from system interface -> ia[7:0]__|

'' 333 MUX ''
{|border="1" cellpadding="2"
! Adress range !! ia(5) !! ia(4) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''1''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''1''' || '''0''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''1''' || '''1''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0.. (even)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''0''' || dma_d0[31:0] || DMA 0 data
|-
| '''0x0.. (odd)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''1''' || dma_d1[31:0] || DMA 1 data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''X''' || '''X''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''X''' || '''X''' || dsdo[31:0] || Data out from descriptor memory
|-
| '''0x3..''' || '''0''' || '''1''' || '''1''' || '''X''' || '''X''' || bdo[31:0] || 32-bit data from SDRAM channel3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''X''' || '''0''' || '''X''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''X''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''X''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''X''' || '''X''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''X''' || '''X''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

'' 333 MUX ''
{|border="1" cellpadding="2"
! Address || ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || {24'b0,irqr[7:0]} || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(2) !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''0''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''0''' || '''1''' || '''1''' || MODELREV || Model revision
|-
| '''0x14''' || '''1''' || '''X''' || '''0''' || {8'h0,imgptr[23:0]} || Image pointer in 32-byte chunks
|-
| '''0x15''' || '''1''' || '''X''' || '''1''' || hifreq[31:0] || Accumulated high-freq components
|-
|}

'' 333 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock0
|-
| '''2''' || sr_sda1 || I2C
|-
| '''3''' || sr_scl1 || I2C clock1
|-
| '''4..12''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''17''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''18''' || 1'b0 || 0x0
|-
| '''19''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''20''' || itrig || TRIG input
|-
| '''21..22''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)
, 01 - clock is too late
, 10 - clock is too early
, 11 - OK (some measurements show too late, some - too early)
|-
| '''23''' || dcm_done ||
|-
| '''24''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''25''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''26''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''27''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''28''' || tok_frame_num_wr || Odd/even frame of tokens written
|-
| '''29''' || 1'b0 || 0x0
|-
| '''30''' || debug_out || Debug shift register output
|-
| '''31''' || 'b0 || 0x0
|-
|}

'' 353 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2''' || sr_ch0rdy || Ready to write next page (channel 0) SENSOR->SDRAM
|-
| '''3''' || sr_ch1rdy || Ready to read next page (channel 1) SDRAM->FPN(SENSOR)
|-
| '''4''' || sr_ch2rdy || Ready to read next page (channel 2) SDRAM->DMA
|-
| '''5''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''6''' || sr_wrempty || CPU write buffer empty (valid only in write mode). May reprogram channel3.
|-
| '''7..10''' || sr_nextFrame[3:0] || (level) generated before actual block is filled - needed to be combined with the pulse from buffer control
|-
| '''11..13''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''14''' || dcc_rdy || 128 of DC components from JPEG encoder are available (same as interrupt)
|-
| '''15''' || compressor_done_input || will go high after EOT and persist until DCT is enabled
|-
| '''16''' || compressor_done_compress || will go high after all data is sent out
|-
| '''17''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''19..18''' || dcm_err[1:0] || SDRAM DCM phase error
|-
| '''20''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''21''' || dcm_locked || SDRAM DCM overflow
|-
| '''22''' || dcm_status[0] || SDRAM DCM overflow
|-
| '''24..23''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''25''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''26''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''27''' || sens_dcm_status[0] || Sensor DCM overflow
|-
| '''28''' || clockios_locked || dcm locked
|-
| '''29..30''' || clockios_status[1:0] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''31''' || 1'b0 || 0x0
|-
|}

=== Control register ===
The dcr[31:0] bus is used to control the different blocks according to the control register values. The control register can be directly written by the CPU at the address 0x00.

''333 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0..2''' || Not used ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || iobuf || EXPS (output pin)
|-
| '''12''' || iobuf || EXPS (output pin)
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || i2cpads || scl1 out
|-
| '''20''' || i2cpads || scl1 enable
|-
| '''21''' || i2cpads || sda1 out
|-
| '''22''' || i2cpads || sda1 enable
|-
| '''23''' || Not used ||
|-
| '''24..27''' || clock_pclk || pclk source
|-
| '''28..30''' || Not used ||
|-
| '''31''' || clock_pclk || clk enable
|-
|}

''353 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0''' || Not used ||
|-
| '''1..2''' || compressor, sensorpix, histogram ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || sensorpads || sensor trigger
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || sensorpads || dclkmode
|-
| '''20''' || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || Not used ||
|-
| '''24..25''' || BUFGMUX || pclk source
|-
| '''28..30''' || compressor ||
|-
| '''31''' || clock_pclk ||
|-
|}

=== Others ===
* Looks like Theora compressor requires 90° phase clock that was abandoned in the 353 design.
Using different phases reduces AC component of the current through the power/ground lines of the FPGA by spreading register transitions. Theora has larger core so it may help spreading phases.--[[User:Andrey.filippov|Andrey.filippov]] 13:45, 25 February 2008 (CST)
* ...?

== Software updates ==

* Adapt FPGA definitions ([http://elphel.cvs.sourceforge.net/elphel/elphel353/elphel353/os/linux-2.6-tag--devboard-R2_01-1/arch/cris/arch-v32/drivers/elphel/x353.h?revision=1.8&view=markup&sortdir=down x353.h]) and most likely some other FPGA drivers.
* ...?

These lists of update are obviously incomplete. They need to be more detailed in order to make an exhaustive list of the changes that have to be done.

== 353 Theora new design ==
=== Compressor ===

=== Sensorpix ===

Some changes have to be done in this block to interface the sensor and the memory controller (ch0 and 1).

=== Memory controller ===

{|border="1" cellpadding="2"
! Channel !! Description
|-
| '''0''' || 8/16 bit data from sensor to SDRAM
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor
|-
| '''3''' || PIO read/write of SDRAM data
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63]
|-
| '''7''' || Reading 12-bit pre-tokens from SDRAM in indexed coded order
|-
|}

=== System interface ===

{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm || tune SDRAM clock phase
|-
| '''0x0a''' || da_framesync_dly || write frame sync interrupt delay (in scan lines)
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts || interrupt control
|-
| '''0x20..0x27''' || da_mcontr || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc || real time clock
|-
| '''0x48''' || da_timestamp || write timestamp mode
|-
| '''0x74''' || da_xjta0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync || control of external sync module 0x78 - 0x7b
|-
|}

=== Interrupts ===

{|border="1" cellpadding="2"
! irq_in !! Signal !! Comments
|-
| '''15..8''' || GND || Extra
|-
| '''7''' || compressor_done_compress || single-cycle pulse when the compressed frame is sent out
|-
| '''6''' || compressor_reset_compress || reset compressor done interrupt (writing any compressor command)
|-
| '''5''' || GND || dcc_rdy was tied to GND in the 333 design
|-
| '''4''' || GND || eot irq was tied to GND in the 333 design
|-
| '''3''' || sr_sensortrig[2] || (sync to pclk) - level, reset by writing to sensor triggering command register
|-
| '''2''' || xfer_over_irq || (sync to pclk) - frame acquisition over
|-
| '''1''' || trig_irq || (sync to pclk) - external trigger
|-
| '''0''' || vacts || (sync to pclk) - frame sync
|-
|}

=== DMA FIFOs ===
A single DMA FIFO from the 333 design will be instanciated.

=== FPGA -> CPU data out MUX ===

{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || '''0''' || '''x''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''x''' || '''x''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''x''' || '''0''' || '''x''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''x''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''x''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''x''' || '''x''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''x''' || '''x''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

{|border="1" cellpadding="2"
! Address !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' Status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C data
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2..10''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''11''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''12''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''17..18''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)

, 01 - clock is too late , 10 - clock is too early , 11 - OK (some measurements show too late, some - too early)
|-
| '''19''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''20''' || dcm_locked || SDRAM DCM overflow
|-
| '''21..22''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''23''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''24''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''25''' || clockios_locked || dcm locked
|-
| '''26''' || clockios_status[1] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''27''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''28''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''29''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''30''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''31''' || took_frame_num_wr || Odd/even frame of tokens written
|-
|}

=== Control register ===
{|border="1" cellpadding="2"
! bit # !! Signal || Destination block !! Comments
|-
| '''0''' || || Not used ||
|-
| '''1..2''' || cb_bayer_phase || compressor, sensorpix, histogram ||
|-
| '''3''' || || sensorpads || Inverts idclk phase (Not used)
|-
| '''4''' || cb_fillfactory || sensorpads || fillfactory sensor mode
|-
| '''5''' || cb_dlyhact || sensorpads || delay hact pulse by 1
|-
| '''6''' || cb_zoran || sensorpads || ''cb_zoran''
|-
| '''7''' || cb_skipline || sensorpads || skip first scan line from the sensor
|-
| '''8''' || cb_xt_pol || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || iarst || sensorpads || ''iarst''
|-
| '''10''' || iaro || sensorpads || ''iaro''
|-
| '''11''' || cb_encnvclk || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || cb_sensor_trigger || sensorpads || sensor trigger
|-
| '''13''' || imrst || sensorpads || ''imrst''
|-
| '''14''' || cb_scl0_o || iobuf || XRST (output pin)
|-
| '''15''' || cb_scl0_o || i2cpads || scl0 out
|-
| '''16''' || cb_scl0_en || i2cpads || scl0 enable
|-
| '''17''' || cb_sda0_o || i2cpads || sda0 out
|-
| '''18''' || cb_sda0_en || i2cpads || sda0 enable
|-
| '''19''' || cb_dclkmode || sensorpads || dclkmode
|-
| '''20''' || cb_pxd14 || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || cb_latehact || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || || Not used ||
|-
| '''24..25''' || cb_pclksrc || BUFGMUX || pclk source
|-
| '''28..30''' || || Not used ||
|-
| '''31''' || || Not used ||
|-
|}

=== Others ===

== See also ==

*[http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/ 353 Theora CVS]
*[[Theora]]
*[[FPGA_Development_in_Elphel_cameras|FPGA Development in Elphel cameras]]
*[[Design Ideas|FPGA Theora Encoder for Videoconferencing]]
*[[10353]]

Talk:Porting Theora to 353 cameras

2008-03-10T15:45:50Z

JeremViewsurf:

Talk:Porting Theora to 353 cameras

2008-03-10T15:45:31Z

JeremViewsurf:

Porting Theora to 353 cameras

2008-03-07T10:31:03Z

JeremViewsurf: /* Control register */

Elphel model 333 cameras were able to encode and stream Ogg Theora with 6.3.9 firmware. However, this model is no longer produced by Elphel. The goal of this project is to use the full potential of 353 cameras (larger FPGA, faster CPU) in order to port the Ogg Theora feature on the new hardware. First, the camera should be able to upload small Theora clips via FTP.

Different solutions are possible as previously mentioned in the [[Theora]] page :
* Instantiate both the Theora compressor and the MJPEG compressor in the FPGA since the new Spartan 3E seems to be large enough to handle the two features.
* Replace the existing MJPEG compressor with the Theora compressor and implement software Theora to JPEG conversion if JPEG is needed.
* Replace the existing MJPEG compressor in the 353 camera with the Theora compressor and keep two configuration files on the camera filesystem (one for Theora the other for MJPEG). FPGA code could be changed at run-time according to the needs.

Dealing with the last solution seems to be a good start for this project as the other features mentioned can be added later. In all cases, both FPGA code and software code will need to be adapted.

== Hardware updates ==

=== Compressor ===
Replace the MJPEG compressor in the 353 with the 333 Theora compressor ([http://elphel.cvs.sourceforge.net/elphel/camera333/fpga/x333 333 Theora FPGA code]). Maybe some adaptations need to be done within the Theora compressor itself. However, assuming that the compressor worked in 333 cameras a simple instantiation should suffice.

=== Memory controller ===
Replace the 4-channel memory controller with an 8-channel memory interface as in the 333 model in order to handle Theora specific data.

{|border="1" cellpadding="2"
! Channel !! 333 Theora !! 353
|-
| '''0''' || 8/16 bit data from sensor to SDRAM || Data from the sensor (it can be combined with FPN correction data) to the SDRAM in either 8-bit mode or 16-bit
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module || Reads FPN data from SDRAM (8bit - subtract, 8 bit - scale) and feeds it to FPGA for FPN correction of the data on the way from sensor to SDRAM (through channel 0)
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor || Provides data to JPEG encoder in 16x16x8bit MCUs. It can also provide data directly to CPU through DMA bypassing any compression
|-
| '''3''' || PIO read/write of SDRAM data || Provides bidirectional access from CPU through 8x32 bit window.
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM ||
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM ||
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63] ||
|-
| '''7''' || reading 12-bit pre-tokens from SDRAM in indexed coded order ||
|-
|}

=== Sensor interface ===
''sensorpix'' block must be adapted in order to provide a coherent interface between the memory controller and the sensor (channels 0 and 1)

=== System Interface ===
Adapt the system interface to assure communication between FPGA and its environment.

A feature of the system interface is to establish communication between the system CPU and the different blocks within the FPGA (compressor, memory controller etc). This is done by selecting a block with the address bus ''a[12:0]'' connected to the internal address bus ''ial[7:0]'':

'''x353.v'''
always @ (posedge cwr) begin
a0[7:0]<=ial[7:0]; // may want to change to just ia if ia will be late enough;
wnr0 <= ~irnw;
da_ctl0 <= (ial[7:0]==8'h00); // 0x00 WE to control 32-bit register (1 loc)
da_dmamode0 <= (ial[7:0]==8'h01); // 0x01 select writing to dma_cntr/dma_raw (1 loc)
da_sensormode0 <= (ial[7:0]==8'h02); // 0x02 select writing to sensorpix (1 loc)
...
da_compressor0 <= (ial[7:1]==7'h06); // 0x0c..0x0d - will be farther decoded in the compressor module
...

Since memory controller and compressor are to be replaced these addresses have to be adapted.

''353 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x09''' || da_saturation0 || write color saturation values
|-
| '''0x0a''' || da_framesync_dly0 || write frame sync interrupt delay (in scan lines)
|-
| '''0x0c..0x0d''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x0e''' || da_table_a0 || write tables address
|-
| '''0x0f''' || twr0 || write tables data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts0 || interrupt control
|-
| '''0x20..0x2f''' || da_dswe0 || select reading/writing to mcontr (16 locations)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist0 || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc0 || real time clock
|-
| '''0x48''' || da_timestamp0 || write timestamp mode
|-
| '''0x74''' || da_xjtag0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync0 || control of external sync module 0x78 - 0x7b
|-
|}

''333 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or aftre trigger)
|-
| '''0x06''' || da_interrupts0 || interrupt mask
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x10''' || da_debug || write 0x10 any - load debug shift, read (through cs4) -shift
|-
| '''0x20..0x27''' || da_mcontr0 || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table0 || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
|}

Addresses 0x01,2,3,4,5,6,8 and 0x30 can be kept in the 353 system interface. The interrupt mask address 0x06 in the 333 sys interface is no longer used (353 uses interrupt vectors). The Theora compressor and the new memory controller addresses have to be mapped again in the new design (addresses 0x0c..0x0d and 0x20 to 0x2f in the 353 sys interface).

=== Interrupts ===
Adapt the Theora compressor interrupts to the 353 interrupt vector .

The 353 interrupt vector can handle up to 16 different irq. However, only irq 0 to 7 are used :
'''x353.v'''

assign irq_in= {8'b0, // extra
compressor_done_compress, // 7 - will go high after all data is sent out (reset by compressor)
compressor_done_input, // 6 - will go high after EOT and persist until DCT is enabled (reset by compressor)
dcc_rdy, // 5 - obsolete in 333 - channel3 has 128 more dc coefficients (or some if the compression is finished)
compressor_eot, // 4 - compressor read in the last MCU (predictable time to end of transfer)
sr_sensortrig[2], // 3 - (sync to pclk) - level, reset by writing to sensor triggering command register
xfer_over_irq, // 2 - (sync to pclk) - frame acquisition over
trig_irq, // 1 - (sync to pclk) - external trigger
vacts}; // 0 - (sync to pclk) - frame sync

353 MJPEG compressor triggers irqs 4, 6 and 7. 333 Theora compressor is the source of two irqs :
'''compressor_all.v'''

done, // single-cycle pulse when the compressed frame is sent out (IRQ source).
reset_compress, // reset compressor done interrupt (writing any compressor command)

Adaptation should consist of assigning Theora compressor irq sources to vectors 6 and 7 for example if the MJPEG compressor is to be replaced.

=== DMA FIFOs ===
353 design uses 2 DMA FIFOs between the compressor and the system interface instead of one for the 333 Theora compressor. The two DMA FIFOs have also slight differences between the two design. Maybe a single 333 FIFO should be kept for the final design (?)

=== FPGA -> CPU data out MUX ===
The purpose of this MUX is to route data out from the different FPGA blocks to the system interface and then to the data bus to the CPU. The selection is made with the internal address bus ''ia''.
_
--| \
--| |
--| |
--| |--- iod[31:0] -> to system interface
--| |
--| |
|_/
from system interface -> ia[7:0]__|

'' 333 MUX ''
{|border="1" cellpadding="2"
! Adress range !! ia(5) !! ia(4) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''1''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''1''' || '''0''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''1''' || '''1''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0.. (even)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''0''' || dma_d0[31:0] || DMA 0 data
|-
| '''0x0.. (odd)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''1''' || dma_d1[31:0] || DMA 1 data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''X''' || '''X''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''X''' || '''X''' || dsdo[31:0] || Data out from descriptor memory
|-
| '''0x3..''' || '''0''' || '''1''' || '''1''' || '''X''' || '''X''' || bdo[31:0] || 32-bit data from SDRAM channel3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''X''' || '''0''' || '''X''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''X''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''X''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''X''' || '''X''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''X''' || '''X''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

'' 333 MUX ''
{|border="1" cellpadding="2"
! Address || ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || {24'b0,irqr[7:0]} || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(2) !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''0''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''0''' || '''1''' || '''1''' || MODELREV || Model revision
|-
| '''0x14''' || '''1''' || '''X''' || '''0''' || {8'h0,imgptr[23:0]} || Image pointer in 32-byte chunks
|-
| '''0x15''' || '''1''' || '''X''' || '''1''' || hifreq[31:0] || Accumulated high-freq components
|-
|}

'' 333 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock0
|-
| '''2''' || sr_sda1 || I2C
|-
| '''3''' || sr_scl1 || I2C clock1
|-
| '''4..12''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''17''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''18''' || 1'b0 || 0x0
|-
| '''19''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''20''' || itrig || TRIG input
|-
| '''21..22''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)
, 01 - clock is too late
, 10 - clock is too early
, 11 - OK (some measurements show too late, some - too early)
|-
| '''23''' || dcm_done ||
|-
| '''24''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''25''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''26''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''27''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''28''' || tok_frame_num_wr || Odd/even frame of tokens written
|-
| '''29''' || 1'b0 || 0x0
|-
| '''30''' || debug_out || Debug shift register output
|-
| '''31''' || 'b0 || 0x0
|-
|}

'' 353 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2''' || sr_ch0rdy || Ready to write next page (channel 0) SENSOR->SDRAM
|-
| '''3''' || sr_ch1rdy || Ready to read next page (channel 1) SDRAM->FPN(SENSOR)
|-
| '''4''' || sr_ch2rdy || Ready to read next page (channel 2) SDRAM->DMA
|-
| '''5''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''6''' || sr_wrempty || CPU write buffer empty (valid only in write mode). May reprogram channel3.
|-
| '''7..10''' || sr_nextFrame[3:0] || (level) generated before actual block is filled - needed to be combined with the pulse from buffer control
|-
| '''11..13''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''14''' || dcc_rdy || 128 of DC components from JPEG encoder are available (same as interrupt)
|-
| '''15''' || compressor_done_input || will go high after EOT and persist until DCT is enabled
|-
| '''16''' || compressor_done_compress || will go high after all data is sent out
|-
| '''17''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''19..18''' || dcm_err[1:0] || SDRAM DCM phase error
|-
| '''20''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''21''' || dcm_locked || SDRAM DCM overflow
|-
| '''22''' || dcm_status[0] || SDRAM DCM overflow
|-
| '''24..23''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''25''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''26''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''27''' || sens_dcm_status[0] || Sensor DCM overflow
|-
| '''28''' || clockios_locked || dcm locked
|-
| '''29..30''' || clockios_status[1:0] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''31''' || 1'b0 || 0x0
|-
|}

=== Control register ===
The dcr[31:0] bus is used to control the different blocks according to the control register values. The control register can be directly written by the CPU at the address 0x00.

''333 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0..2''' || Not used ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || iobuf || EXPS (output pin)
|-
| '''12''' || iobuf || EXPS (output pin)
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || i2cpads || scl1 out
|-
| '''20''' || i2cpads || scl1 enable
|-
| '''21''' || i2cpads || sda1 out
|-
| '''22''' || i2cpads || sda1 enable
|-
| '''23''' || Not used ||
|-
| '''24..27''' || clock_pclk || pclk source
|-
| '''28..30''' || Not used ||
|-
| '''31''' || clock_pclk || clk enable
|-
|}

''353 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0''' || Not used ||
|-
| '''1..2''' || compressor, sensorpix, histogram ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || sensorpads || sensor trigger
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || sensorpads || dclkmode
|-
| '''20''' || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || Not used ||
|-
| '''24..25''' || BUFGMUX || pclk source
|-
| '''28..30''' || compressor ||
|-
| '''31''' || clock_pclk ||
|-
|}

=== Others ===
* Looks like Theora compressor requires 90° phase clock that was abandoned in the 353 design.
Using different phases reduces AC component of the current through the power/ground lines of the FPGA by spreading register transitions. Theora has larger core so it may help spreading phases.--[[User:Andrey.filippov|Andrey.filippov]] 13:45, 25 February 2008 (CST)
* ...?

== Software updates ==

* Adapt FPGA definitions ([http://elphel.cvs.sourceforge.net/elphel/elphel353/elphel353/os/linux-2.6-tag--devboard-R2_01-1/arch/cris/arch-v32/drivers/elphel/x353.h?revision=1.8&view=markup&sortdir=down x353.h]) and most likely some other FPGA drivers.
* ...?

These lists of update are obviously incomplete. They need to be more detailed in order to make an exhaustive list of the changes that have to be done.

== 353 Theora new design ==
=== Compressor ===

=== Sensorpix ===

Some changes have to be done in this block to interface the sensor and the memory controller (ch0 and 1).

=== Memory controller ===

{|border="1" cellpadding="2"
! Channel !! Description
|-
| '''0''' || 8/16 bit data from sensor to SDRAM
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor
|-
| '''3''' || PIO read/write of SDRAM data
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63]
|-
| '''7''' || Reading 12-bit pre-tokens from SDRAM in indexed coded order
|-
|}

=== System interface ===

{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm || tune SDRAM clock phase
|-
| '''0x0a''' || da_framesync_dly || write frame sync interrupt delay (in scan lines)
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts || interrupt control
|-
| '''0x20..0x27''' || da_mcontr || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc || real time clock
|-
| '''0x48''' || da_timestamp || write timestamp mode
|-
| '''0x74''' || da_xjta0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync || control of external sync module 0x78 - 0x7b
|-
|}

=== Interrupts ===

{|border="1" cellpadding="2"
! irq_in !! Signal !! Comments
|-
| '''15..8''' || GND || Extra
|-
| '''7''' || compressor_done_compress || single-cycle pulse when the compressed frame is sent out
|-
| '''6''' || compressor_reset_compress || reset compressor done interrupt (writing any compressor command)
|-
| '''5''' || GND || dcc_rdy was tied to GND in the 333 design
|-
| '''4''' || GND || eot irq was tied to GND in the 333 design
|-
| '''3''' || sr_sensortrig[2] || (sync to pclk) - level, reset by writing to sensor triggering command register
|-
| '''2''' || xfer_over_irq || (sync to pclk) - frame acquisition over
|-
| '''1''' || trig_irq || (sync to pclk) - external trigger
|-
| '''0''' || vacts || (sync to pclk) - frame sync
|-
|}

=== DMA FIFOs ===
A single DMA FIFO from the 333 design will be instanciated.

=== FPGA -> CPU data out MUX ===

{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || '''0''' || '''x''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''x''' || '''x''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''x''' || '''0''' || '''x''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''x''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''x''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''x''' || '''x''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''x''' || '''x''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

{|border="1" cellpadding="2"
! Address !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' Status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C data
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2..10''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''11''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''12''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''17..18''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)

, 01 - clock is too late , 10 - clock is too early , 11 - OK (some measurements show too late, some - too early)
|-
| '''19''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''20''' || dcm_locked || SDRAM DCM overflow
|-
| '''21..22''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''23''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''24''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''25''' || clockios_locked || dcm locked
|-
| '''26''' || clockios_status[1] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''27''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''28''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''29''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''30''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''31''' || took_frame_num_wr || Odd/even frame of tokens written
|-
|}

=== Control register ===
{|border="1" cellpadding="2"
! bit # !! Signal || Destination block !! Comments
|-
| '''0''' || || Not used ||
|-
| '''1..2''' || cb_bayer_phase || compressor, sensorpix, histogram ||
|-
| '''3''' || || sensorpads || Inverts idclk phase (Not used)
|-
| '''4''' || cb_fillfactory || sensorpads || fillfactory sensor mode
|-
| '''5''' || cb_dlyhact || sensorpads || delay hact pulse by 1
|-
| '''6''' || cb_zoran || sensorpads || ''cb_zoran''
|-
| '''7''' || cb_skipline || sensorpads || skip first scan line from the sensor
|-
| '''8''' || cb_xt_pol || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || iarst || sensorpads || ''iarst''
|-
| '''10''' || iaro || sensorpads || ''iaro''
|-
| '''11''' || cb_encnvclk || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || cb_sensor_trigger || sensorpads || sensor trigger
|-
| '''13''' || imrst || sensorpads || ''imrst''
|-
| '''14''' || cb_scl0_o || iobuf || XRST (output pin)
|-
| '''15''' || cb_scl0_o || i2cpads || scl0 out
|-
| '''16''' || cb_scl0_en || i2cpads || scl0 enable
|-
| '''17''' || cb_sda0_o || i2cpads || sda0 out
|-
| '''18''' || cb_sda0_en || i2cpads || sda0 enable
|-
| '''19''' || cb_dclkmode || sensorpads || dclkmode
|-
| '''20''' || cb_pxd14 || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || cb_latehact || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || || Not used ||
|-
| '''24..25''' || cb_pclksrc || BUFGMUX || pclk source
|-
| '''28..30''' || || Not used ||
|-
| '''31''' || || Not used ||
|-
|}

=== Others ===

== See also ==

*[[Theora]]
*[[FPGA_Development_in_Elphel_cameras|FPGA Development in Elphel cameras]]
*[[Design Ideas|FPGA Theora Encoder for Videoconferencing]]
*[[10353]]

Porting Theora to 353 cameras

2008-03-06T10:59:52Z

JeremViewsurf: /* System interface */

Elphel model 333 cameras were able to encode and stream Ogg Theora with 6.3.9 firmware. However, this model is no longer produced by Elphel. The goal of this project is to use the full potential of 353 cameras (larger FPGA, faster CPU) in order to port the Ogg Theora feature on the new hardware. First, the camera should be able to upload small Theora clips via FTP.

Different solutions are possible as previously mentioned in the [[Theora]] page :
* Instantiate both the Theora compressor and the MJPEG compressor in the FPGA since the new Spartan 3E seems to be large enough to handle the two features.
* Replace the existing MJPEG compressor with the Theora compressor and implement software Theora to JPEG conversion if JPEG is needed.
* Replace the existing MJPEG compressor in the 353 camera with the Theora compressor and keep two configuration files on the camera filesystem (one for Theora the other for MJPEG). FPGA code could be changed at run-time according to the needs.

Dealing with the last solution seems to be a good start for this project as the other features mentioned can be added later. In all cases, both FPGA code and software code will need to be adapted.

== Hardware updates ==

=== Compressor ===
Replace the MJPEG compressor in the 353 with the 333 Theora compressor ([http://elphel.cvs.sourceforge.net/elphel/camera333/fpga/x333 333 Theora FPGA code]). Maybe some adaptations need to be done within the Theora compressor itself. However, assuming that the compressor worked in 333 cameras a simple instantiation should suffice.

=== Memory controller ===
Replace the 4-channel memory controller with an 8-channel memory interface as in the 333 model in order to handle Theora specific data.

{|border="1" cellpadding="2"
! Channel !! 333 Theora !! 353
|-
| '''0''' || 8/16 bit data from sensor to SDRAM || Data from the sensor (it can be combined with FPN correction data) to the SDRAM in either 8-bit mode or 16-bit
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module || Reads FPN data from SDRAM (8bit - subtract, 8 bit - scale) and feeds it to FPGA for FPN correction of the data on the way from sensor to SDRAM (through channel 0)
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor || Provides data to JPEG encoder in 16x16x8bit MCUs. It can also provide data directly to CPU through DMA bypassing any compression
|-
| '''3''' || PIO read/write of SDRAM data || Provides bidirectional access from CPU through 8x32 bit window.
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM ||
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM ||
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63] ||
|-
| '''7''' || reading 12-bit pre-tokens from SDRAM in indexed coded order ||
|-
|}

=== Sensor interface ===
''sensorpix'' block must be adapted in order to provide a coherent interface between the memory controller and the sensor (channels 0 and 1)

=== System Interface ===
Adapt the system interface to assure communication between FPGA and its environment.

A feature of the system interface is to establish communication between the system CPU and the different blocks within the FPGA (compressor, memory controller etc). This is done by selecting a block with the address bus ''a[12:0]'' connected to the internal address bus ''ial[7:0]'':

'''x353.v'''
always @ (posedge cwr) begin
a0[7:0]<=ial[7:0]; // may want to change to just ia if ia will be late enough;
wnr0 <= ~irnw;
da_ctl0 <= (ial[7:0]==8'h00); // 0x00 WE to control 32-bit register (1 loc)
da_dmamode0 <= (ial[7:0]==8'h01); // 0x01 select writing to dma_cntr/dma_raw (1 loc)
da_sensormode0 <= (ial[7:0]==8'h02); // 0x02 select writing to sensorpix (1 loc)
...
da_compressor0 <= (ial[7:1]==7'h06); // 0x0c..0x0d - will be farther decoded in the compressor module
...

Since memory controller and compressor are to be replaced these addresses have to be adapted.

''353 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x09''' || da_saturation0 || write color saturation values
|-
| '''0x0a''' || da_framesync_dly0 || write frame sync interrupt delay (in scan lines)
|-
| '''0x0c..0x0d''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x0e''' || da_table_a0 || write tables address
|-
| '''0x0f''' || twr0 || write tables data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts0 || interrupt control
|-
| '''0x20..0x2f''' || da_dswe0 || select reading/writing to mcontr (16 locations)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist0 || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc0 || real time clock
|-
| '''0x48''' || da_timestamp0 || write timestamp mode
|-
| '''0x74''' || da_xjtag0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync0 || control of external sync module 0x78 - 0x7b
|-
|}

''333 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or aftre trigger)
|-
| '''0x06''' || da_interrupts0 || interrupt mask
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x10''' || da_debug || write 0x10 any - load debug shift, read (through cs4) -shift
|-
| '''0x20..0x27''' || da_mcontr0 || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table0 || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
|}

Addresses 0x01,2,3,4,5,6,8 and 0x30 can be kept in the 353 system interface. The interrupt mask address 0x06 in the 333 sys interface is no longer used (353 uses interrupt vectors). The Theora compressor and the new memory controller addresses have to be mapped again in the new design (addresses 0x0c..0x0d and 0x20 to 0x2f in the 353 sys interface).

=== Interrupts ===
Adapt the Theora compressor interrupts to the 353 interrupt vector .

The 353 interrupt vector can handle up to 16 different irq. However, only irq 0 to 7 are used :
'''x353.v'''

assign irq_in= {8'b0, // extra
compressor_done_compress, // 7 - will go high after all data is sent out (reset by compressor)
compressor_done_input, // 6 - will go high after EOT and persist until DCT is enabled (reset by compressor)
dcc_rdy, // 5 - obsolete in 333 - channel3 has 128 more dc coefficients (or some if the compression is finished)
compressor_eot, // 4 - compressor read in the last MCU (predictable time to end of transfer)
sr_sensortrig[2], // 3 - (sync to pclk) - level, reset by writing to sensor triggering command register
xfer_over_irq, // 2 - (sync to pclk) - frame acquisition over
trig_irq, // 1 - (sync to pclk) - external trigger
vacts}; // 0 - (sync to pclk) - frame sync

353 MJPEG compressor triggers irqs 4, 6 and 7. 333 Theora compressor is the source of two irqs :
'''compressor_all.v'''

done, // single-cycle pulse when the compressed frame is sent out (IRQ source).
reset_compress, // reset compressor done interrupt (writing any compressor command)

Adaptation should consist of assigning Theora compressor irq sources to vectors 6 and 7 for example if the MJPEG compressor is to be replaced.

=== DMA FIFOs ===
353 design uses 2 DMA FIFOs between the compressor and the system interface instead of one for the 333 Theora compressor. The two DMA FIFOs have also slight differences between the two design. Maybe a single 333 FIFO should be kept for the final design (?)

=== FPGA -> CPU data out MUX ===
The purpose of this MUX is to route data out from the different FPGA blocks to the system interface and then to the data bus to the CPU. The selection is made with the internal address bus ''ia''.
_
--| \
--| |
--| |
--| |--- iod[31:0] -> to system interface
--| |
--| |
|_/
from system interface -> ia[7:0]__|

'' 333 MUX ''
{|border="1" cellpadding="2"
! Adress range !! ia(5) !! ia(4) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''1''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''1''' || '''0''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''1''' || '''1''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0.. (even)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''0''' || dma_d0[31:0] || DMA 0 data
|-
| '''0x0.. (odd)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''1''' || dma_d1[31:0] || DMA 1 data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''X''' || '''X''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''X''' || '''X''' || dsdo[31:0] || Data out from descriptor memory
|-
| '''0x3..''' || '''0''' || '''1''' || '''1''' || '''X''' || '''X''' || bdo[31:0] || 32-bit data from SDRAM channel3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''X''' || '''0''' || '''X''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''X''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''X''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''X''' || '''X''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''X''' || '''X''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

'' 333 MUX ''
{|border="1" cellpadding="2"
! Address || ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || {24'b0,irqr[7:0]} || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(2) !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''0''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''0''' || '''1''' || '''1''' || MODELREV || Model revision
|-
| '''0x14''' || '''1''' || '''X''' || '''0''' || {8'h0,imgptr[23:0]} || Image pointer in 32-byte chunks
|-
| '''0x15''' || '''1''' || '''X''' || '''1''' || hifreq[31:0] || Accumulated high-freq components
|-
|}

'' 333 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock0
|-
| '''2''' || sr_sda1 || I2C
|-
| '''3''' || sr_scl1 || I2C clock1
|-
| '''4..12''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''17''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''18''' || 1'b0 || 0x0
|-
| '''19''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''20''' || itrig || TRIG input
|-
| '''21..22''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)
, 01 - clock is too late
, 10 - clock is too early
, 11 - OK (some measurements show too late, some - too early)
|-
| '''23''' || dcm_done ||
|-
| '''24''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''25''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''26''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''27''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''28''' || tok_frame_num_wr || Odd/even frame of tokens written
|-
| '''29''' || 1'b0 || 0x0
|-
| '''30''' || debug_out || Debug shift register output
|-
| '''31''' || 'b0 || 0x0
|-
|}

'' 353 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2''' || sr_ch0rdy || Ready to write next page (channel 0) SENSOR->SDRAM
|-
| '''3''' || sr_ch1rdy || Ready to read next page (channel 1) SDRAM->FPN(SENSOR)
|-
| '''4''' || sr_ch2rdy || Ready to read next page (channel 2) SDRAM->DMA
|-
| '''5''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''6''' || sr_wrempty || CPU write buffer empty (valid only in write mode). May reprogram channel3.
|-
| '''7..10''' || sr_nextFrame[3:0] || (level) generated before actual block is filled - needed to be combined with the pulse from buffer control
|-
| '''11..13''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''14''' || dcc_rdy || 128 of DC components from JPEG encoder are available (same as interrupt)
|-
| '''15''' || compressor_done_input || will go high after EOT and persist until DCT is enabled
|-
| '''16''' || compressor_done_compress || will go high after all data is sent out
|-
| '''17''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''19..18''' || dcm_err[1:0] || SDRAM DCM phase error
|-
| '''20''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''21''' || dcm_locked || SDRAM DCM overflow
|-
| '''22''' || dcm_status[0] || SDRAM DCM overflow
|-
| '''24..23''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''25''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''26''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''27''' || sens_dcm_status[0] || Sensor DCM overflow
|-
| '''28''' || clockios_locked || dcm locked
|-
| '''29..30''' || clockios_status[1:0] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''31''' || 1'b0 || 0x0
|-
|}

=== Control register ===
The dcr[31:0] bus is used to control the different blocks according to the control register values. The control register can be directly written by the CPU at the address 0x00.

''333 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0..2''' || Not used ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || iobuf || EXPS (output pin)
|-
| '''12''' || iobuf || EXPS (output pin)
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || i2cpads || scl1 out
|-
| '''20''' || i2cpads || scl1 enable
|-
| '''21''' || i2cpads || sda1 out
|-
| '''22''' || i2cpads || sda1 enable
|-
| '''23''' || Not used ||
|-
| '''24..27''' || clock_pclk || pclk source
|-
| '''28..30''' || Not used ||
|-
| '''31''' || clock_pclk || clk enable
|-
|}

''353 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0''' || Not used ||
|-
| '''1..2''' || compressor, sensorpix, histogram ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || sensorpads || sensor trigger
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || sensorpads || dclkmode
|-
| '''20''' || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || Not used ||
|-
| '''24..25''' || BUFGMUX || pclk source
|-
| '''28..30''' || compressor ||
|-
| '''31''' || clock_pclk ||
|-
|}

=== Others ===
* Looks like Theora compressor requires 90° phase clock that was abandoned in the 353 design.
Using different phases reduces AC component of the current through the power/ground lines of the FPGA by spreading register transitions. Theora has larger core so it may help spreading phases.--[[User:Andrey.filippov|Andrey.filippov]] 13:45, 25 February 2008 (CST)
* ...?

== Software updates ==

* Adapt FPGA definitions ([http://elphel.cvs.sourceforge.net/elphel/elphel353/elphel353/os/linux-2.6-tag--devboard-R2_01-1/arch/cris/arch-v32/drivers/elphel/x353.h?revision=1.8&view=markup&sortdir=down x353.h]) and most likely some other FPGA drivers.
* ...?

These lists of update are obviously incomplete. They need to be more detailed in order to make an exhaustive list of the changes that have to be done.

== 353 Theora new design ==
=== Compressor ===

=== Sensorpix ===

Some changes have to be done in this block to interface the sensor and the memory controller (ch0 and 1).

=== Memory controller ===

{|border="1" cellpadding="2"
! Channel !! Description
|-
| '''0''' || 8/16 bit data from sensor to SDRAM
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor
|-
| '''3''' || PIO read/write of SDRAM data
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63]
|-
| '''7''' || Reading 12-bit pre-tokens from SDRAM in indexed coded order
|-
|}

=== System interface ===

{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm || tune SDRAM clock phase
|-
| '''0x0a''' || da_framesync_dly || write frame sync interrupt delay (in scan lines)
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts || interrupt control
|-
| '''0x20..0x27''' || da_mcontr || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc || real time clock
|-
| '''0x48''' || da_timestamp || write timestamp mode
|-
| '''0x74''' || da_xjta0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync || control of external sync module 0x78 - 0x7b
|-
|}

=== Interrupts ===

{|border="1" cellpadding="2"
! irq_in !! Signal !! Comments
|-
| '''15..8''' || GND || Extra
|-
| '''7''' || compressor_done_compress || single-cycle pulse when the compressed frame is sent out
|-
| '''6''' || compressor_reset_compress || reset compressor done interrupt (writing any compressor command)
|-
| '''5''' || GND || dcc_rdy was tied to GND in the 333 design
|-
| '''4''' || GND || eot irq was tied to GND in the 333 design
|-
| '''3''' || sr_sensortrig[2] || (sync to pclk) - level, reset by writing to sensor triggering command register
|-
| '''2''' || xfer_over_irq || (sync to pclk) - frame acquisition over
|-
| '''1''' || trig_irq || (sync to pclk) - external trigger
|-
| '''0''' || vacts || (sync to pclk) - frame sync
|-
|}

=== DMA FIFOs ===
A single DMA FIFO from the 333 design will be instanciated.

=== FPGA -> CPU data out MUX ===

{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || '''0''' || '''x''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''x''' || '''x''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''x''' || '''0''' || '''x''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''x''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''x''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''x''' || '''x''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''x''' || '''x''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

{|border="1" cellpadding="2"
! Address !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' Status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C data
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2..10''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''11''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''12''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''17..18''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)

, 01 - clock is too late , 10 - clock is too early , 11 - OK (some measurements show too late, some - too early)
|-
| '''19''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''20''' || dcm_locked || SDRAM DCM overflow
|-
| '''21..22''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''23''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''24''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''25''' || clockios_locked || dcm locked
|-
| '''26''' || clockios_status[1] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''27''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''28''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''29''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''30''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''31''' || took_frame_num_wr || Odd/even frame of tokens written
|-
|}

=== Control register ===
{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0''' || Not used ||
|-
| '''1..2''' || compressor, sensorpix, histogram ||
|-
| '''3''' || sensorpads || Inverts idclk phase (Not used)
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || sensorpads || sensor trigger
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || sensorpads || dclkmode
|-
| '''20''' || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || Not used ||
|-
| '''24..25''' || BUFGMUX || pclk source
|-
| '''28..30''' || Not used ||
|-
| '''31''' || Not used ||
|-
|}

=== Others ===

== See also ==

*[[Theora]]
*[[FPGA_Development_in_Elphel_cameras|FPGA Development in Elphel cameras]]
*[[Design Ideas|FPGA Theora Encoder for Videoconferencing]]
*[[10353]]

Talk:Porting Theora to 353 cameras

2008-03-06T09:17:57Z

JeremViewsurf:

Talk:Porting Theora to 353 cameras

2008-03-06T09:13:25Z

JeremViewsurf:

Talk:Porting Theora to 353 cameras

2008-03-05T14:57:50Z

JeremViewsurf:

Porting Theora to 353 cameras

2008-03-05T14:23:21Z

JeremViewsurf: /* 353 Theora new design */

Elphel model 333 cameras were able to encode and stream Ogg Theora with 6.3.9 firmware. However, this model is no longer produced by Elphel. The goal of this project is to use the full potential of 353 cameras (larger FPGA, faster CPU) in order to port the Ogg Theora feature on the new hardware. First, the camera should be able to upload small Theora clips via FTP.

Different solutions are possible as previously mentioned in the [[Theora]] page :
* Instantiate both the Theora compressor and the MJPEG compressor in the FPGA since the new Spartan 3E seems to be large enough to handle the two features.
* Replace the existing MJPEG compressor with the Theora compressor and implement software Theora to JPEG conversion if JPEG is needed.
* Replace the existing MJPEG compressor in the 353 camera with the Theora compressor and keep two configuration files on the camera filesystem (one for Theora the other for MJPEG). FPGA code could be changed at run-time according to the needs.

Dealing with the last solution seems to be a good start for this project as the other features mentioned can be added later. In all cases, both FPGA code and software code will need to be adapted.

== Hardware updates ==

=== Compressor ===
Replace the MJPEG compressor in the 353 with the 333 Theora compressor ([http://elphel.cvs.sourceforge.net/elphel/camera333/fpga/x333 333 Theora FPGA code]). Maybe some adaptations need to be done within the Theora compressor itself. However, assuming that the compressor worked in 333 cameras a simple instantiation should suffice.

=== Memory controller ===
Replace the 4-channel memory controller with an 8-channel memory interface as in the 333 model in order to handle Theora specific data.

{|border="1" cellpadding="2"
! Channel !! 333 Theora !! 353
|-
| '''0''' || 8/16 bit data from sensor to SDRAM || Data from the sensor (it can be combined with FPN correction data) to the SDRAM in either 8-bit mode or 16-bit
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module || Reads FPN data from SDRAM (8bit - subtract, 8 bit - scale) and feeds it to FPGA for FPN correction of the data on the way from sensor to SDRAM (through channel 0)
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor || Provides data to JPEG encoder in 16x16x8bit MCUs. It can also provide data directly to CPU through DMA bypassing any compression
|-
| '''3''' || PIO read/write of SDRAM data || Provides bidirectional access from CPU through 8x32 bit window.
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM ||
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM ||
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63] ||
|-
| '''7''' || reading 12-bit pre-tokens from SDRAM in indexed coded order ||
|-
|}

=== Sensor interface ===
''sensorpix'' block must be adapted in order to provide a coherent interface between the memory controller and the sensor (channels 0 and 1)

=== System Interface ===
Adapt the system interface to assure communication between FPGA and its environment.

A feature of the system interface is to establish communication between the system CPU and the different blocks within the FPGA (compressor, memory controller etc). This is done by selecting a block with the address bus ''a[12:0]'' connected to the internal address bus ''ial[7:0]'':

'''x353.v'''
always @ (posedge cwr) begin
a0[7:0]<=ial[7:0]; // may want to change to just ia if ia will be late enough;
wnr0 <= ~irnw;
da_ctl0 <= (ial[7:0]==8'h00); // 0x00 WE to control 32-bit register (1 loc)
da_dmamode0 <= (ial[7:0]==8'h01); // 0x01 select writing to dma_cntr/dma_raw (1 loc)
da_sensormode0 <= (ial[7:0]==8'h02); // 0x02 select writing to sensorpix (1 loc)
...
da_compressor0 <= (ial[7:1]==7'h06); // 0x0c..0x0d - will be farther decoded in the compressor module
...

Since memory controller and compressor are to be replaced these addresses have to be adapted.

''353 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x09''' || da_saturation0 || write color saturation values
|-
| '''0x0a''' || da_framesync_dly0 || write frame sync interrupt delay (in scan lines)
|-
| '''0x0c..0x0d''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x0e''' || da_table_a0 || write tables address
|-
| '''0x0f''' || twr0 || write tables data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts0 || interrupt control
|-
| '''0x20..0x2f''' || da_dswe0 || select reading/writing to mcontr (16 locations)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist0 || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc0 || real time clock
|-
| '''0x48''' || da_timestamp0 || write timestamp mode
|-
| '''0x74''' || da_xjtag0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync0 || control of external sync module 0x78 - 0x7b
|-
|}

''333 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or aftre trigger)
|-
| '''0x06''' || da_interrupts0 || interrupt mask
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x10''' || da_debug || write 0x10 any - load debug shift, read (through cs4) -shift
|-
| '''0x20..0x27''' || da_mcontr0 || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table0 || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
|}

Addresses 0x01,2,3,4,5,6,8 and 0x30 can be kept in the 353 system interface. The interrupt mask address 0x06 in the 333 sys interface is no longer used (353 uses interrupt vectors). The Theora compressor and the new memory controller addresses have to be mapped again in the new design (addresses 0x0c..0x0d and 0x20 to 0x2f in the 353 sys interface).

=== Interrupts ===
Adapt the Theora compressor interrupts to the 353 interrupt vector .

The 353 interrupt vector can handle up to 16 different irq. However, only irq 0 to 7 are used :
'''x353.v'''

assign irq_in= {8'b0, // extra
compressor_done_compress, // 7 - will go high after all data is sent out (reset by compressor)
compressor_done_input, // 6 - will go high after EOT and persist until DCT is enabled (reset by compressor)
dcc_rdy, // 5 - obsolete in 333 - channel3 has 128 more dc coefficients (or some if the compression is finished)
compressor_eot, // 4 - compressor read in the last MCU (predictable time to end of transfer)
sr_sensortrig[2], // 3 - (sync to pclk) - level, reset by writing to sensor triggering command register
xfer_over_irq, // 2 - (sync to pclk) - frame acquisition over
trig_irq, // 1 - (sync to pclk) - external trigger
vacts}; // 0 - (sync to pclk) - frame sync

353 MJPEG compressor triggers irqs 4, 6 and 7. 333 Theora compressor is the source of two irqs :
'''compressor_all.v'''

done, // single-cycle pulse when the compressed frame is sent out (IRQ source).
reset_compress, // reset compressor done interrupt (writing any compressor command)

Adaptation should consist of assigning Theora compressor irq sources to vectors 6 and 7 for example if the MJPEG compressor is to be replaced.

=== DMA FIFOs ===
353 design uses 2 DMA FIFOs between the compressor and the system interface instead of one for the 333 Theora compressor. The two DMA FIFOs have also slight differences between the two design. Maybe a single 333 FIFO should be kept for the final design (?)

=== FPGA -> CPU data out MUX ===
The purpose of this MUX is to route data out from the different FPGA blocks to the system interface and then to the data bus to the CPU. The selection is made with the internal address bus ''ia''.
_
--| \
--| |
--| |
--| |--- iod[31:0] -> to system interface
--| |
--| |
|_/
from system interface -> ia[7:0]__|

'' 333 MUX ''
{|border="1" cellpadding="2"
! Adress range !! ia(5) !! ia(4) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''1''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''1''' || '''0''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''1''' || '''1''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0.. (even)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''0''' || dma_d0[31:0] || DMA 0 data
|-
| '''0x0.. (odd)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''1''' || dma_d1[31:0] || DMA 1 data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''X''' || '''X''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''X''' || '''X''' || dsdo[31:0] || Data out from descriptor memory
|-
| '''0x3..''' || '''0''' || '''1''' || '''1''' || '''X''' || '''X''' || bdo[31:0] || 32-bit data from SDRAM channel3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''X''' || '''0''' || '''X''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''X''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''X''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''X''' || '''X''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''X''' || '''X''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

'' 333 MUX ''
{|border="1" cellpadding="2"
! Address || ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || {24'b0,irqr[7:0]} || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(2) !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''0''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''0''' || '''1''' || '''1''' || MODELREV || Model revision
|-
| '''0x14''' || '''1''' || '''X''' || '''0''' || {8'h0,imgptr[23:0]} || Image pointer in 32-byte chunks
|-
| '''0x15''' || '''1''' || '''X''' || '''1''' || hifreq[31:0] || Accumulated high-freq components
|-
|}

'' 333 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock0
|-
| '''2''' || sr_sda1 || I2C
|-
| '''3''' || sr_scl1 || I2C clock1
|-
| '''4..12''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''17''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''18''' || 1'b0 || 0x0
|-
| '''19''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''20''' || itrig || TRIG input
|-
| '''21..22''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)
, 01 - clock is too late
, 10 - clock is too early
, 11 - OK (some measurements show too late, some - too early)
|-
| '''23''' || dcm_done ||
|-
| '''24''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''25''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''26''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''27''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''28''' || tok_frame_num_wr || Odd/even frame of tokens written
|-
| '''29''' || 1'b0 || 0x0
|-
| '''30''' || debug_out || Debug shift register output
|-
| '''31''' || 'b0 || 0x0
|-
|}

'' 353 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2''' || sr_ch0rdy || Ready to write next page (channel 0) SENSOR->SDRAM
|-
| '''3''' || sr_ch1rdy || Ready to read next page (channel 1) SDRAM->FPN(SENSOR)
|-
| '''4''' || sr_ch2rdy || Ready to read next page (channel 2) SDRAM->DMA
|-
| '''5''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''6''' || sr_wrempty || CPU write buffer empty (valid only in write mode). May reprogram channel3.
|-
| '''7..10''' || sr_nextFrame[3:0] || (level) generated before actual block is filled - needed to be combined with the pulse from buffer control
|-
| '''11..13''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''14''' || dcc_rdy || 128 of DC components from JPEG encoder are available (same as interrupt)
|-
| '''15''' || compressor_done_input || will go high after EOT and persist until DCT is enabled
|-
| '''16''' || compressor_done_compress || will go high after all data is sent out
|-
| '''17''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''19..18''' || dcm_err[1:0] || SDRAM DCM phase error
|-
| '''20''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''21''' || dcm_locked || SDRAM DCM overflow
|-
| '''22''' || dcm_status[0] || SDRAM DCM overflow
|-
| '''24..23''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''25''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''26''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''27''' || sens_dcm_status[0] || Sensor DCM overflow
|-
| '''28''' || clockios_locked || dcm locked
|-
| '''29..30''' || clockios_status[1:0] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''31''' || 1'b0 || 0x0
|-
|}

=== Control register ===
The dcr[31:0] bus is used to control the different blocks according to the control register values. The control register can be directly written by the CPU at the address 0x00.

''333 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0..2''' || Not used ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || iobuf || EXPS (output pin)
|-
| '''12''' || iobuf || EXPS (output pin)
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || i2cpads || scl1 out
|-
| '''20''' || i2cpads || scl1 enable
|-
| '''21''' || i2cpads || sda1 out
|-
| '''22''' || i2cpads || sda1 enable
|-
| '''23''' || Not used ||
|-
| '''24..27''' || clock_pclk || pclk source
|-
| '''28..30''' || Not used ||
|-
| '''31''' || clock_pclk || clk enable
|-
|}

''353 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0''' || Not used ||
|-
| '''1..2''' || compressor, sensorpix, histogram ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || sensorpads || sensor trigger
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || sensorpads || dclkmode
|-
| '''20''' || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || Not used ||
|-
| '''24..25''' || BUFGMUX || pclk source
|-
| '''28..30''' || compressor ||
|-
| '''31''' || clock_pclk ||
|-
|}

=== Others ===
* Looks like Theora compressor requires 90° phase clock that was abandoned in the 353 design.
Using different phases reduces AC component of the current through the power/ground lines of the FPGA by spreading register transitions. Theora has larger core so it may help spreading phases.--[[User:Andrey.filippov|Andrey.filippov]] 13:45, 25 February 2008 (CST)
* ...?

== Software updates ==

* Adapt FPGA definitions ([http://elphel.cvs.sourceforge.net/elphel/elphel353/elphel353/os/linux-2.6-tag--devboard-R2_01-1/arch/cris/arch-v32/drivers/elphel/x353.h?revision=1.8&view=markup&sortdir=down x353.h]) and most likely some other FPGA drivers.
* ...?

These lists of update are obviously incomplete. They need to be more detailed in order to make an exhaustive list of the changes that have to be done.

== 353 Theora new design ==
=== Compressor ===

=== Sensorpix ===

Some changes have to be done in this block to interface the sensor and the memory controller (ch0 and 1).

=== Memory controller ===

{|border="1" cellpadding="2"
! Channel !! Description
|-
| '''0''' || 8/16 bit data from sensor to SDRAM
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor
|-
| '''3''' || PIO read/write of SDRAM data
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63]
|-
| '''7''' || Reading 12-bit pre-tokens from SDRAM in indexed coded order
|-
|}

=== System interface ===

{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x0a''' || da_framesync_dly0 || write frame sync interrupt delay (in scan lines)
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts0 || interrupt control
|-
| '''0x20..0x27''' || da_mcontr0 || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || twr_gamma || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist0 || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc0 || real time clock
|-
| '''0x48''' || da_timestamp0 || write timestamp mode
|-
| '''0x74''' || da_xjtag0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync0 || control of external sync module 0x78 - 0x7b
|-
|}

=== Interrupts ===

{|border="1" cellpadding="2"
! irq_in !! Signal !! Comments
|-
| '''15..8''' || GND || Extra
|-
| '''7''' || compressor_done_compress || single-cycle pulse when the compressed frame is sent out
|-
| '''6''' || compressor_reset_compress || reset compressor done interrupt (writing any compressor command)
|-
| '''5''' || GND || dcc_rdy was tied to GND in the 333 design
|-
| '''4''' || GND || eot irq was tied to GND in the 333 design
|-
| '''3''' || sr_sensortrig[2] || (sync to pclk) - level, reset by writing to sensor triggering command register
|-
| '''2''' || xfer_over_irq || (sync to pclk) - frame acquisition over
|-
| '''1''' || trig_irq || (sync to pclk) - external trigger
|-
| '''0''' || vacts || (sync to pclk) - frame sync
|-
|}

=== DMA FIFOs ===
A single DMA FIFO from the 333 design will be instanciated.

=== FPGA -> CPU data out MUX ===

{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || '''0''' || '''x''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''x''' || '''x''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''x''' || '''0''' || '''x''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''x''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''x''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''x''' || '''x''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''x''' || '''x''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

{|border="1" cellpadding="2"
! Address !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' Status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C data
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2..10''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''11''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''12''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''17..18''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)

, 01 - clock is too late , 10 - clock is too early , 11 - OK (some measurements show too late, some - too early)
|-
| '''19''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''20''' || dcm_locked || SDRAM DCM overflow
|-
| '''21..22''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''23''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''24''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''25''' || clockios_locked || dcm locked
|-
| '''26''' || clockios_status[1] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''27''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''28''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''29''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''30''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''31''' || took_frame_num_wr || Odd/even frame of tokens written
|-
|}

=== Control register ===
{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0''' || Not used ||
|-
| '''1..2''' || compressor, sensorpix, histogram ||
|-
| '''3''' || sensorpads || Inverts idclk phase (Not used)
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || sensorpads || sensor trigger
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || sensorpads || dclkmode
|-
| '''20''' || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || Not used ||
|-
| '''24..25''' || BUFGMUX || pclk source
|-
| '''28..30''' || Not used ||
|-
| '''31''' || Not used ||
|-
|}

=== Others ===

== See also ==

*[[Theora]]
*[[FPGA_Development_in_Elphel_cameras|FPGA Development in Elphel cameras]]
*[[Design Ideas|FPGA Theora Encoder for Videoconferencing]]
*[[10353]]

Porting Theora to 353 cameras

2008-03-05T14:14:27Z

JeremViewsurf: /* Control register */

Elphel model 333 cameras were able to encode and stream Ogg Theora with 6.3.9 firmware. However, this model is no longer produced by Elphel. The goal of this project is to use the full potential of 353 cameras (larger FPGA, faster CPU) in order to port the Ogg Theora feature on the new hardware. First, the camera should be able to upload small Theora clips via FTP.

Different solutions are possible as previously mentioned in the [[Theora]] page :
* Instantiate both the Theora compressor and the MJPEG compressor in the FPGA since the new Spartan 3E seems to be large enough to handle the two features.
* Replace the existing MJPEG compressor with the Theora compressor and implement software Theora to JPEG conversion if JPEG is needed.
* Replace the existing MJPEG compressor in the 353 camera with the Theora compressor and keep two configuration files on the camera filesystem (one for Theora the other for MJPEG). FPGA code could be changed at run-time according to the needs.

Dealing with the last solution seems to be a good start for this project as the other features mentioned can be added later. In all cases, both FPGA code and software code will need to be adapted.

== Hardware updates ==

=== Compressor ===
Replace the MJPEG compressor in the 353 with the 333 Theora compressor ([http://elphel.cvs.sourceforge.net/elphel/camera333/fpga/x333 333 Theora FPGA code]). Maybe some adaptations need to be done within the Theora compressor itself. However, assuming that the compressor worked in 333 cameras a simple instantiation should suffice.

=== Memory controller ===
Replace the 4-channel memory controller with an 8-channel memory interface as in the 333 model in order to handle Theora specific data.

{|border="1" cellpadding="2"
! Channel !! 333 Theora !! 353
|-
| '''0''' || 8/16 bit data from sensor to SDRAM || Data from the sensor (it can be combined with FPN correction data) to the SDRAM in either 8-bit mode or 16-bit
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module || Reads FPN data from SDRAM (8bit - subtract, 8 bit - scale) and feeds it to FPGA for FPN correction of the data on the way from sensor to SDRAM (through channel 0)
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor || Provides data to JPEG encoder in 16x16x8bit MCUs. It can also provide data directly to CPU through DMA bypassing any compression
|-
| '''3''' || PIO read/write of SDRAM data || Provides bidirectional access from CPU through 8x32 bit window.
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM ||
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM ||
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63] ||
|-
| '''7''' || reading 12-bit pre-tokens from SDRAM in indexed coded order ||
|-
|}

=== Sensor interface ===
''sensorpix'' block must be adapted in order to provide a coherent interface between the memory controller and the sensor (channels 0 and 1)

=== System Interface ===
Adapt the system interface to assure communication between FPGA and its environment.

A feature of the system interface is to establish communication between the system CPU and the different blocks within the FPGA (compressor, memory controller etc). This is done by selecting a block with the address bus ''a[12:0]'' connected to the internal address bus ''ial[7:0]'':

'''x353.v'''
always @ (posedge cwr) begin
a0[7:0]<=ial[7:0]; // may want to change to just ia if ia will be late enough;
wnr0 <= ~irnw;
da_ctl0 <= (ial[7:0]==8'h00); // 0x00 WE to control 32-bit register (1 loc)
da_dmamode0 <= (ial[7:0]==8'h01); // 0x01 select writing to dma_cntr/dma_raw (1 loc)
da_sensormode0 <= (ial[7:0]==8'h02); // 0x02 select writing to sensorpix (1 loc)
...
da_compressor0 <= (ial[7:1]==7'h06); // 0x0c..0x0d - will be farther decoded in the compressor module
...

Since memory controller and compressor are to be replaced these addresses have to be adapted.

''353 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x09''' || da_saturation0 || write color saturation values
|-
| '''0x0a''' || da_framesync_dly0 || write frame sync interrupt delay (in scan lines)
|-
| '''0x0c..0x0d''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x0e''' || da_table_a0 || write tables address
|-
| '''0x0f''' || twr0 || write tables data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts0 || interrupt control
|-
| '''0x20..0x2f''' || da_dswe0 || select reading/writing to mcontr (16 locations)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist0 || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc0 || real time clock
|-
| '''0x48''' || da_timestamp0 || write timestamp mode
|-
| '''0x74''' || da_xjtag0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync0 || control of external sync module 0x78 - 0x7b
|-
|}

''333 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or aftre trigger)
|-
| '''0x06''' || da_interrupts0 || interrupt mask
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x10''' || da_debug || write 0x10 any - load debug shift, read (through cs4) -shift
|-
| '''0x20..0x27''' || da_mcontr0 || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table0 || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
|}

Addresses 0x01,2,3,4,5,6,8 and 0x30 can be kept in the 353 system interface. The interrupt mask address 0x06 in the 333 sys interface is no longer used (353 uses interrupt vectors). The Theora compressor and the new memory controller addresses have to be mapped again in the new design (addresses 0x0c..0x0d and 0x20 to 0x2f in the 353 sys interface).

=== Interrupts ===
Adapt the Theora compressor interrupts to the 353 interrupt vector .

The 353 interrupt vector can handle up to 16 different irq. However, only irq 0 to 7 are used :
'''x353.v'''

assign irq_in= {8'b0, // extra
compressor_done_compress, // 7 - will go high after all data is sent out (reset by compressor)
compressor_done_input, // 6 - will go high after EOT and persist until DCT is enabled (reset by compressor)
dcc_rdy, // 5 - obsolete in 333 - channel3 has 128 more dc coefficients (or some if the compression is finished)
compressor_eot, // 4 - compressor read in the last MCU (predictable time to end of transfer)
sr_sensortrig[2], // 3 - (sync to pclk) - level, reset by writing to sensor triggering command register
xfer_over_irq, // 2 - (sync to pclk) - frame acquisition over
trig_irq, // 1 - (sync to pclk) - external trigger
vacts}; // 0 - (sync to pclk) - frame sync

353 MJPEG compressor triggers irqs 4, 6 and 7. 333 Theora compressor is the source of two irqs :
'''compressor_all.v'''

done, // single-cycle pulse when the compressed frame is sent out (IRQ source).
reset_compress, // reset compressor done interrupt (writing any compressor command)

Adaptation should consist of assigning Theora compressor irq sources to vectors 6 and 7 for example if the MJPEG compressor is to be replaced.

=== DMA FIFOs ===
353 design uses 2 DMA FIFOs between the compressor and the system interface instead of one for the 333 Theora compressor. The two DMA FIFOs have also slight differences between the two design. Maybe a single 333 FIFO should be kept for the final design (?)

=== FPGA -> CPU data out MUX ===
The purpose of this MUX is to route data out from the different FPGA blocks to the system interface and then to the data bus to the CPU. The selection is made with the internal address bus ''ia''.
_
--| \
--| |
--| |
--| |--- iod[31:0] -> to system interface
--| |
--| |
|_/
from system interface -> ia[7:0]__|

'' 333 MUX ''
{|border="1" cellpadding="2"
! Adress range !! ia(5) !! ia(4) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''1''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''1''' || '''0''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''1''' || '''1''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0.. (even)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''0''' || dma_d0[31:0] || DMA 0 data
|-
| '''0x0.. (odd)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''1''' || dma_d1[31:0] || DMA 1 data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''X''' || '''X''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''X''' || '''X''' || dsdo[31:0] || Data out from descriptor memory
|-
| '''0x3..''' || '''0''' || '''1''' || '''1''' || '''X''' || '''X''' || bdo[31:0] || 32-bit data from SDRAM channel3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''X''' || '''0''' || '''X''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''X''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''X''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''X''' || '''X''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''X''' || '''X''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

'' 333 MUX ''
{|border="1" cellpadding="2"
! Address || ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || {24'b0,irqr[7:0]} || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(2) !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''0''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''0''' || '''1''' || '''1''' || MODELREV || Model revision
|-
| '''0x14''' || '''1''' || '''X''' || '''0''' || {8'h0,imgptr[23:0]} || Image pointer in 32-byte chunks
|-
| '''0x15''' || '''1''' || '''X''' || '''1''' || hifreq[31:0] || Accumulated high-freq components
|-
|}

'' 333 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock0
|-
| '''2''' || sr_sda1 || I2C
|-
| '''3''' || sr_scl1 || I2C clock1
|-
| '''4..12''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''17''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''18''' || 1'b0 || 0x0
|-
| '''19''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''20''' || itrig || TRIG input
|-
| '''21..22''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)
, 01 - clock is too late
, 10 - clock is too early
, 11 - OK (some measurements show too late, some - too early)
|-
| '''23''' || dcm_done ||
|-
| '''24''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''25''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''26''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''27''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''28''' || tok_frame_num_wr || Odd/even frame of tokens written
|-
| '''29''' || 1'b0 || 0x0
|-
| '''30''' || debug_out || Debug shift register output
|-
| '''31''' || 'b0 || 0x0
|-
|}

'' 353 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2''' || sr_ch0rdy || Ready to write next page (channel 0) SENSOR->SDRAM
|-
| '''3''' || sr_ch1rdy || Ready to read next page (channel 1) SDRAM->FPN(SENSOR)
|-
| '''4''' || sr_ch2rdy || Ready to read next page (channel 2) SDRAM->DMA
|-
| '''5''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''6''' || sr_wrempty || CPU write buffer empty (valid only in write mode). May reprogram channel3.
|-
| '''7..10''' || sr_nextFrame[3:0] || (level) generated before actual block is filled - needed to be combined with the pulse from buffer control
|-
| '''11..13''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''14''' || dcc_rdy || 128 of DC components from JPEG encoder are available (same as interrupt)
|-
| '''15''' || compressor_done_input || will go high after EOT and persist until DCT is enabled
|-
| '''16''' || compressor_done_compress || will go high after all data is sent out
|-
| '''17''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''19..18''' || dcm_err[1:0] || SDRAM DCM phase error
|-
| '''20''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''21''' || dcm_locked || SDRAM DCM overflow
|-
| '''22''' || dcm_status[0] || SDRAM DCM overflow
|-
| '''24..23''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''25''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''26''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''27''' || sens_dcm_status[0] || Sensor DCM overflow
|-
| '''28''' || clockios_locked || dcm locked
|-
| '''29..30''' || clockios_status[1:0] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''31''' || 1'b0 || 0x0
|-
|}

=== Control register ===
The dcr[31:0] bus is used to control the different blocks according to the control register values. The control register can be directly written by the CPU at the address 0x00.

''333 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0..2''' || Not used ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || iobuf || EXPS (output pin)
|-
| '''12''' || iobuf || EXPS (output pin)
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || i2cpads || scl1 out
|-
| '''20''' || i2cpads || scl1 enable
|-
| '''21''' || i2cpads || sda1 out
|-
| '''22''' || i2cpads || sda1 enable
|-
| '''23''' || Not used ||
|-
| '''24..27''' || clock_pclk || pclk source
|-
| '''28..30''' || Not used ||
|-
| '''31''' || clock_pclk || clk enable
|-
|}

''353 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0''' || Not used ||
|-
| '''1..2''' || compressor, sensorpix, histogram ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || sensorpads || sensor trigger
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || sensorpads || dclkmode
|-
| '''20''' || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || Not used ||
|-
| '''24..25''' || BUFGMUX || pclk source
|-
| '''28..30''' || compressor ||
|-
| '''31''' || clock_pclk ||
|-
|}

=== Others ===
* Looks like Theora compressor requires 90° phase clock that was abandoned in the 353 design.
Using different phases reduces AC component of the current through the power/ground lines of the FPGA by spreading register transitions. Theora has larger core so it may help spreading phases.--[[User:Andrey.filippov|Andrey.filippov]] 13:45, 25 February 2008 (CST)
* ...?

== Software updates ==

* Adapt FPGA definitions ([http://elphel.cvs.sourceforge.net/elphel/elphel353/elphel353/os/linux-2.6-tag--devboard-R2_01-1/arch/cris/arch-v32/drivers/elphel/x353.h?revision=1.8&view=markup&sortdir=down x353.h]) and most likely some other FPGA drivers.
* ...?

These lists of update are obviously incomplete. They need to be more detailed in order to make an exhaustive list of the changes that have to be done.

== 353 Theora new design ==
=== Compressor ===
=== Memory controller ===

{|border="1" cellpadding="2"
! Channel !! Description
|-
| '''0''' || 8/16 bit data from sensor to SDRAM
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor
|-
| '''3''' || PIO read/write of SDRAM data
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63]
|-
| '''7''' || Reading 12-bit pre-tokens from SDRAM in indexed coded order
|-
|}

=== System interface ===

{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x0a''' || da_framesync_dly0 || write frame sync interrupt delay (in scan lines)
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts0 || interrupt control
|-
| '''0x20..0x27''' || da_mcontr0 || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || twr_gamma || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist0 || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc0 || real time clock
|-
| '''0x48''' || da_timestamp0 || write timestamp mode
|-
| '''0x74''' || da_xjtag0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync0 || control of external sync module 0x78 - 0x7b
|-
|}

=== Interrupts ===

{|border="1" cellpadding="2"
! irq_in !! Signal !! Comments
|-
| '''15..8''' || GND || Extra
|-
| '''7''' || compressor_done_compress || single-cycle pulse when the compressed frame is sent out
|-
| '''6''' || compressor_reset_compress || reset compressor done interrupt (writing any compressor command)
|-
| '''5''' || GND || dcc_rdy was tied to GND in the 333 design
|-
| '''4''' || GND || eot irq was tied to GND in the 333 design
|-
| '''3''' || sr_sensortrig[2] || (sync to pclk) - level, reset by writing to sensor triggering command register
|-
| '''2''' || xfer_over_irq || (sync to pclk) - frame acquisition over
|-
| '''1''' || trig_irq || (sync to pclk) - external trigger
|-
| '''0''' || vacts || (sync to pclk) - frame sync
|-
|}

=== DMA FIFOs ===
A single DMA FIFO from the 333 design will be instanciated.

=== FPGA -> CPU data out MUX ===

{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || '''0''' || '''x''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''x''' || '''x''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''x''' || '''0''' || '''x''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''x''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''x''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''x''' || '''x''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''x''' || '''x''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

{|border="1" cellpadding="2"
! Address !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' Status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C data
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2..10''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''11''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''12''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''17..18''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)

, 01 - clock is too late , 10 - clock is too early , 11 - OK (some measurements show too late, some - too early)
|-
| '''19''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''20''' || dcm_locked || SDRAM DCM overflow
|-
| '''21..22''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''23''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''24''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''25''' || clockios_locked || dcm locked
|-
| '''26''' || clockios_status[1] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''27''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''28''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''29''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''30''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''31''' || took_frame_num_wr || Odd/even frame of tokens written
|-
|}

=== Control register ===
{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0''' || Not used ||
|-
| '''1..2''' || compressor, sensorpix, histogram ||
|-
| '''3''' || sensorpads || Inverts idclk phase (Not used)
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || sensorpads || sensor trigger
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || sensorpads || dclkmode
|-
| '''20''' || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || Not used ||
|-
| '''24..25''' || BUFGMUX || pclk source
|-
| '''28..30''' || Not used ||
|-
| '''31''' || Not used ||
|-
|}

=== Others ===

== See also ==

*[[Theora]]
*[[FPGA_Development_in_Elphel_cameras|FPGA Development in Elphel cameras]]
*[[Design Ideas|FPGA Theora Encoder for Videoconferencing]]
*[[10353]]

Porting Theora to 353 cameras

2008-03-05T14:12:39Z

JeremViewsurf: /* FPGA -> CPU data out MUX */

Elphel model 333 cameras were able to encode and stream Ogg Theora with 6.3.9 firmware. However, this model is no longer produced by Elphel. The goal of this project is to use the full potential of 353 cameras (larger FPGA, faster CPU) in order to port the Ogg Theora feature on the new hardware. First, the camera should be able to upload small Theora clips via FTP.

Different solutions are possible as previously mentioned in the [[Theora]] page :
* Instantiate both the Theora compressor and the MJPEG compressor in the FPGA since the new Spartan 3E seems to be large enough to handle the two features.
* Replace the existing MJPEG compressor with the Theora compressor and implement software Theora to JPEG conversion if JPEG is needed.
* Replace the existing MJPEG compressor in the 353 camera with the Theora compressor and keep two configuration files on the camera filesystem (one for Theora the other for MJPEG). FPGA code could be changed at run-time according to the needs.

Dealing with the last solution seems to be a good start for this project as the other features mentioned can be added later. In all cases, both FPGA code and software code will need to be adapted.

== Hardware updates ==

=== Compressor ===
Replace the MJPEG compressor in the 353 with the 333 Theora compressor ([http://elphel.cvs.sourceforge.net/elphel/camera333/fpga/x333 333 Theora FPGA code]). Maybe some adaptations need to be done within the Theora compressor itself. However, assuming that the compressor worked in 333 cameras a simple instantiation should suffice.

=== Memory controller ===
Replace the 4-channel memory controller with an 8-channel memory interface as in the 333 model in order to handle Theora specific data.

{|border="1" cellpadding="2"
! Channel !! 333 Theora !! 353
|-
| '''0''' || 8/16 bit data from sensor to SDRAM || Data from the sensor (it can be combined with FPN correction data) to the SDRAM in either 8-bit mode or 16-bit
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module || Reads FPN data from SDRAM (8bit - subtract, 8 bit - scale) and feeds it to FPGA for FPN correction of the data on the way from sensor to SDRAM (through channel 0)
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor || Provides data to JPEG encoder in 16x16x8bit MCUs. It can also provide data directly to CPU through DMA bypassing any compression
|-
| '''3''' || PIO read/write of SDRAM data || Provides bidirectional access from CPU through 8x32 bit window.
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM ||
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM ||
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63] ||
|-
| '''7''' || reading 12-bit pre-tokens from SDRAM in indexed coded order ||
|-
|}

=== Sensor interface ===
''sensorpix'' block must be adapted in order to provide a coherent interface between the memory controller and the sensor (channels 0 and 1)

=== System Interface ===
Adapt the system interface to assure communication between FPGA and its environment.

A feature of the system interface is to establish communication between the system CPU and the different blocks within the FPGA (compressor, memory controller etc). This is done by selecting a block with the address bus ''a[12:0]'' connected to the internal address bus ''ial[7:0]'':

'''x353.v'''
always @ (posedge cwr) begin
a0[7:0]<=ial[7:0]; // may want to change to just ia if ia will be late enough;
wnr0 <= ~irnw;
da_ctl0 <= (ial[7:0]==8'h00); // 0x00 WE to control 32-bit register (1 loc)
da_dmamode0 <= (ial[7:0]==8'h01); // 0x01 select writing to dma_cntr/dma_raw (1 loc)
da_sensormode0 <= (ial[7:0]==8'h02); // 0x02 select writing to sensorpix (1 loc)
...
da_compressor0 <= (ial[7:1]==7'h06); // 0x0c..0x0d - will be farther decoded in the compressor module
...

Since memory controller and compressor are to be replaced these addresses have to be adapted.

''353 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x09''' || da_saturation0 || write color saturation values
|-
| '''0x0a''' || da_framesync_dly0 || write frame sync interrupt delay (in scan lines)
|-
| '''0x0c..0x0d''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x0e''' || da_table_a0 || write tables address
|-
| '''0x0f''' || twr0 || write tables data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts0 || interrupt control
|-
| '''0x20..0x2f''' || da_dswe0 || select reading/writing to mcontr (16 locations)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist0 || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc0 || real time clock
|-
| '''0x48''' || da_timestamp0 || write timestamp mode
|-
| '''0x74''' || da_xjtag0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync0 || control of external sync module 0x78 - 0x7b
|-
|}

''333 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or aftre trigger)
|-
| '''0x06''' || da_interrupts0 || interrupt mask
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x10''' || da_debug || write 0x10 any - load debug shift, read (through cs4) -shift
|-
| '''0x20..0x27''' || da_mcontr0 || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table0 || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
|}

Addresses 0x01,2,3,4,5,6,8 and 0x30 can be kept in the 353 system interface. The interrupt mask address 0x06 in the 333 sys interface is no longer used (353 uses interrupt vectors). The Theora compressor and the new memory controller addresses have to be mapped again in the new design (addresses 0x0c..0x0d and 0x20 to 0x2f in the 353 sys interface).

=== Interrupts ===
Adapt the Theora compressor interrupts to the 353 interrupt vector .

The 353 interrupt vector can handle up to 16 different irq. However, only irq 0 to 7 are used :
'''x353.v'''

assign irq_in= {8'b0, // extra
compressor_done_compress, // 7 - will go high after all data is sent out (reset by compressor)
compressor_done_input, // 6 - will go high after EOT and persist until DCT is enabled (reset by compressor)
dcc_rdy, // 5 - obsolete in 333 - channel3 has 128 more dc coefficients (or some if the compression is finished)
compressor_eot, // 4 - compressor read in the last MCU (predictable time to end of transfer)
sr_sensortrig[2], // 3 - (sync to pclk) - level, reset by writing to sensor triggering command register
xfer_over_irq, // 2 - (sync to pclk) - frame acquisition over
trig_irq, // 1 - (sync to pclk) - external trigger
vacts}; // 0 - (sync to pclk) - frame sync

353 MJPEG compressor triggers irqs 4, 6 and 7. 333 Theora compressor is the source of two irqs :
'''compressor_all.v'''

done, // single-cycle pulse when the compressed frame is sent out (IRQ source).
reset_compress, // reset compressor done interrupt (writing any compressor command)

Adaptation should consist of assigning Theora compressor irq sources to vectors 6 and 7 for example if the MJPEG compressor is to be replaced.

=== DMA FIFOs ===
353 design uses 2 DMA FIFOs between the compressor and the system interface instead of one for the 333 Theora compressor. The two DMA FIFOs have also slight differences between the two design. Maybe a single 333 FIFO should be kept for the final design (?)

=== FPGA -> CPU data out MUX ===
The purpose of this MUX is to route data out from the different FPGA blocks to the system interface and then to the data bus to the CPU. The selection is made with the internal address bus ''ia''.
_
--| \
--| |
--| |
--| |--- iod[31:0] -> to system interface
--| |
--| |
|_/
from system interface -> ia[7:0]__|

'' 333 MUX ''
{|border="1" cellpadding="2"
! Adress range !! ia(5) !! ia(4) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''1''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''1''' || '''0''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''1''' || '''1''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0.. (even)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''0''' || dma_d0[31:0] || DMA 0 data
|-
| '''0x0.. (odd)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''1''' || dma_d1[31:0] || DMA 1 data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''X''' || '''X''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''X''' || '''X''' || dsdo[31:0] || Data out from descriptor memory
|-
| '''0x3..''' || '''0''' || '''1''' || '''1''' || '''X''' || '''X''' || bdo[31:0] || 32-bit data from SDRAM channel3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''X''' || '''0''' || '''X''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''X''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''X''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''X''' || '''X''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''X''' || '''X''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

'' 333 MUX ''
{|border="1" cellpadding="2"
! Address || ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || {24'b0,irqr[7:0]} || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(2) !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''0''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''0''' || '''1''' || '''1''' || MODELREV || Model revision
|-
| '''0x14''' || '''1''' || '''X''' || '''0''' || {8'h0,imgptr[23:0]} || Image pointer in 32-byte chunks
|-
| '''0x15''' || '''1''' || '''X''' || '''1''' || hifreq[31:0] || Accumulated high-freq components
|-
|}

'' 333 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock0
|-
| '''2''' || sr_sda1 || I2C
|-
| '''3''' || sr_scl1 || I2C clock1
|-
| '''4..12''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''17''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''18''' || 1'b0 || 0x0
|-
| '''19''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''20''' || itrig || TRIG input
|-
| '''21..22''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)
, 01 - clock is too late
, 10 - clock is too early
, 11 - OK (some measurements show too late, some - too early)
|-
| '''23''' || dcm_done ||
|-
| '''24''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''25''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''26''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''27''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''28''' || tok_frame_num_wr || Odd/even frame of tokens written
|-
| '''29''' || 1'b0 || 0x0
|-
| '''30''' || debug_out || Debug shift register output
|-
| '''31''' || 'b0 || 0x0
|-
|}

'' 353 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2''' || sr_ch0rdy || Ready to write next page (channel 0) SENSOR->SDRAM
|-
| '''3''' || sr_ch1rdy || Ready to read next page (channel 1) SDRAM->FPN(SENSOR)
|-
| '''4''' || sr_ch2rdy || Ready to read next page (channel 2) SDRAM->DMA
|-
| '''5''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''6''' || sr_wrempty || CPU write buffer empty (valid only in write mode). May reprogram channel3.
|-
| '''7..10''' || sr_nextFrame[3:0] || (level) generated before actual block is filled - needed to be combined with the pulse from buffer control
|-
| '''11..13''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''14''' || dcc_rdy || 128 of DC components from JPEG encoder are available (same as interrupt)
|-
| '''15''' || compressor_done_input || will go high after EOT and persist until DCT is enabled
|-
| '''16''' || compressor_done_compress || will go high after all data is sent out
|-
| '''17''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''19..18''' || dcm_err[1:0] || SDRAM DCM phase error
|-
| '''20''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''21''' || dcm_locked || SDRAM DCM overflow
|-
| '''22''' || dcm_status[0] || SDRAM DCM overflow
|-
| '''24..23''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''25''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''26''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''27''' || sens_dcm_status[0] || Sensor DCM overflow
|-
| '''28''' || clockios_locked || dcm locked
|-
| '''29..30''' || clockios_status[1:0] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''31''' || 1'b0 || 0x0
|-
|}

=== Control register ===
The dcr[31:0] bus is used to control the different blocks according to the control register values. The control register can be directly written by the CPU at the address 0x00.

''333 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0..2''' || Not used ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || iobuf || EXPS (output pin)
|-
| '''12''' || iobuf || EXPS (output pin)
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || i2cpads || scl1 out
|-
| '''20''' || i2cpads || scl1 enable
|-
| '''21''' || i2cpads || sda1 out
|-
| '''22''' || i2cpads || sda1 enable
|-
| '''23''' || Not used ||
|-
| '''24..27''' || clock_pclk || pclk source
|-
| '''28..30''' || Not used ||
|-
| '''31''' || clock_pclk || clk enable
|-
|}

''353 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0''' || Not used ||
|-
| '''1..2''' || compressor, sensorpix, histogram ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || sensorpads || sensor trigger
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || sensorpads || dclkmode
|-
| '''20''' || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || Not used ||
|-
| '''24..25''' || BUFGMUX || pclk source
|-
| '''28..30''' || compressor ||
|-
| '''31''' || clock_pclk ||
|-
|}

=== Others ===
* Looks like Theora compressor requires 90° phase clock that was abandoned in the 353 design.
Using different phases reduces AC component of the current through the power/ground lines of the FPGA by spreading register transitions. Theora has larger core so it may help spreading phases.--[[User:Andrey.filippov|Andrey.filippov]] 13:45, 25 February 2008 (CST)
* ...?

== Software updates ==

* Adapt FPGA definitions ([http://elphel.cvs.sourceforge.net/elphel/elphel353/elphel353/os/linux-2.6-tag--devboard-R2_01-1/arch/cris/arch-v32/drivers/elphel/x353.h?revision=1.8&view=markup&sortdir=down x353.h]) and most likely some other FPGA drivers.
* ...?

These lists of update are obviously incomplete. They need to be more detailed in order to make an exhaustive list of the changes that have to be done.

== 353 Theora new design ==
=== Compressor ===
=== Memory controller ===

{|border="1" cellpadding="2"
! Channel !! Description
|-
| '''0''' || 8/16 bit data from sensor to SDRAM
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor
|-
| '''3''' || PIO read/write of SDRAM data
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63]
|-
| '''7''' || Reading 12-bit pre-tokens from SDRAM in indexed coded order
|-
|}

=== System interface ===

{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x0a''' || da_framesync_dly0 || write frame sync interrupt delay (in scan lines)
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts0 || interrupt control
|-
| '''0x20..0x27''' || da_mcontr0 || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || twr_gamma || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist0 || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc0 || real time clock
|-
| '''0x48''' || da_timestamp0 || write timestamp mode
|-
| '''0x74''' || da_xjtag0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync0 || control of external sync module 0x78 - 0x7b
|-
|}

=== Interrupts ===

{|border="1" cellpadding="2"
! irq_in !! Signal !! Comments
|-
| '''15..8''' || GND || Extra
|-
| '''7''' || compressor_done_compress || single-cycle pulse when the compressed frame is sent out
|-
| '''6''' || compressor_reset_compress || reset compressor done interrupt (writing any compressor command)
|-
| '''5''' || GND || dcc_rdy was tied to GND in the 333 design
|-
| '''4''' || GND || eot irq was tied to GND in the 333 design
|-
| '''3''' || sr_sensortrig[2] || (sync to pclk) - level, reset by writing to sensor triggering command register
|-
| '''2''' || xfer_over_irq || (sync to pclk) - frame acquisition over
|-
| '''1''' || trig_irq || (sync to pclk) - external trigger
|-
| '''0''' || vacts || (sync to pclk) - frame sync
|-
|}

=== DMA FIFOs ===
A single DMA FIFO from the 333 design will be instanciated.

=== FPGA -> CPU data out MUX ===

{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || '''0''' || '''x''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''x''' || '''x''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''0''' || '''0''' || '''1''' || '''x''' || '''x''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''x''' || '''0''' || '''x''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''x''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''x''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''x''' || '''x''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''x''' || '''x''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

{|border="1" cellpadding="2"
! Address !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' Status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C data
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2..10''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''11''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''12''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''17..18''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)

, 01 - clock is too late , 10 - clock is too early , 11 - OK (some measurements show too late, some - too early)
|-
| '''19''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''20''' || dcm_locked || SDRAM DCM overflow
|-
| '''21..22''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''23''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''24''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''25''' || clockios_locked || dcm locked
|-
| '''26''' || clockios_status[1] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''27''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''28''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''29''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''30''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''31''' || took_frame_num_wr || Odd/even frame of tokens written
|-
|}

=== Control register ===

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0''' || Not used ||
|-
| '''1..2''' || compressor, sensorpix, histogram ||
|-
| '''3''' || sensorpads || Inverts idclk phase (Not used)
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || sensorpads || sensor trigger
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || sensorpads || dclkmode
|-
| '''20''' || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || Not used ||
|-
| '''24..25''' || BUFGMUX || pclk source
|-
| '''28..30''' || Not used ||
|-
| '''31''' || Not used ||
|-
|}

=== Others ===

== See also ==

*[[Theora]]
*[[FPGA_Development_in_Elphel_cameras|FPGA Development in Elphel cameras]]
*[[Design Ideas|FPGA Theora Encoder for Videoconferencing]]
*[[10353]]

Porting Theora to 353 cameras

2008-03-05T13:58:44Z

JeremViewsurf: /* Internal registers MUX and status register */

Elphel model 333 cameras were able to encode and stream Ogg Theora with 6.3.9 firmware. However, this model is no longer produced by Elphel. The goal of this project is to use the full potential of 353 cameras (larger FPGA, faster CPU) in order to port the Ogg Theora feature on the new hardware. First, the camera should be able to upload small Theora clips via FTP.

Different solutions are possible as previously mentioned in the [[Theora]] page :
* Instantiate both the Theora compressor and the MJPEG compressor in the FPGA since the new Spartan 3E seems to be large enough to handle the two features.
* Replace the existing MJPEG compressor with the Theora compressor and implement software Theora to JPEG conversion if JPEG is needed.
* Replace the existing MJPEG compressor in the 353 camera with the Theora compressor and keep two configuration files on the camera filesystem (one for Theora the other for MJPEG). FPGA code could be changed at run-time according to the needs.

Dealing with the last solution seems to be a good start for this project as the other features mentioned can be added later. In all cases, both FPGA code and software code will need to be adapted.

== Hardware updates ==

=== Compressor ===
Replace the MJPEG compressor in the 353 with the 333 Theora compressor ([http://elphel.cvs.sourceforge.net/elphel/camera333/fpga/x333 333 Theora FPGA code]). Maybe some adaptations need to be done within the Theora compressor itself. However, assuming that the compressor worked in 333 cameras a simple instantiation should suffice.

=== Memory controller ===
Replace the 4-channel memory controller with an 8-channel memory interface as in the 333 model in order to handle Theora specific data.

{|border="1" cellpadding="2"
! Channel !! 333 Theora !! 353
|-
| '''0''' || 8/16 bit data from sensor to SDRAM || Data from the sensor (it can be combined with FPN correction data) to the SDRAM in either 8-bit mode or 16-bit
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module || Reads FPN data from SDRAM (8bit - subtract, 8 bit - scale) and feeds it to FPGA for FPN correction of the data on the way from sensor to SDRAM (through channel 0)
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor || Provides data to JPEG encoder in 16x16x8bit MCUs. It can also provide data directly to CPU through DMA bypassing any compression
|-
| '''3''' || PIO read/write of SDRAM data || Provides bidirectional access from CPU through 8x32 bit window.
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM ||
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM ||
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63] ||
|-
| '''7''' || reading 12-bit pre-tokens from SDRAM in indexed coded order ||
|-
|}

=== Sensor interface ===
''sensorpix'' block must be adapted in order to provide a coherent interface between the memory controller and the sensor (channels 0 and 1)

=== System Interface ===
Adapt the system interface to assure communication between FPGA and its environment.

A feature of the system interface is to establish communication between the system CPU and the different blocks within the FPGA (compressor, memory controller etc). This is done by selecting a block with the address bus ''a[12:0]'' connected to the internal address bus ''ial[7:0]'':

'''x353.v'''
always @ (posedge cwr) begin
a0[7:0]<=ial[7:0]; // may want to change to just ia if ia will be late enough;
wnr0 <= ~irnw;
da_ctl0 <= (ial[7:0]==8'h00); // 0x00 WE to control 32-bit register (1 loc)
da_dmamode0 <= (ial[7:0]==8'h01); // 0x01 select writing to dma_cntr/dma_raw (1 loc)
da_sensormode0 <= (ial[7:0]==8'h02); // 0x02 select writing to sensorpix (1 loc)
...
da_compressor0 <= (ial[7:1]==7'h06); // 0x0c..0x0d - will be farther decoded in the compressor module
...

Since memory controller and compressor are to be replaced these addresses have to be adapted.

''353 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x09''' || da_saturation0 || write color saturation values
|-
| '''0x0a''' || da_framesync_dly0 || write frame sync interrupt delay (in scan lines)
|-
| '''0x0c..0x0d''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x0e''' || da_table_a0 || write tables address
|-
| '''0x0f''' || twr0 || write tables data
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts0 || interrupt control
|-
| '''0x20..0x2f''' || da_dswe0 || select reading/writing to mcontr (16 locations)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist0 || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc0 || real time clock
|-
| '''0x48''' || da_timestamp0 || write timestamp mode
|-
| '''0x74''' || da_xjtag0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync0 || control of external sync module 0x78 - 0x7b
|-
|}

''333 system interface address table''
{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or aftre trigger)
|-
| '''0x06''' || da_interrupts0 || interrupt mask
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x10''' || da_debug || write 0x10 any - load debug shift, read (through cs4) -shift
|-
| '''0x20..0x27''' || da_mcontr0 || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || da_table0 || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
|}

Addresses 0x01,2,3,4,5,6,8 and 0x30 can be kept in the 353 system interface. The interrupt mask address 0x06 in the 333 sys interface is no longer used (353 uses interrupt vectors). The Theora compressor and the new memory controller addresses have to be mapped again in the new design (addresses 0x0c..0x0d and 0x20 to 0x2f in the 353 sys interface).

=== Interrupts ===
Adapt the Theora compressor interrupts to the 353 interrupt vector .

The 353 interrupt vector can handle up to 16 different irq. However, only irq 0 to 7 are used :
'''x353.v'''

assign irq_in= {8'b0, // extra
compressor_done_compress, // 7 - will go high after all data is sent out (reset by compressor)
compressor_done_input, // 6 - will go high after EOT and persist until DCT is enabled (reset by compressor)
dcc_rdy, // 5 - obsolete in 333 - channel3 has 128 more dc coefficients (or some if the compression is finished)
compressor_eot, // 4 - compressor read in the last MCU (predictable time to end of transfer)
sr_sensortrig[2], // 3 - (sync to pclk) - level, reset by writing to sensor triggering command register
xfer_over_irq, // 2 - (sync to pclk) - frame acquisition over
trig_irq, // 1 - (sync to pclk) - external trigger
vacts}; // 0 - (sync to pclk) - frame sync

353 MJPEG compressor triggers irqs 4, 6 and 7. 333 Theora compressor is the source of two irqs :
'''compressor_all.v'''

done, // single-cycle pulse when the compressed frame is sent out (IRQ source).
reset_compress, // reset compressor done interrupt (writing any compressor command)

Adaptation should consist of assigning Theora compressor irq sources to vectors 6 and 7 for example if the MJPEG compressor is to be replaced.

=== DMA FIFOs ===
353 design uses 2 DMA FIFOs between the compressor and the system interface instead of one for the 333 Theora compressor. The two DMA FIFOs have also slight differences between the two design. Maybe a single 333 FIFO should be kept for the final design (?)

=== FPGA -> CPU data out MUX ===
The purpose of this MUX is to route data out from the different FPGA blocks to the system interface and then to the data bus to the CPU. The selection is made with the internal address bus ''ia''.
_
--| \
--| |
--| |
--| |--- iod[31:0] -> to system interface
--| |
--| |
|_/
from system interface -> ia[7:0]__|

'' 333 MUX ''
{|border="1" cellpadding="2"
! Adress range !! ia(5) !! ia(4) !! iod[31:0] !! Comments
|-
| '''0x0..''' || '''0''' || '''0''' || dma_d[31:0] || DMA data
|-
| '''0x1..''' || '''0''' || '''1''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''1''' || '''0''' || {8'h0,xfer_bytes[23:0]} || Frame length (in bytes)
|-
| '''0x3..''' || '''1''' || '''1''' || bdo[31:0] || 32-bit data from SDRAM channel 3
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| '''0x0.. (even)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''0''' || dma_d0[31:0] || DMA 0 data
|-
| '''0x0.. (odd)''' || '''0''' || '''0''' || '''0''' || '''X''' || '''1''' || dma_d1[31:0] || DMA 1 data
|-
| '''0x1..''' || '''0''' || '''0''' || '''1''' || '''X''' || '''X''' || rd_regs[31:0] || Data from internal registers
|-
| '''0x2..''' || '''0''' || '''1''' || '''0''' || '''X''' || '''X''' || dsdo[31:0] || Data out from descriptor memory
|-
| '''0x3..''' || '''0''' || '''1''' || '''1''' || '''X''' || '''X''' || bdo[31:0] || 32-bit data from SDRAM channel3
|-
| '''0x40..0x43''' || '''1''' || '''0''' || '''X''' || '''0''' || '''X''' || hist_do[31:0] || Histogram data out, actully only [17:0]
|-
| '''0x44''' || '''1''' || '''0''' || '''X''' || '''1''' || '''0''' || {12'h0,pio_usec[19:0]} || usec output from RTC
|-
| '''0x45''' || '''1''' || '''0''' || '''X''' || '''1''' || '''1''' || pio_sec[31:0] || sec output from RTC
|-
| '''0x6..''' || '''1''' || '''1''' || '''0''' || '''X''' || '''X''' || 32'h0 || 0x0000
|-
| '''0x7..''' || '''1''' || '''1''' || '''1''' || '''X''' || '''X''' || {14'b0,xfpgatdo,xfpgastat,4'b0,io_pins[11:0]} || TDO read from an external FPGA / Multiplexed read data from xjtag / Status of 12 i/o pins
|-
|}

=== Internal registers MUX and status register ===

'' 333 MUX ''
{|border="1" cellpadding="2"
! Address || ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || {24'b0,irqr[7:0]} || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' 353 MUX ''
{|border="1" cellpadding="2"
! Address !! ia(2) !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''0''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''0''' || '''1''' || '''1''' || MODELREV || Model revision
|-
| '''0x14''' || '''1''' || '''X''' || '''0''' || {8'h0,imgptr[23:0]} || Image pointer in 32-byte chunks
|-
| '''0x15''' || '''1''' || '''X''' || '''1''' || hifreq[31:0] || Accumulated high-freq components
|-
|}

'' 333 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock0
|-
| '''2''' || sr_sda1 || I2C
|-
| '''3''' || sr_scl1 || I2C clock1
|-
| '''4..12''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''17''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''18''' || 1'b0 || 0x0
|-
| '''19''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''20''' || itrig || TRIG input
|-
| '''21..22''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)
, 01 - clock is too late
, 10 - clock is too early
, 11 - OK (some measurements show too late, some - too early)
|-
| '''23''' || dcm_done ||
|-
| '''24''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''25''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''26''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''27''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''28''' || tok_frame_num_wr || Odd/even frame of tokens written
|-
| '''29''' || 1'b0 || 0x0
|-
| '''30''' || debug_out || Debug shift register output
|-
| '''31''' || 'b0 || 0x0
|-
|}

'' 353 status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C to sensor
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2''' || sr_ch0rdy || Ready to write next page (channel 0) SENSOR->SDRAM
|-
| '''3''' || sr_ch1rdy || Ready to read next page (channel 1) SDRAM->FPN(SENSOR)
|-
| '''4''' || sr_ch2rdy || Ready to read next page (channel 2) SDRAM->DMA
|-
| '''5''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''6''' || sr_wrempty || CPU write buffer empty (valid only in write mode). May reprogram channel3.
|-
| '''7..10''' || sr_nextFrame[3:0] || (level) generated before actual block is filled - needed to be combined with the pulse from buffer control
|-
| '''11..13''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''14''' || dcc_rdy || 128 of DC components from JPEG encoder are available (same as interrupt)
|-
| '''15''' || compressor_done_input || will go high after EOT and persist until DCT is enabled
|-
| '''16''' || compressor_done_compress || will go high after all data is sent out
|-
| '''17''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''19..18''' || dcm_err[1:0] || SDRAM DCM phase error
|-
| '''20''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''21''' || dcm_locked || SDRAM DCM overflow
|-
| '''22''' || dcm_status[0] || SDRAM DCM overflow
|-
| '''24..23''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''25''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''26''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''27''' || sens_dcm_status[0] || Sensor DCM overflow
|-
| '''28''' || clockios_locked || dcm locked
|-
| '''29..30''' || clockios_status[1:0] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''31''' || 1'b0 || 0x0
|-
|}

=== Control register ===
The dcr[31:0] bus is used to control the different blocks according to the control register values. The control register can be directly written by the CPU at the address 0x00.

''333 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0..2''' || Not used ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || iobuf || EXPS (output pin)
|-
| '''12''' || iobuf || EXPS (output pin)
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || i2cpads || scl1 out
|-
| '''20''' || i2cpads || scl1 enable
|-
| '''21''' || i2cpads || sda1 out
|-
| '''22''' || i2cpads || sda1 enable
|-
| '''23''' || Not used ||
|-
| '''24..27''' || clock_pclk || pclk source
|-
| '''28..30''' || Not used ||
|-
| '''31''' || clock_pclk || clk enable
|-
|}

''353 control register''

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0''' || Not used ||
|-
| '''1..2''' || compressor, sensorpix, histogram ||
|-
| '''3''' || sensorpads || Inverts idclk phase
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || sensorpads || sensor trigger
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || sensorpads || dclkmode
|-
| '''20''' || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || Not used ||
|-
| '''24..25''' || BUFGMUX || pclk source
|-
| '''28..30''' || compressor ||
|-
| '''31''' || clock_pclk ||
|-
|}

=== Others ===
* Looks like Theora compressor requires 90° phase clock that was abandoned in the 353 design.
Using different phases reduces AC component of the current through the power/ground lines of the FPGA by spreading register transitions. Theora has larger core so it may help spreading phases.--[[User:Andrey.filippov|Andrey.filippov]] 13:45, 25 February 2008 (CST)
* ...?

== Software updates ==

* Adapt FPGA definitions ([http://elphel.cvs.sourceforge.net/elphel/elphel353/elphel353/os/linux-2.6-tag--devboard-R2_01-1/arch/cris/arch-v32/drivers/elphel/x353.h?revision=1.8&view=markup&sortdir=down x353.h]) and most likely some other FPGA drivers.
* ...?

These lists of update are obviously incomplete. They need to be more detailed in order to make an exhaustive list of the changes that have to be done.

== 353 Theora new design ==
=== Compressor ===
=== Memory controller ===

{|border="1" cellpadding="2"
! Channel !! Description
|-
| '''0''' || 8/16 bit data from sensor to SDRAM
|-
| '''1''' || 16 bit data from SDRAM to FPN correction module
|-
| '''2''' || 20x20 tiles of raw data from SDRAM to the color space converter and compressor
|-
| '''3''' || PIO read/write of SDRAM data
|-
| '''4''' || Writing current (restored) frame as YCbCr 4:2:0 data to SDRAM
|-
| '''5''' || Reading previous frame as YCbCr 4:2:0 data from SDRAM
|-
| '''6''' || Writing 12-bit pre-tokens to SDRAM (in macroblock-scan order, starting with AC[63]
|-
| '''7''' || Reading 12-bit pre-tokens from SDRAM in indexed coded order
|-
|}

=== System interface ===

{|border="1" cellpadding="2"
! Address !! da signal !! Comments
|-
| '''0x00''' || da_ctl0 || WE to control 32-bit register (1 loc)
|-
| '''0x01''' || da_dmamode0 || select writing to dma_cntr/dma_raw (1 loc)
|-
| '''0x02''' || da_sensormode0 || select writing to sensorpix (1 loc)
|-
| '''0x03''' || da_virttrig0 || write virtual trigger threshold
|-
| '''0x04''' || da_sensortrig0 || select writing to sensorpix (1 loc)
|-
| '''0x05''' || da_sensortrig_lines0 || write number of lines to be transferred in a frame (or after trigger)
|-
| '''0x07''' || da_sens_dc0 || write to sensor DCDC converter frequency divider
|-
| '''0x08''' || da_dcm0 || tune SDRAM clock phase
|-
| '''0x0a''' || da_framesync_dly0 || write frame sync interrupt delay (in scan lines)
|-
| '''0x10''' || || Status register
|-
| '''0x1b''' || dcmrst || async signal to restart DCMs (if irnw=0)
|-
| '''0x1c..0x1f''' || da_interrupts0 || interrupt control
|-
| '''0x20..0x27''' || da_mcontr0 || select reading/writing to mcontr (8 locations)
|-
| '''0x28..0x2f''' || da_compressor0 || will be farther decoded in the compressor module
|-
| '''0x2c..0x2d''' || twr_gamma || write gamma tables address (same as in compressor)
|-
| '''0x30''' || da_mem0 || read/write to SDRAM buffer, autoincrement address
|-
| '''0x40..0x43''' || da_hist0 || write/read histogram related data/registers
|-
| '''0x44..0x47''' || da_rtc0 || real time clock
|-
| '''0x48''' || da_timestamp0 || write timestamp mode
|-
| '''0x74''' || da_xjtag0 || write to external (sensor board) JTAG
|-
| '''0x78..0x7b''' || da_extsync0 || control of external sync module 0x78 - 0x7b
|-
|}

=== Interrupts ===

{|border="1" cellpadding="2"
! irq_in !! Signal !! Comments
|-
| '''15..8''' || GND || Extra
|-
| '''7''' || compressor_done_compress || single-cycle pulse when the compressed frame is sent out
|-
| '''6''' || compressor_reset_compress || reset compressor done interrupt (writing any compressor command)
|-
| '''5''' || GND || dcc_rdy was tied to GND in the 333 design
|-
| '''4''' || GND || eot irq was tied to GND in the 333 design
|-
| '''3''' || sr_sensortrig[2] || (sync to pclk) - level, reset by writing to sensor triggering command register
|-
| '''2''' || xfer_over_irq || (sync to pclk) - frame acquisition over
|-
| '''1''' || trig_irq || (sync to pclk) - external trigger
|-
| '''0''' || vacts || (sync to pclk) - frame sync
|-
|}

=== DMA FIFOs ===
A single DMA FIFO from the 333 design will be instanciated.

=== FPGA -> CPU data out MUX ===

{|border="1" cellpadding="2"
! Address !! ia(6) !! ia(5) !! ia(4) !! ia(2) !! ia(0) !! iod[31:0] !! Comments
|-
| || || || || || || ||
|-
|}

=== Internal registers MUX and status register ===

{|border="1" cellpadding="2"
! Address !! ia(1) !! ia(0) !! rd_regs[31:0] !! Comments
|-
| '''0x10''' || '''0''' || '''0''' || Status register || See below
|-
| '''0x11''' || '''0''' || '''1''' || irqr[31:0] || Interrupts
|-
| '''0x12''' || '''1''' || '''0''' || {5'b0,trig_v[10:0],4'b0,trig_h[11:0]} || Trigger phase
|-
| '''0x13''' || '''1''' || '''1''' || MODELREV || Model revision
|-
|}

'' Status register ''
{|border="1" cellpadding="2"
! Bit # !! Signal !! Comments
|-
| '''0''' || sr_sda0 || I2C data
|-
| '''1''' || sr_scl0 || I2C clock
|-
| '''2..10''' || rq_busy[8:0] || Request or busy - per mcontr channel
|-
| '''11''' || sr_memrdy || Ready to r/w next 8x32 page (channel 3) CPU<->SDRAM
|-
| '''12''' || sr_wrempty || CPU write buffer empty (valid only in write mode)
|-
| '''13..15''' || sr_sensortrig[2:0] || x00 - idle, x01 - waiting vacts to start, x10 - waiting for trigger, x11 - frame over ,1xx - frame done (reset by writing command to sensor_trig
|-
| '''16''' || dma_empty || dma output buffer empty and dma is enabled (pessimistic - with delay)
|-
| '''17..18''' || dcm_err[1:0] || 00 - no data (SDRAM reads) since last change (wclk*wcmd)

, 01 - clock is too late , 10 - clock is too early , 11 - OK (some measurements show too late, some - too early)
|-
| '''19''' || dcm_done || SDRAM DCM cmd (inc/dec) done
|-
| '''20''' || dcm_locked || SDRAM DCM overflow
|-
| '''21..22''' || sens_ph_err[1:0] || Sensor DCM phase error
|-
| '''23''' || sens_dcm_done || Sensor DCM cmd (inc/dec/reset) done
|-
| '''24''' || sens_dcm_locked || Sensor DCM overflow
|-
| '''25''' || clockios_locked || dcm locked
|-
| '''26''' || clockios_status[1] || dcm status (bit 1 - dcm clkin stopped)
|-
| '''27''' || sr_pipe_rdy || Will go active with delay to overlap with DMA busy (external)
|-
| '''28''' || sr_pipe_nempty || Compressor pipe not empty (updated with done -> IRQ)
|-
| '''29''' || sr_pipe_full || Compressor pipe has 3 frame compress commands in the input queue/in progress
|-
| '''30''' || en_refresh || Status bit to find out if SDRAM is programmed
|-
| '''31''' || took_frame_num_wr || Odd/even frame of tokens written
|-
|}

=== Control register ===

{|border="1" cellpadding="2"
! bit # !! destination block !! Comments
|-
| '''0''' || Not used ||
|-
| '''1..2''' || compressor, sensorpix, histogram ||
|-
| '''3''' || sensorpads || Inverts idclk phase (Not used)
|-
| '''4''' || sensorpads || fillfactory sensor mode
|-
| '''5''' || sensorpads || delay hact pulse by 1
|-
| '''6''' || sensorpads || ''cb_zoran''
|-
| '''7''' || sensorpads || skip first scan line from the sensor
|-
| '''8''' || sensortrig || external trigger polarity (0: 1->0, 1: 0->1)
|-
| '''9''' || sensorpads || ''iarst''
|-
| '''10''' || sensorpads || ''iaro''
|-
| '''11''' || sensorpads || 0 - use 12-bit sensor data, 1 - use converter output pins
|-
| '''12''' || sensorpads || sensor trigger
|-
| '''13''' || sensorpads || ''imrst''
|-
| '''14''' || iobuf || XRST (output pin)
|-
| '''15''' || i2cpads || scl0 out
|-
| '''16''' || i2cpads || scl0 enable
|-
| '''17''' || i2cpads || sda0 out
|-
| '''18''' || i2cpads || sda0 enable
|-
| '''19''' || sensorpads || dclkmode
|-
| '''20''' || sensorpads || use {vact,hact} as 2 LSB in 14-bit data
|-
| '''21..22''' || sensorpads || register hact, vact, bpf N/4 Tpclk later than data
|-
| '''23''' || Not used ||
|-
| '''24..25''' || BUFGMUX || pclk source
|-
| '''28..30''' || Not used ||
|-
| '''31''' || Not used ||
|-
|}

=== Others ===

== See also ==

*[[Theora]]
*[[FPGA_Development_in_Elphel_cameras|FPGA Development in Elphel cameras]]
*[[Design Ideas|FPGA Theora Encoder for Videoconferencing]]
*[[10353]]