ElphelWiki - User contributions [en]

10359 FPGA Simulation

2008-03-04T22:05:16Z

Okdzhimiev:

The main page for the board is [[10359]].

==Verification==
1. Channel 3 simulation:
* DDR initialization through i2c - done.
* write to DDR - done.
* read from DDR - done.

2. PHASE_SHIFT in DCM is not available currently, because the model had bad constructs, but SDCLK(SDNCLK) can be controlled by "phsel".
For correct writing/reading from DDR in model set phsel="01" (register=0x1008, value=0x00000004).

==Board tests==
1. I2c check
a. It doesn't work when assemled with mcontr and 2 DCMs.
b. Started from the beginning. Works.
c. Checked i2c four read with 1 start. Works fine.
d. Adding DCMs.

2. Check BRAM read/write. All's fine

3. Check DDR read/write. Some problems. not solved

4. Three different boards operate identically: BRAM - ok, DDR - not
a. not marked 359
acquired data is 0x05020306
acquired data is 0x05060706
acquired data is 0x090a0b16
acquired data is 0x0d0e1f16
acquired data is 0x11121316
acquired data is 0x15161716
acquired data is 0x191a1b06
acquired data is 0x1d1e0f26
acquired data is 0x21222326
acquired data is 0x25262726
acquired data is 0x292a2b36
acquired data is 0x2d2e3f36
acquired data is 0x31323336
acquired data is 0x35363736
acquired data is 0x393a3b26
acquired data is 0x3d3e2f46

b. yellow circle marked 359
acquired data is 0x01020306
acquired data is 0x05060706
acquired data is 0x090a0b16
acquired data is 0x0d0e1f16
acquired data is 0x11121316
acquired data is 0x15161716
acquired data is 0x191a1b06
acquired data is 0x1d1e0f26
acquired data is 0x21222326
acquired data is 0x25262726
acquired data is 0x292a2b36
acquired data is 0x2d2e3f36
acquired data is 0x31323336
acquired data is 0x35363736
acquired data is 0x393a3b26
acquired data is 0x3d3e2f46

==Understanding how 353's mcontr works==
02/28/08:
15:04
for mode=0 ( 8 - burst length)
TileX - number of (32x8) blocks
Seq_par(or Param) - the last write block length - (Seq_par)x8
TileY - number of TileX
All this starts from StartAddress

10359 FPGA Simulation

2008-03-04T21:59:36Z

Okdzhimiev:

The main page for the board is [[10359]].

==Verification==
1. Channel 3 simulation:
* DDR initialization through i2c - done.
* write to DDR - done.
* read from DDR - done.

2. PHASE_SHIFT in DCM is not available currently, because the model had bad constructs, but SDCLK(SDNCLK) can be controlled by "phsel".
For correct writing/reading from DDR in model set phsel="01" (register=0x1008, value=0x00000004).

==Board tests==
1. I2c check
a. It doesn't work when assemled with mcontr and 2 DCMs.
b. Started from the beginning. Works.
c. Checked i2c four read with 1 start. Works fine.
d. Adding DCMs.

2. Check BRAM read/write. All's fine

3. Check DDR read/write. Some problems. not solved

4. Three different boards operate identically: BRAM - ok, DDR - not
a. not marked 359
acquired data is 0x05020306
acquired data is 0x05060706
acquired data is 0x090a0b16
acquired data is 0x0d0e1f16
acquired data is 0x11121316
acquired data is 0x15161716
acquired data is 0x191a1b06
acquired data is 0x1d1e0f26
acquired data is 0x21222326
acquired data is 0x25262726
acquired data is 0x292a2b36
acquired data is 0x2d2e3f36
acquired data is 0x31323336
acquired data is 0x35363736
acquired data is 0x393a3b26
acquired data is 0x3d3e2f46

b. yellow circle marked 359
acquired data is 0xfbdfdbf6
acquired data is 0xfe71bff6
acquired data is 0xf7d57f76
acquired data is 0x1d9bfde6
acquired data is 0xffecefe6
acquired data is 0xf7fc7de6
acquired data is 0xbbb63fe6
acquired data is 0xddd6def6
acquired data is 0xbff37ba6
acquired data is 0x3f7ffff6
acquired data is 0xffbcbf76
acquired data is 0xbfffff66
acquired data is 0xfdfd79e6
acquired data is 0x77ef39c6
acquired data is 0xfffbbfd6
acquired data is 0xbb8bfb96

==Understanding how 353's mcontr works==
02/28/08:
15:04
for mode=0 ( 8 - burst length)
TileX - number of (32x8) blocks
Seq_par(or Param) - the last write block length - (Seq_par)x8
TileY - number of TileX
All this starts from StartAddress

10359 FPGA Simulation

2008-03-04T20:54:12Z

Okdzhimiev:

10359 FPGA Simulation

2008-02-28T22:05:25Z

Okdzhimiev:

10359 FPGA Simulation

2008-02-28T22:00:39Z

Okdzhimiev:

10359 FPGA Simulation

2008-02-28T21:59:04Z

Okdzhimiev:

10359 FPGA Simulation

2008-02-19T23:02:33Z

Okdzhimiev:

10359 FPGA Simulation

2008-02-19T22:36:27Z

Okdzhimiev:

10359 FPGA Simulation

2008-02-19T22:16:27Z

Okdzhimiev:

The main page for the board is [[10359]].

==Verification==
1. Channel 3 simulation:
* DDR initialization through i2c - done.
* write to DDR - done.
* read from DDR - done.

2. PHASE_SHIFT in DCM is not available currently, because the model had bad constructs

==Board tests==
1. I2c check
a. It doesn't work when i assemled project with mcontr and 2 DCMs.
b. Started from the beginning. Works.
c. Checked i2c four read with 1 start. Works fine.
d. Adding DCMs.

2. Check BRAM read/write.

3. Check DDR read/write.

10359 FPGA Simulation

2008-02-15T18:23:42Z

Okdzhimiev:

The main page for the board is [[10359]].

==Verification==
1. Channel 3 simulation:
* DDR initialization through i2c - done.
* write to DDR - done.
* read from DDR - done.

==Board tests==
1. I2c check
a. It doesn't work when i assemled project with mcontr and 2 DCMs.
b. Started from the beginning. Works.
c. Checked i2c four read with 1 start. Works fine.
d. Adding DCMs.

2. Check BRAM read/write.

3. Check DDR read/write.

Talk:10359 FPGA Simulation

2008-02-14T01:04:39Z

Okdzhimiev:

1800.02.13.2008: Wrong device type was selected in the project x359. This caused the programming file generation error: that was about differential pin SDNCLK (the pinout is not the same for different packages).

10359 FPGA Simulation

2008-02-14T00:59:10Z

Okdzhimiev:

10359 FPGA Simulation

2008-02-14T00:57:53Z

Okdzhimiev:

10359 FPGA Simulation

2008-02-14T00:57:25Z

Okdzhimiev:

The main page for the board is [[10359]].

==Verification==
1. channel 3 simulation:
* DDR initialization through i2c - done
* write to DDR - done
* read from DDR - done

==Board tests==
1. check BRAM read/write
2. check DDR read/write

10359 FPGA Simulation

2008-02-14T00:54:01Z

Okdzhimiev:

The main page for the board is [[10359]].

1. channel 3 simulation:
* DDR initialization through i2c - done
* write to DDR - done
* read from DDR - done

10359 FPGA Simulation

2008-02-13T01:57:16Z

Okdzhimiev:

The main page for the board is [[10359]].

1. channel 3 simulation:
* DDR initialization through i2c - done
* write to DDR - done
* read from DDR - doing

10359

2008-02-13T01:40:07Z

Okdzhimiev:

==10359==
[[Image:10359top_sm.jpeg|frame|[[Media:10359top.jpeg|10359 board, top view]]]]
[[Image:10359bot_sm.jpeg|frame|[[Media:10359bot.jpeg|10359 board, bottom view]]]]
[[Image:10359bd.png|frame|[[Media:10359sch.pdf|10359 Circuit Diagram]]]]
10359 is an optional multi-function board for [[353|Elplhel Model 353/363 Cameras]]. It can be connected between the [[10353|10353 Processor board]] and a sensor one (up to three sensor boards can be connected)
This board has the same FPGA-DDR SDRAM pair as on the 10353 (Processor) board. It uses just one extra conductor in the flex cable to configure the on-board FPGA, rest of the JTAG programming interface pins share connections with the data signals. This board can fit in the standard camera enclosure (when only one sensor board is used) and does not interfere with the boards that use inter-board connectors (i.e. 10357) - the 10359 is mounted on the other side of the 10353 board.

10359 board can be used in the following applications (as well as other ones):
* Additional custom image processing in the FPGA without the requirement to recompile the main FPGA on the 10353 board and solve possible conflicts with existent functionality.
* multiplex several sensor boards (i.e. "day" - color and "night" - monochrome) to one 10353 camera board.
* simultaneously acquire images from up to 3 sensors, compress them and send out one after another
* extract 3-d information from multiple sensors in real time in FPGA
* use additional sensor(s) to run correlation code (like in optical mice) to track camera orientation to compensate for the effect of [[Electronic_Rolling_Shutter]]
* connect earlier sensor boards (with 3.3V interface) to the 10353 board. Interface voltage for the sensor boards can be switched from 2.5V to 3.3V (all 3 simultaneously)

Connectors:
* 30-pin flex cable connector (J1) for data to/from the [[10353|10353 Processor board]]. It also receives 3.3V power through this connector
* 3 of 30-pin flex cable connectors (J2, J3, J4) for the flex cables to the sensor boards (i.e. [[10338]], [[10347]])

Spartan3E:
*[[10359_FPGA_Simulation|Firmware verification notes]].

10359

2008-02-13T01:38:31Z

Okdzhimiev:

==10359==
[[Image:10359top_sm.jpeg|frame|[[Media:10359top.jpeg|10359 board, top view]]]]
[[Image:10359bot_sm.jpeg|frame|[[Media:10359bot.jpeg|10359 board, bottom view]]]]
[[Image:10359bd.png|frame|[[Media:10359sch.pdf|10359 Circuit Diagram]]]]
10359 is an optional multi-function board for [[353|Elplhel Model 353/363 Cameras]]. It can be connected between the [[10353|10353 Processor board]] and a sensor one (up to three sensor boards can be connected)
This board has the same FPGA-DDR SDRAM pair as on the 10353 (Processor) board. It uses just one extra conductor in the flex cable to configure the on-board FPGA, rest of the JTAG programming interface pins share connections with the data signals. This board can fit in the standard camera enclosure (when only one sensor board is used) and does not interfere with the boards that use inter-board connectors (i.e. 10357) - the 10359 is mounted on the other side of the 10353 board.

10359 board can be used in the following applications (as well as other ones):
* Additional custom image processing in the FPGA without the requirement to recompile the main FPGA on the 10353 board and solve possible conflicts with existent functionality.
* multiplex several sensor boards (i.e. "day" - color and "night" - monochrome) to one 10353 camera board.
* simultaneously acquire images from up to 3 sensors, compress them and send out one after another
* extract 3-d information from multiple sensors in real time in FPGA
* use additional sensor(s) to run correlation code (like in optical mice) to track camera orientation to compensate for the effect of [[Electronic_Rolling_Shutter]]
* connect earlier sensor boards (with 3.3V interface) to the 10353 board. Interface voltage for the sensor boards can be switched from 2.5V to 3.3V (all 3 simultaneously)

Connectors:
* 30-pin flex cable connector (J1) for data to/from the [[10353|10353 Processor board]]. It also receives 3.3V power through this connector
* 3 of 30-pin flex cable connectors (J2, J3, J4) for the flex cables to the sensor boards (i.e. [[10338]], [[10347]])

[[10359_FPGA_Simulation|Firmware verification notes]].

10359 FPGA Simulation

2008-02-13T01:34:46Z

Okdzhimiev:

The main page for the board is [[10359]].

10359 FPGA Simulation

2008-02-13T01:34:22Z

Okdzhimiev:

The main page for board is [[10359]].

FPGA Development in Elphel cameras

2008-02-05T01:11:52Z

Okdzhimiev: /* Installation of the Xilinx ISE WebPACK */

== Introduction ==
Much of the performance and flexibility of the Elphel cameras are provided by the reconfigurable [http://en.wikipedia.org/wiki/Fpga FPGA] chips. FPGA is used on the main camera board (currently it is [[10353]]) and on some of the extension ones ([[10347]], [[10359]], [[10357]]). On the main board the FPGA chip complements CPU to perform video processing and compression - it does this nearly 100 times faster than the CPU alone, but generally it is significantly more difficult to implement some functionality in the FPGA than it can be done in the software. And so the camera (like many other modern devices) combines the strong features of both: FPGA performs computationally intensive but algorithmically relatively simple operations (working with the images on the pixel level, providing image compression) and the CPU is responsible for the higher level functions, interface and overall control of the camera.

Elphel does not make secrets of the FPGA code, all the source code is available under [http://www.gnu.org/licenses/gpl.html GNU GPL v 3.0] license, the same one as used for the camera software. Elphel software distribution (available both on [https://sourceforge.net/projects/elphel Sourceforge project page] and inside each camera file system) includes both binary FPGA image ("bit file") and the source code needed to re-create the FPGA image and/or simulate the design. Also included are the log files generated by the FPGA "compiler" during creation of the provided bit file so you may look inside even if you do not have the necessary FPGA tools, you may also find these files useful to compare with the output that you get from those tools.

==FPGA design flow==
There are two main activities during development of the FPGA code: synthesis and simulation.
* Synthesis (the whole process involves more steps in addition to just strictly "synthesis" itself) is needed to translate the source code into the "executable" and
* Simulation - software emulation of the FPGA functionality. Simulation runs about million times slower than the real thing, but it allows easy analysis of what is going inside the design, provides ability to test and troubleshoot project as a whole or individual modules.

==Software required for FPGA development with Elphel products==
===Software for synthesis===
Elphel cameras use 1200K gates Xilinx [http://www.xilinx.com/products/silicon_solutions/fpgas/spartan_series/spartan3e_fpgas/index.htm Spartan(R) 3e FPGA] (XC3S1200E-5FT256C) that are supported (among others) by free for download (but non-free software) [http://www.xilinx.com/ise/logic_design_prod/webpack.htm ISE WebPACK (R)] tools (registration required for download).

That software package is really good for "compiling" your design into silicon, but the simulator provided with the free for download tools has reduced functionality.
===Software for simulation===
Luckily there are really free (GNU GPL) tools available for simulation and Elphel provides scripts for simulation of the design using these tools. Simulation software we use consists of two parts (that require separate installation), provided are the links to the current (as of January,28 2008) releases:
* [ftp://ftp.icarus.com/pub/eda/verilog/v0.8/verilog-0.8.6.tar.gz Icarus] Verilog simulator and
* [http://home.nc.rr.com/gtkwave/ GTKWave] wave viewer - download: [http://home.nc.rr.com/gtkwave/gtkwave-3.1.4.tar.gz gtkwave-3.1.4.tar.gz], documentation (archived PDF): [http://home.nc.rr.com/gtkwave/gtkwave-doc-3.1.3.tar.gz gtkwave-doc-3.1.3.tar.gz].

Note:''You will still need to download and install [http://www.xilinx.com/ise/logic_design_prod/webpack.htm Xilinx ISE WebPACK (R)] even for simulation only. That package includes Verilog source code library that describes the FPGA device primitives used in the design and the current license does not allow to distribute this library with the design.''

=== Installation of the Xilinx ISE WebPACK ===
To install WebPACK on 64-bit platform 32-bit libraries are needed:
sudo apt-get install ia32-libs ia32-libs-gtk ia32-libs-sdl dpkg-dev

Current versions of Xilinx ISE WebPACK install on Linux rather smoothly (Last time I used WebPACK 9.2 and Kubuntu 7.04) but minor tweaking was needed to launch programs like Timing Analyzer or FPGA Editor. They needed additional package to be installed (don't remember - will put here when find out) and "export DISPLAY=:0" to run correctly (without that ISE "as if" launches those programs, but nothing really happens). I just created a small startup script ''launch_ise.sh'' in the WebPACK installation directory (it was /usr/local/Xilinx92 in my case) with the following content:
#!/bin/sh
cd $(dirname $0)
export DISPLAY=:0
./bin/lin/ise

==Importing Elphel project into Xilinx ISE WebPack==

All the FPGA code for Elphel products is located in the fpga directory of the top installation directory that will be created when you run "./install_elphel" script inside the directory created when you inflate the Elphel software distribution. The project files for the main board ([[10353]]) FPGA is included in the fpga/x3x3 subdirectory.

When you start the ISE WebPack you need to select (from the top menu)"
Project -> Source Control -> Import
And then for the "Project file to import" navigate to the fpga/x3x3 subdirectory of you project and select file x353_import.tcl. For the "Directory to import to" select the same directory (you may just click on "..." button and then on "OK").

That should conclude importing of the project, the x353.ise will be created and you should be able to view/edit project files and run synthesis and implementation tools.

==Simulating 10353 board FPGA with Icarus Verilog and GTKWave==

The first step is to create a library of the Xilinx primitives that can be processed by Icarus Verilog. Unfortunately the library as provided with WebPACK is not immediately compatible with the Icarus Verilog simulator and we do not have a license to distribute the modified for Icarus version of the primitives source code.

The library in question is installed as verilg/src/unisims directory of the top installation directory of Xilinx WebPACK (in my case it is /usr/local/Xilinx92). The [http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/fpga/Makefile?view=markup Makefile] (together with the [http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/fpga/unisims_patch.sh?view=markup unisims_patch.sh] script) in the fpga subdirectory of the Elphel product source tree looks for the Xilinx WebPACK installation on the computer, copies unisims library directory to the fpga directory and patches the files for compatibility with Icarus Verilog. Some modifications (like removing of qualifiers "integer" an "real" after the keywords "parameter" and "localparam" currently not supported by Icarus) are applied to all files, other are specific patches to the files used so far in the project. That means that if you use some other unisims primitives in addition to those already used in the x3x3 project they may also need some patching.

We do not know when any of the files we used will be modified by Xilinx, but we'll try to maintain the patches current. Please notify Elphel developers if you will have incompatibility problems.

If the script can not locate the Xilinx WebPACK installation during software build, the empty "unisims" directory is created under "fpga" and during next runs of "make" it will skip searching for the unisims library. In the case you installed WebPACK after the first run of "make" or have several different versions of WebPACK you may want to navigate to fpga directory and run
make; make install
there (if you did not build Elphel software in the current session you may need to run
. ./init_env
(dot-space-dot-slash-init_env) in the top installation directory (called "elphel353" by default), one level above "fpga" one.

When the unisims library is ready you may try the simulation itself. Navigate to the fpga/x3x3 and run
./[http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/fpga/x3x3/x353_sim.sh?view=markup x353_sim.sh]
As a result you will see some output (it may make sense to set console history to "unlimited"), there should be no errors (at least until until the "Runnig ..."):
removed `x353.lxt'
Using UNISIM library ../unisims
Icarus Verilog version 0.8.6 ($Name: $)
Copyright 1998-2003 Stephen Williams
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
translate: /usr/local/lib/ivl/ivlpp -v -L -D__ICARUS__=1 -f/tmp/ivrlg60f03525 -Dlegacy_model | /usr/local/lib/ivl/ivl -v -C/tmp/ivrlh60f03525 -C/usr/local/lib/ivl/vvp.conf -- -
Icarus Verilog Preprocessor version $Name: $ $State: Exp $
Copyright (c) 1999 Stephen Williams (steve@icarus.com)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
Indexing library: ../unisims
/usr/local/lib/ivl/system.sft: Processing System Function Table file.
Using language generation: SystemVerilog 3.0
PARSING INPUT
... done, 0.08 seconds.
ELABORATING DESIGN
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/PULLDOWN.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/FD.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/FD_1.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/IOBUF.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/FDDRCPE.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/FDCPE.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/FDCPE_1.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/OBUF.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/KEEPER.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/IBUF.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/LD.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/BUFG.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/FDCE.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/LUT4.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/BUF.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/FDE_1.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/FDCE_1.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/IBUFDS.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/IBUFG.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/DCM.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/BUFGMUX.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/OBUFDS.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/SRL16.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/FDE.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/PULLUP.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/RAMB16_S18_S36.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/RAMB16_S9_S36.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/RAMB16_S36_S36.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/SRL16_1.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/MULT18X18.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/RAMB16_S18_S18.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/FDC_1.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/FDC.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/RAMB16_S9_S9.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/RAM16X1D.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/RAMB4_S8_S8.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/ROM32X1.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/MULT18X18SIO.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/LD_1.v
... done, 0.64 seconds.
RUNNING FUNCTORS
-F cprop ...
-F nodangle ...
... 1 iterations deleted 3265 dangling signals and 1210 events. (count=3067)
... 2 iterations deleted 3265 dangling signals and 1210 events. (count=0)
... done, 0.06 seconds.
CODE GENERATION -t dll
... invoking target_design
... done, 0.93 seconds.
STATISTICS
lex_string: add_count=15385 hit_count=41544
Compiling VVP ...
Compile cleanup...
... Linking
... Removing symbol tables
... 347402 functors
9435 table
177 bufif
859 resolv
328086 variable
... 222122 opcodes (5357568 bytes)
... 12573 nets
... 28 memories
... 1290 scopes
... 1.47609 seconds, 57292.0/38120.0/1356.0 KBytes size/rss/shared
Running ...
After the simulation itself will start that generates "x353.lxt" (older version if any of that file was removed at the start of the script). It will take some time to simulate a fraction of a millisecond (as simulation is about a million times slower than the real time) and then the
gtkwave x353.lxt x353_1.sav &
command will be executed that should open the waveform viewer. In addition to the simulation result "x353.lxt" the viewer uses "[http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/fpga/x3x3/x353_1.sav?view=markup x353_1.sav]" - file that contains viewer state with some signals selected and grouped. GTKWave allows you to create, save and read back such files.

You may change the simulation sequence by modifying the file [http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/fpga/x3x3/x353_1.tf?view=markup fpga/x3x3/x353_1.tf] or creating a new simulation sequence and modifying the [http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/fpga/x3x3/x353_sim.sh?view=markup fpga/x3x3/x353_sim.sh] script to use that file instead of the [http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/fpga/x3x3/x353_1.tf?view=markup fpga/x3x3/x353_1.tf].

FPGA Development in Elphel cameras

2008-02-04T22:25:41Z

Okdzhimiev:

== Introduction ==
Much of the performance and flexibility of the Elphel cameras are provided by the reconfigurable [http://en.wikipedia.org/wiki/Fpga FPGA] chips. FPGA is used on the main camera board (currently it is [[10353]]) and on some of the extension ones ([[10347]], [[10359]], [[10357]]). On the main board the FPGA chip complements CPU to perform video processing and compression - it does this nearly 100 times faster than the CPU alone, but generally it is significantly more difficult to implement some functionality in the FPGA than it can be done in the software. And so the camera (like many other modern devices) combines the strong features of both: FPGA performs computationally intensive but algorithmically relatively simple operations (working with the images on the pixel level, providing image compression) and the CPU is responsible for the higher level functions, interface and overall control of the camera.

Elphel does not make secrets of the FPGA code, all the source code is available under [http://www.gnu.org/licenses/gpl.html GNU GPL v 3.0] license, the same one as used for the camera software. Elphel software distribution (available both on [https://sourceforge.net/projects/elphel Sourceforge project page] and inside each camera file system) includes both binary FPGA image ("bit file") and the source code needed to re-create the FPGA image and/or simulate the design. Also included are the log files generated by the FPGA "compiler" during creation of the provided bit file so you may look inside even if you do not have the necessary FPGA tools, you may also find these files useful to compare with the output that you get from those tools.

==FPGA design flow==
There are two main activities during development of the FPGA code: synthesis and simulation.
* Synthesis (the whole process involves more steps in addition to just strictly "synthesis" itself) is needed to translate the source code into the "executable" and
* Simulation - software emulation of the FPGA functionality. Simulation runs about million times slower than the real thing, but it allows easy analysis of what is going inside the design, provides ability to test and troubleshoot project as a whole or individual modules.

==Software required for FPGA development with Elphel products==
===Software for synthesis===
Elphel cameras use 1200K gates Xilinx [http://www.xilinx.com/products/silicon_solutions/fpgas/spartan_series/spartan3e_fpgas/index.htm Spartan(R) 3e FPGA] (XC3S1200E-5FT256C) that are supported (among others) by free for download (but non-free software) [http://www.xilinx.com/ise/logic_design_prod/webpack.htm ISE WebPACK (R)] tools (registration required for download).

That software package is really good for "compiling" your design into silicon, but the simulator provided with the free for download tools has reduced functionality.
===Software for simulation===
Luckily there are really free (GNU GPL) tools available for simulation and Elphel provides scripts for simulation of the design using these tools. Simulation software we use consists of two parts (that require separate installation), provided are the links to the current (as of January,28 2008) releases:
* [ftp://ftp.icarus.com/pub/eda/verilog/v0.8/verilog-0.8.6.tar.gz Icarus] Verilog simulator and
* [http://home.nc.rr.com/gtkwave/ GTKWave] wave viewer - download: [http://home.nc.rr.com/gtkwave/gtkwave-3.1.4.tar.gz gtkwave-3.1.4.tar.gz], documentation (archived PDF): [http://home.nc.rr.com/gtkwave/gtkwave-doc-3.1.3.tar.gz gtkwave-doc-3.1.3.tar.gz].

Note:''You will still need to download and install [http://www.xilinx.com/ise/logic_design_prod/webpack.htm Xilinx ISE WebPACK (R)] even for simulation only. That package includes Verilog source code library that describes the FPGA device primitives used in the design and the current license does not allow to distribute this library with the design.''

=== Installation of the Xilinx ISE WebPACK ===

Current versions of Xilinx ISE WebPACK install on Linux rather smoothly (Last time I used WebPACK 9.2 and Kubuntu 7.04) but minor tweaking was needed to launch programs like Timing Analyzer or FPGA Editor. They needed additional package to be installed (don't remember - will put here when find out) and "export DISPLAY=:0" to run correctly (without that ISE "as if" launches those programs, but nothing really happens). I just created a small startup script ''launch_ise.sh'' in the WebPACK installation directory (it was /usr/local/Xilinx92 in my case) with the following content:
#!/bin/sh
cd $(dirname $0)
export DISPLAY=:0
./bin/lin/ise

==Importing Elphel project into Xilinx ISE WebPack==

All the FPGA code for Elphel products is located in the fpga directory of the top installation directory that will be created when you run "./install_elphel" script inside the directory created when you inflate the Elphel software distribution. The project files for the main board ([[10353]]) FPGA is included in the fpga/x3x3 subdirectory.

When you start the ISE WebPack you need to select (from the top menu)"
Project -> Source Control -> Import
And then for the "Project file to import" navigate to the fpga/x3x3 subdirectory of you project and select file x353_import.tcl. For the "Directory to import to" select the same directory (you may just click on "..." button and then on "OK").

That should conclude importing of the project, the x353.ise will be created and you should be able to view/edit project files and run synthesis and implementation tools.

==Simulating 10353 board FPGA with Icarus Verilog and GTKWave==

The first step is to create a library of the Xilinx primitives that can be processed by Icarus Verilog. Unfortunately the library as provided with WebPACK is not immediately compatible with the Icarus Verilog simulator and we do not have a license to distribute the modified for Icarus version of the primitives source code.

The library in question is installed as verilg/src/unisims directory of the top installation directory of Xilinx WebPACK (in my case it is /usr/local/Xilinx92). The [http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/fpga/Makefile?view=markup Makefile] (together with the [http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/fpga/unisims_patch.sh?view=markup unisims_patch.sh] script) in the fpga subdirectory of the Elphel product source tree looks for the Xilinx WebPACK installation on the computer, copies unisims library directory to the fpga directory and patches the files for compatibility with Icarus Verilog. Some modifications (like removing of qualifiers "integer" an "real" after the keywords "parameter" and "localparam" currently not supported by Icarus) are applied to all files, other are specific patches to the files used so far in the project. That means that if you use some other unisims primitives in addition to those already used in the x3x3 project they may also need some patching.

We do not know when any of the files we used will be modified by Xilinx, but we'll try to maintain the patches current. Please notify Elphel developers if you will have incompatibility problems.

If the script can not locate the Xilinx WebPACK installation during software build, the empty "unisims" directory is created under "fpga" and during next runs of "make" it will skip searching for the unisims library. In the case you installed WebPACK after the first run of "make" or have several different versions of WebPACK you may want to navigate to fpga directory and run
make; make install
there (if you did not build Elphel software in the current session you may need to run
. ./init_env
(dot-space-dot-slash-init_env) in the top installation directory (called "elphel353" by default), one level above "fpga" one.

When the unisims library is ready you may try the simulation itself. Navigate to the fpga/x3x3 and run
./[http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/fpga/x3x3/x353_sim.sh?view=markup x353_sim.sh]
As a result you will see some output (it may make sense to set console history to "unlimited"), there should be no errors (at least until until the "Runnig ..."):
removed `x353.lxt'
Using UNISIM library ../unisims
Icarus Verilog version 0.8.6 ($Name: $)
Copyright 1998-2003 Stephen Williams
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
translate: /usr/local/lib/ivl/ivlpp -v -L -D__ICARUS__=1 -f/tmp/ivrlg60f03525 -Dlegacy_model | /usr/local/lib/ivl/ivl -v -C/tmp/ivrlh60f03525 -C/usr/local/lib/ivl/vvp.conf -- -
Icarus Verilog Preprocessor version $Name: $ $State: Exp $
Copyright (c) 1999 Stephen Williams (steve@icarus.com)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
Indexing library: ../unisims
/usr/local/lib/ivl/system.sft: Processing System Function Table file.
Using language generation: SystemVerilog 3.0
PARSING INPUT
... done, 0.08 seconds.
ELABORATING DESIGN
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/PULLDOWN.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/FD.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/FD_1.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/IOBUF.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/FDDRCPE.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/FDCPE.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/FDCPE_1.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/OBUF.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/KEEPER.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/IBUF.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/LD.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/BUFG.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/FDCE.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/LUT4.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/BUF.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/FDE_1.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/FDCE_1.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/IBUFDS.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/IBUFG.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/DCM.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/BUFGMUX.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/OBUFDS.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/SRL16.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/FDE.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/PULLUP.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/RAMB16_S18_S36.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/RAMB16_S9_S36.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/RAMB16_S36_S36.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/SRL16_1.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/MULT18X18.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/RAMB16_S18_S18.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/FDC_1.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/FDC.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/RAMB16_S9_S9.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/RAM16X1D.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/RAMB4_S8_S8.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/ROM32X1.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/MULT18X18SIO.v
Executing: /usr/local/lib/ivl/ivlpp -D__ICARUS__ -L -Dlegacy_model ../unisims/LD_1.v
... done, 0.64 seconds.
RUNNING FUNCTORS
-F cprop ...
-F nodangle ...
... 1 iterations deleted 3265 dangling signals and 1210 events. (count=3067)
... 2 iterations deleted 3265 dangling signals and 1210 events. (count=0)
... done, 0.06 seconds.
CODE GENERATION -t dll
... invoking target_design
... done, 0.93 seconds.
STATISTICS
lex_string: add_count=15385 hit_count=41544
Compiling VVP ...
Compile cleanup...
... Linking
... Removing symbol tables
... 347402 functors
9435 table
177 bufif
859 resolv
328086 variable
... 222122 opcodes (5357568 bytes)
... 12573 nets
... 28 memories
... 1290 scopes
... 1.47609 seconds, 57292.0/38120.0/1356.0 KBytes size/rss/shared
Running ...
After the simulation itself will start that generates "x353.lxt" (older version if any of that file was removed at the start of the script). It will take some time to simulate a fraction of a millisecond (as simulation is about a million times slower than the real time) and then the
gtkwave x353.lxt x353_1.sav &
command will be executed that should open the waveform viewer. In addition to the simulation result "x353.lxt" the viewer uses "[http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/fpga/x3x3/x353_1.sav?view=markup x353_1.sav]" - file that contains viewer state with some signals selected and grouped. GTKWave allows you to create, save and read back such files.

You may change the simulation sequence by modifying the file [http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/fpga/x3x3/x353_1.tf?view=markup fpga/x3x3/x353_1.tf] or creating a new simulation sequence and modifying the [http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/fpga/x3x3/x353_sim.sh?view=markup fpga/x3x3/x353_sim.sh] script to use that file instead of the [http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/fpga/x3x3/x353_1.tf?view=markup fpga/x3x3/x353_1.tf].