10342 - Revision history

Andrey.filippov: /* 10342 */

2010-12-09T20:49:29Z

10342

← Older revision		Revision as of 20:49, 9 December 2010
Line 9:		Line 9:
	* high-current amplifiers for CCD vertical phase drivers. These signals are multi-level, they are generated by a DAC on the [[10347\|10347 board]] and then amplified on this board.		* high-current amplifiers for CCD vertical phase drivers. These signals are multi-level, they are generated by a DAC on the [[10347\|10347 board]] and then amplified on this board.
	* fast high-current drivers for horizontal phase signals - the AC component is generated by the switches with regulated input voltage, DC shift is added to it (for some signals - to the high level, for others - to the lower level) by the programmable bias voltage generator		* fast high-current drivers for horizontal phase signals - the AC component is generated by the switches with regulated input voltage, DC shift is added to it (for some signals - to the high level, for others - to the lower level) by the programmable bias voltage generator
	* bias voltage generator is used to provide DC bias for horizontal phase signals and the levels for DC signals required ~~fro~~ CCD operation. It uses multi-channel serial DAC (programmed by the signals generated by the FPGA on the [[10347\|10347 board]] and operational amplifiers to provide required output voltage range for each signal.		* bias voltage generator is used to provide DC bias for horizontal phase signals and the levels for DC signals required for CCD operation. It uses multi-channel serial DAC (programmed by the signals generated by the FPGA on the [[10347\|10347 board]] and operational amplifiers to provide required output voltage range for each signal.
	* substrate (erase) pulse generator provides a high voltage (>40V) pulse to erase pixels before the exposure		* substrate (erase) pulse generator provides a high voltage (>40V) pulse to erase pixels before the exposure
	Connectors:		Connectors:
	* 10342 board has a single 40-pin connector (J5) in the middle of the board that links it to the [[10353#10347\|10347 board]]		* 10342 board has a single 40-pin connector (J5) in the middle of the board that links it to the [[10353#10347\|10347 board]]

Andrey.filippov: /* 10342 */

2010-12-09T16:12:09Z

10342

← Older revision		Revision as of 16:12, 9 December 2010
Line 2:		Line 2:
	[[Image:10342top_sm.jpeg\|frame\|[[Media:10342top.jpeg\|10342 board, top view]]]]		[[Image:10342top_sm.jpeg\|frame\|[[Media:10342top.jpeg\|10342 board, top view]]]]
	[[Image:10342bot_sm.jpeg\|frame\|[[Media:10342bot.jpeg\|10342 board, bottom view]]]]		[[Image:10342bot_sm.jpeg\|frame\|[[Media:10342bot.jpeg\|10342 board, bottom view]]]]
	[[Image:10342bd.png\|frame\|[[Media:10342sch.pdf\|10342 Circuit Diagram]]]]		[[Image:10342bd.png\|frame\|[[Media:10342sch.pdf\|10342 Circuit Diagram, Parts List, PCB layout ]]]]
	10342 CCD Interface Board is a part of [[353\|Elplhel Model 353/363 Camera]]. It is designed to work together with the CCD Control Board ([[10353#10347\|10347]]), both controlled by the [[10353\|10353 processor board]]. This board is built around 11 Megapixel interline Kodak KAI-11002 CCD image sensor.		10342 CCD Interface Board is a part of [[353\|Elplhel Model 353/363 Camera]]. It is designed to work together with the CCD Control Board ([[10353#10347\|10347]]), both controlled by the [[10353\|10353 processor board]]. This board is built around 11 Megapixel interline Kodak KAI-11002 CCD image sensor.
	This board include:		This board include:

Andrey.filippov at 14:00, 11 April 2007

2007-04-11T14:00:07Z

← Older revision		Revision as of 14:00, 11 April 2007
Line 3:		Line 3:
	[[Image:10342bot_sm.jpeg\|frame\|[[Media:10342bot.jpeg\|10342 board, bottom view]]]]		[[Image:10342bot_sm.jpeg\|frame\|[[Media:10342bot.jpeg\|10342 board, bottom view]]]]
	[[Image:10342bd.png\|frame\|[[Media:10342sch.pdf\|10342 Circuit Diagram]]]]		[[Image:10342bd.png\|frame\|[[Media:10342sch.pdf\|10342 Circuit Diagram]]]]
	10342 CCD Interface Board is a part of [[353\|Elplhel Model 353/363 Camera]]. It is designed to work together with the CCD Control Board (10347), both controlled by the [[10353\|10353 processor board]]. This board is built around 11 Megapixel interline Kodak KAI-11002 CCD image sensor.		10342 CCD Interface Board is a part of [[353\|Elplhel Model 353/363 Camera]]. It is designed to work together with the CCD Control Board ([[10353#10347\|10347]]), both controlled by the [[10353\|10353 processor board]]. This board is built around 11 Megapixel interline Kodak KAI-11002 CCD image sensor.
	This board include:		This board include:
	* pin sockets for the KAI-11002 CCD image sensor (to facilitate sensor replacement)		* pin sockets for the KAI-11002 CCD image sensor (to facilitate sensor replacement)
	* a pair of pre-amplifiers of the CCD output signals		* a pair of pre-amplifiers of the CCD output signals
	* high-current amplifiers for CCD vertical phase drivers. These signals are multi-level, they are generated by a DAC on the [[~~10353#~~10347\|10347 board]] and then amplified on this board.		* high-current amplifiers for CCD vertical phase drivers. These signals are multi-level, they are generated by a DAC on the [[10347\|10347 board]] and then amplified on this board.
	* fast high-current drivers for horizontal phase signals - the AC component is generated by the switches with regulated input voltage, DC shift is added to it (for some signals - to the high level, for others - to the lower level) by the programmable bias voltage generator		* fast high-current drivers for horizontal phase signals - the AC component is generated by the switches with regulated input voltage, DC shift is added to it (for some signals - to the high level, for others - to the lower level) by the programmable bias voltage generator
	* bias voltage generator is used to provide DC bias for horizontal phase signals and the levels for DC signals required fro CCD operation. It uses multi-channel serial DAC (programmed by the signals generated by the FPGA on the [[~~10353#~~10347\|10347 board]] and operational amplifiers to provide required output voltage range for each signal.		* bias voltage generator is used to provide DC bias for horizontal phase signals and the levels for DC signals required fro CCD operation. It uses multi-channel serial DAC (programmed by the signals generated by the FPGA on the [[10347\|10347 board]] and operational amplifiers to provide required output voltage range for each signal.
	* substrate (erase) pulse generator provides a high voltage (>40V) pulse to erase pixels before the exposure		* substrate (erase) pulse generator provides a high voltage (>40V) pulse to erase pixels before the exposure
	Connectors:		Connectors:
	* 10342 board has a single 40-pin connector (J5) in the middle of the board that links it to the [[10353#10347\|10347 board]]		* 10342 board has a single 40-pin connector (J5) in the middle of the board that links it to the [[10353#10347\|10347 board]]

Andrey.filippov at 13:58, 11 April 2007

2007-04-11T13:58:05Z

New page

==10342==
[[Image:10342top_sm.jpeg|frame|[[Media:10342top.jpeg|10342 board, top view]]]]
[[Image:10342bot_sm.jpeg|frame|[[Media:10342bot.jpeg|10342 board, bottom view]]]]
[[Image:10342bd.png|frame|[[Media:10342sch.pdf|10342 Circuit Diagram]]]]
10342 CCD Interface Board is a part of [[353|Elplhel Model 353/363 Camera]]. It is designed to work together with the CCD Control Board (10347), both controlled by the [[10353|10353 processor board]]. This board is built around 11 Megapixel interline Kodak KAI-11002 CCD image sensor.
This board include:
* pin sockets for the KAI-11002 CCD image sensor (to facilitate sensor replacement)
* a pair of pre-amplifiers of the CCD output signals
* high-current amplifiers for CCD vertical phase drivers. These signals are multi-level, they are generated by a DAC on the [[10353#10347|10347 board]] and then amplified on this board.
* fast high-current drivers for horizontal phase signals - the AC component is generated by the switches with regulated input voltage, DC shift is added to it (for some signals - to the high level, for others - to the lower level) by the programmable bias voltage generator
* bias voltage generator is used to provide DC bias for horizontal phase signals and the levels for DC signals required fro CCD operation. It uses multi-channel serial DAC (programmed by the signals generated by the FPGA on the [[10353#10347|10347 board]] and operational amplifiers to provide required output voltage range for each signal.
* substrate (erase) pulse generator provides a high voltage (>40V) pulse to erase pixels before the exposure
Connectors:
* 10342 board has a single 40-pin connector (J5) in the middle of the board that links it to the [[10353#10347|10347 board]]