FPGA Development in Elphel cameras - Revision history

Andrey.filippov: links to current development

2017-12-01T21:33:13Z

links to current development

← Older revision		Revision as of 21:33, 1 December 2017
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			{{legacy}} See current FPGA project here: [[X393]], [[VDT]]
	== Introduction ==		== Introduction ==
	Much of the performance and flexibility of the Elphel cameras are provided by the reconfigurable [http://en.wikipedia.org/wiki/Fpga FPGA] chips. FPGA is used on the main camera board (currently it is [[10353]]) and on some of the extension ones ([[10347]], [[10359]], [[10357]]). On the main board the FPGA chip complements CPU to perform video processing and compression - it does this nearly 100 times faster than the CPU alone, but generally it is significantly more difficult to implement some functionality in the FPGA than it can be done in the software. And so the camera (like many other modern devices) combines the strong features of both: FPGA performs computationally intensive but algorithmically relatively simple operations (working with the images on the pixel level, providing image compression) and the CPU is responsible for the higher level functions, interface and overall control of the camera.		Much of the performance and flexibility of the Elphel cameras are provided by the reconfigurable [http://en.wikipedia.org/wiki/Fpga FPGA] chips. FPGA is used on the main camera board (currently it is [[10353]]) and on some of the extension ones ([[10347]], [[10359]], [[10357]]). On the main board the FPGA chip complements CPU to perform video processing and compression - it does this nearly 100 times faster than the CPU alone, but generally it is significantly more difficult to implement some functionality in the FPGA than it can be done in the software. And so the camera (like many other modern devices) combines the strong features of both: FPGA performs computationally intensive but algorithmically relatively simple operations (working with the images on the pixel level, providing image compression) and the CPU is responsible for the higher level functions, interface and overall control of the camera.

Oleg at 00:10, 14 November 2009

2009-11-14T00:10:20Z

← Older revision		Revision as of 00:10, 14 November 2009
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	=== Installation of the Xilinx ISE WebPACK ===		=== Installation of the Xilinx ISE WebPACK ===
			For ISE versions 9.2-11.1 - no problems in Ubuntu on 32-bit platforms.

	To install WebPACK on 64-bit platform 32-bit libraries are needed:		To install WebPACK on 64-bit platform 32-bit libraries are needed:
	sudo apt-get install ia32-libs ia32-libs-gtk ia32-libs-sdl dpkg-dev		sudo apt-get install ia32-libs ia32-libs-gtk ia32-libs-sdl dpkg-dev

	When was installing on Kubuntu 9.10 64-bit got:
			When was installing WebPACK 9.2 on Kubuntu 9.10, 64-bit got:
	error while loading shared libraries: libstdc++.so.5: cannot open shared object file: No such file or directory		error while loading shared libraries: libstdc++.so.5: cannot open shared object file: No such file or directory
	[http://swiss.ubuntuforums.org/showthread.php?p=8090632 Solution] - this is the [https://bugs.launchpad.net/ubuntu/+source/ia32-libs/+bug/431091 bug#431091]		[http://swiss.ubuntuforums.org/showthread.php?p=8090632 Solution] - this is the [https://bugs.launchpad.net/ubuntu/+source/ia32-libs/+bug/431091 bug#431091]


			To install WebPack 10.1 on 64-bit - launch ./bin/lin/setup

Oleg at 02:41, 5 November 2009

2009-11-05T02:41:21Z

← Older revision		Revision as of 02:41, 5 November 2009
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	To install WebPACK on 64-bit platform 32-bit libraries are needed:		To install WebPACK on 64-bit platform 32-bit libraries are needed:
	sudo apt-get install ia32-libs ia32-libs-gtk ia32-libs-sdl dpkg-dev		sudo apt-get install ia32-libs ia32-libs-gtk ia32-libs-sdl dpkg-dev

			When was installing on Kubuntu 9.10 64-bit got:
			error while loading shared libraries: libstdc++.so.5: cannot open shared object file: No such file or directory
			[http://swiss.ubuntuforums.org/showthread.php?p=8090632 Solution] - this is the [https://bugs.launchpad.net/ubuntu/+source/ia32-libs/+bug/431091 bug#431091]


	Current versions of Xilinx ISE WebPACK install on Linux rather smoothly (Last time I used WebPACK 9.2 and Kubuntu 7.04) but minor tweaking was needed to launch programs like Timing Analyzer or FPGA Editor. They needed additional package to be installed (don't remember - will put here when find out) and "export DISPLAY=:0" to run correctly (without that ISE "as if" launches those programs, but nothing really happens). I just created a small startup script ''launch_ise.sh'' in the WebPACK installation directory (it was /usr/local/Xilinx92 in my case) with the following content:		Current versions of Xilinx ISE WebPACK install on Linux rather smoothly (Last time I used WebPACK 9.2 and Kubuntu 7.04) but minor tweaking was needed to launch programs like Timing Analyzer or FPGA Editor. They needed additional package to be installed (don't remember - will put here when find out) and "export DISPLAY=:0" to run correctly (without that ISE "as if" launches those programs, but nothing really happens). I just created a small startup script ''launch_ise.sh'' in the WebPACK installation directory (it was /usr/local/Xilinx92 in my case) with the following content:

OneArtPlease: /* Introduction */

2008-05-24T14:01:16Z

Introduction

← Older revision		Revision as of 14:01, 24 May 2008
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	Much of the performance and flexibility of the Elphel cameras are provided by the reconfigurable [http://en.wikipedia.org/wiki/Fpga FPGA] chips. FPGA is used on the main camera board (currently it is [[10353]]) and on some of the extension ones ([[10347]], [[10359]], [[10357]]). On the main board the FPGA chip complements CPU to perform video processing and compression - it does this nearly 100 times faster than the CPU alone, but generally it is significantly more difficult to implement some functionality in the FPGA than it can be done in the software. And so the camera (like many other modern devices) combines the strong features of both: FPGA performs computationally intensive but algorithmically relatively simple operations (working with the images on the pixel level, providing image compression) and the CPU is responsible for the higher level functions, interface and overall control of the camera.		Much of the performance and flexibility of the Elphel cameras are provided by the reconfigurable [http://en.wikipedia.org/wiki/Fpga FPGA] chips. FPGA is used on the main camera board (currently it is [[10353]]) and on some of the extension ones ([[10347]], [[10359]], [[10357]]). On the main board the FPGA chip complements CPU to perform video processing and compression - it does this nearly 100 times faster than the CPU alone, but generally it is significantly more difficult to implement some functionality in the FPGA than it can be done in the software. And so the camera (like many other modern devices) combines the strong features of both: FPGA performs computationally intensive but algorithmically relatively simple operations (working with the images on the pixel level, providing image compression) and the CPU is responsible for the higher level functions, interface and overall control of the camera.

	Elphel does not make secrets of the FPGA code, all the source code is available under [http://www.gnu.org/licenses/gpl.html GNU GPL v 3.0] license, the same one as used for the camera software. Elphel software distribution (available both on [https://sourceforge.net/projects/elphel Sourceforge project page] and inside each camera file system) includes both binary FPGA image ("bit file") and the source code needed to re-create the FPGA image and/or simulate the design. Also included are the log files generated by the FPGA "compiler" during creation of the provided bit file so you may look inside even if you do not have the necessary FPGA tools, you may also find these files useful to compare with the output that you get from those tools.		Elphel does not make secrets of the FPGA code, all the source code is available under [http://www.gnu.org/licenses/gpl.html GNU GPL v 3.0] license, the same one as used for the camera software. Elphel software distribution (available both on [https://sourceforge.net/projects/elphel Sourceforge project page] and inside each camera file system) includes both binary FPGA image ("bit file") and the source code (*.v files in \elphel_tree\fpga) needed to re-create the FPGA image and/or simulate the design. Also included are the log files generated by the FPGA "compiler" during creation of the provided bit file so you may look inside even if you do not have the necessary FPGA tools, you may also find these files useful to compare with the output that you get from those tools.

	==FPGA design flow==		==FPGA design flow==

Oleg at 10:58, 7 May 2008

2008-05-07T10:58:21Z

← Older revision		Revision as of 10:58, 7 May 2008
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	Luckily there are really free (GNU GPL) tools available for simulation and Elphel provides scripts for simulation of the design using these tools. Simulation software we use consists of two parts (that require separate installation), provided are the links to the current (as of January,28 2008) releases:		Luckily there are really free (GNU GPL) tools available for simulation and Elphel provides scripts for simulation of the design using these tools. Simulation software we use consists of two parts (that require separate installation), provided are the links to the current (as of January,28 2008) releases:
	* [ftp://ftp.icarus.com/pub/eda/verilog/v0.8/verilog-0.8.6.tar.gz Icarus] Verilog simulator and		* [ftp://ftp.icarus.com/pub/eda/verilog/v0.8/verilog-0.8.6.tar.gz Icarus] Verilog simulator and
	* [http://home.nc.rr.com/gtkwave/ GTKWave] wave viewer - download: [http://home.nc.rr.com/gtkwave/gtkwave~~-3.1.9.tar.gz gtkwave-3.1.9.tar.gz~~], documentation (archived PDF): [http://home.nc.rr.com/gtkwave/gtkwave-doc-3.1.3.tar.gz gtkwave-doc-3.1.3.tar.gz].		* [http://home.nc.rr.com/gtkwave/ GTKWave] wave viewer - download: [http://home.nc.rr.com/gtkwave/ gtkwave], documentation (archived PDF): [http://home.nc.rr.com/gtkwave/gtkwave-doc-3.1.3.tar.gz gtkwave-doc-3.1.3.tar.gz].

	Note:''You will still need to download and install [http://www.xilinx.com/ise/logic_design_prod/webpack.htm Xilinx ISE WebPACK (R)] even for simulation only. That package includes Verilog source code library that describes the FPGA device primitives used in the design and the current license does not allow to distribute this library with the design.''		Note:''You will still need to download and install [http://www.xilinx.com/ise/logic_design_prod/webpack.htm Xilinx ISE WebPACK (R)] even for simulation only. That package includes Verilog source code library that describes the FPGA device primitives used in the design and the current license does not allow to distribute this library with the design.''

Oleg at 10:56, 7 May 2008

2008-05-07T10:56:52Z

← Older revision		Revision as of 10:56, 7 May 2008
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	Luckily there are really free (GNU GPL) tools available for simulation and Elphel provides scripts for simulation of the design using these tools. Simulation software we use consists of two parts (that require separate installation), provided are the links to the current (as of January,28 2008) releases:		Luckily there are really free (GNU GPL) tools available for simulation and Elphel provides scripts for simulation of the design using these tools. Simulation software we use consists of two parts (that require separate installation), provided are the links to the current (as of January,28 2008) releases:
	* [ftp://ftp.icarus.com/pub/eda/verilog/v0.8/verilog-0.8.6.tar.gz Icarus] Verilog simulator and		* [ftp://ftp.icarus.com/pub/eda/verilog/v0.8/verilog-0.8.6.tar.gz Icarus] Verilog simulator and
	* [http://home.nc.rr.com/gtkwave/ GTKWave] wave viewer - download: [http://home.nc.rr.com/gtkwave/gtkwave-3.1.4.tar.gz gtkwave-3.1.4.tar.gz], documentation (archived PDF): [http://home.nc.rr.com/gtkwave/gtkwave-doc-3.1.3.tar.gz gtkwave-doc-3.1.3.tar.gz].		* [http://home.nc.rr.com/gtkwave/ GTKWave] wave viewer - download: [http://home.nc.rr.com/gtkwave/gtkwave-3.1.9.tar.gz gtkwave-3.1.9.tar.gz], documentation (archived PDF): [http://home.nc.rr.com/gtkwave/gtkwave-doc-3.1.3.tar.gz gtkwave-doc-3.1.3.tar.gz].

	Note:''You will still need to download and install [http://www.xilinx.com/ise/logic_design_prod/webpack.htm Xilinx ISE WebPACK (R)] even for simulation only. That package includes Verilog source code library that describes the FPGA device primitives used in the design and the current license does not allow to distribute this library with the design.''		Note:''You will still need to download and install [http://www.xilinx.com/ise/logic_design_prod/webpack.htm Xilinx ISE WebPACK (R)] even for simulation only. That package includes Verilog source code library that describes the FPGA device primitives used in the design and the current license does not allow to distribute this library with the design.''

Okdzhimiev: /* Installation of the Xilinx ISE WebPACK */

2008-02-05T01:11:52Z

Installation of the Xilinx ISE WebPACK

← Older revision		Revision as of 01:11, 5 February 2008
Line 22:		Line 22:

	=== Installation of the Xilinx ISE WebPACK ===		=== Installation of the Xilinx ISE WebPACK ===
			To install WebPACK on 64-bit platform 32-bit libraries are needed:
			sudo apt-get install ia32-libs ia32-libs-gtk ia32-libs-sdl dpkg-dev

	Current versions of Xilinx ISE WebPACK install on Linux rather smoothly (Last time I used WebPACK 9.2 and Kubuntu 7.04) but minor tweaking was needed to launch programs like Timing Analyzer or FPGA Editor. They needed additional package to be installed (don't remember - will put here when find out) and "export DISPLAY=:0" to run correctly (without that ISE "as if" launches those programs, but nothing really happens). I just created a small startup script ''launch_ise.sh'' in the WebPACK installation directory (it was /usr/local/Xilinx92 in my case) with the following content:		Current versions of Xilinx ISE WebPACK install on Linux rather smoothly (Last time I used WebPACK 9.2 and Kubuntu 7.04) but minor tweaking was needed to launch programs like Timing Analyzer or FPGA Editor. They needed additional package to be installed (don't remember - will put here when find out) and "export DISPLAY=:0" to run correctly (without that ISE "as if" launches those programs, but nothing really happens). I just created a small startup script ''launch_ise.sh'' in the WebPACK installation directory (it was /usr/local/Xilinx92 in my case) with the following content:

Okdzhimiev at 22:25, 4 February 2008

2008-02-04T22:25:41Z

← Older revision		Revision as of 22:25, 4 February 2008
Line 17:		Line 17:
	Luckily there are really free (GNU GPL) tools available for simulation and Elphel provides scripts for simulation of the design using these tools. Simulation software we use consists of two parts (that require separate installation), provided are the links to the current (as of January,28 2008) releases:		Luckily there are really free (GNU GPL) tools available for simulation and Elphel provides scripts for simulation of the design using these tools. Simulation software we use consists of two parts (that require separate installation), provided are the links to the current (as of January,28 2008) releases:
	* [ftp://ftp.icarus.com/pub/eda/verilog/v0.8/verilog-0.8.6.tar.gz Icarus] Verilog simulator and		* [ftp://ftp.icarus.com/pub/eda/verilog/v0.8/verilog-0.8.6.tar.gz Icarus] Verilog simulator and
	* [http://home.nc.rr.com/gtkwave/ GTKWave] wave viewer - download: [http://home.nc.rr.com/gtkwave/gtkwave-3.1.3.tar.gz gtkwave-3.1.3.tar.gz], documentation (archived PDF): [http://home.nc.rr.com/gtkwave/gtkwave-doc-3.1.3.tar.gz gtkwave-doc-3.1.3.tar.gz].		* [http://home.nc.rr.com/gtkwave/ GTKWave] wave viewer - download: [http://home.nc.rr.com/gtkwave/gtkwave-3.1.4.tar.gz gtkwave-3.1.4.tar.gz], documentation (archived PDF): [http://home.nc.rr.com/gtkwave/gtkwave-doc-3.1.3.tar.gz gtkwave-doc-3.1.3.tar.gz].

	Note:''You will still need to download and install [http://www.xilinx.com/ise/logic_design_prod/webpack.htm Xilinx ISE WebPACK (R)] even for simulation only. That package includes Verilog source code library that describes the FPGA device primitives used in the design and the current license does not allow to distribute this library with the design.''		Note:''You will still need to download and install [http://www.xilinx.com/ise/logic_design_prod/webpack.htm Xilinx ISE WebPACK (R)] even for simulation only. That package includes Verilog source code library that describes the FPGA device primitives used in the design and the current license does not allow to distribute this library with the design.''

Andrey.filippov at 07:08, 29 January 2008

2008-01-29T07:08:22Z

← Older revision		Revision as of 07:08, 29 January 2008
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	command will be executed that should open the waveform viewer. In addition to the simulation result "x353.lxt" the viewer uses "[http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/fpga/x3x3/x353_1.sav?view=markup x353_1.sav]" - file that contains viewer state with some signals selected and grouped. GTKWave allows you to create, save and read back such files.		command will be executed that should open the waveform viewer. In addition to the simulation result "x353.lxt" the viewer uses "[http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/fpga/x3x3/x353_1.sav?view=markup x353_1.sav]" - file that contains viewer state with some signals selected and grouped. GTKWave allows you to create, save and read back such files.

	You may change the simulation sequence by modifying the file [http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/fpga/x3x3/x353_1.tf?view=markup fpga/x3x3/x353_1.tf] or creating a new simulation sequence and ~~pointing~~ the [http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/fpga/x3x3/x353_sim.sh?view=markup fpga/x3x3/x353_sim.sh] script to that file.		You may change the simulation sequence by modifying the file [http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/fpga/x3x3/x353_1.tf?view=markup fpga/x3x3/x353_1.tf] or creating a new simulation sequence and modifying the [http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/fpga/x3x3/x353_sim.sh?view=markup fpga/x3x3/x353_sim.sh] script to use that file instead of the [http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/fpga/x3x3/x353_1.tf?view=markup fpga/x3x3/x353_1.tf].

Andrey.filippov at 07:06, 29 January 2008

2008-01-29T07:06:59Z

← Older revision		Revision as of 07:06, 29 January 2008
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	After the simulation itself will start that generates "x353.lxt" (older version if any of that file was removed at the start of the script). It will take some time to simulate a fraction of a millisecond (as simulation is about a million times slower than the real time) and then the		After the simulation itself will start that generates "x353.lxt" (older version if any of that file was removed at the start of the script). It will take some time to simulate a fraction of a millisecond (as simulation is about a million times slower than the real time) and then the
	gtkwave x353.lxt x353_1.sav &		gtkwave x353.lxt x353_1.sav &
	command will be executed that should open the waveform viewer. In addition to the simulation result "x353.lxt" the viewer uses x353_1.sav - file that contains viewer state with some signals selected and grouped. GTKWave allows you to create, save and read back such files.		command will be executed that should open the waveform viewer. In addition to the simulation result "x353.lxt" the viewer uses "[http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/fpga/x3x3/x353_1.sav?view=markup x353_1.sav]" - file that contains viewer state with some signals selected and grouped. GTKWave allows you to create, save and read back such files.

	You may change the simulation sequence by modifying the file [http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/fpga/x3x3/x353_1.tf?view=markup fpga/x3x3/x353_1.tf] or creating a new simulation sequence and pointing the [http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/fpga/x3x3/x353_sim.sh?view=markup fpga/x3x3/x353_sim.sh] script to that file.		You may change the simulation sequence by modifying the file [http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/fpga/x3x3/x353_1.tf?view=markup fpga/x3x3/x353_1.tf] or creating a new simulation sequence and pointing the [http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/fpga/x3x3/x353_sim.sh?view=markup fpga/x3x3/x353_sim.sh] script to that file.