Load custom bitstream - Revision history

Oleg at 21:50, 20 April 2017

2017-04-20T21:50:30Z

← Older revision		Revision as of 21:50, 20 April 2017
Line 3:		Line 3:

	Reasons:		Reasons:
	* Different banks have different (software - controlled and regulated) voltages and they need to be set up before loading.		* Different banks have different (software controlled and regulated) voltages and they need to be set up before loading.
	** voltages are set by the software through i2c		** voltages are set by the software through i2c

Oleg: /* Init */

2017-04-20T21:49:39Z

Init

← Older revision		Revision as of 21:49, 20 April 2017
Line 31:		Line 31:

	==Init==		==Init==
	* '''detect_sensors''' driver reads the device tree to get the default system configuration which gets later updated by '''autocampars'''		* '''detect_sensors''' driver reads the device tree to get the default system configuration which gets later updated by '''autocampars''' application
	* /etc/init.d/init_elphel393		* /etc/init.d/init_elphel393
	...		...

Oleg: /* Init */

2017-04-20T21:49:19Z

Init

← Older revision		Revision as of 21:49, 20 April 2017
Line 31:		Line 31:

	==Init==		==Init==
			* '''detect_sensors''' driver reads the device tree to get the default system configuration which gets later updated by '''autocampars'''
	* /etc/init.d/init_elphel393		* /etc/init.d/init_elphel393
	...		...

Oleg: /* sata */

2017-04-20T21:41:00Z

sata

← Older revision		Revision as of 21:41, 20 April 2017
Line 63:		Line 63:
	* project [https://git.elphel.com/Elphel/x393_sata x393_sata]		* project [https://git.elphel.com/Elphel/x393_sata x393_sata]
	* Location on target system: ''/usr/local/verilog/''		* Location on target system: ''/usr/local/verilog/''
	* '''/usr/local/bin/x393sata.py''' loads it default bitstream if fpga ~~was~~ not programmed yet.		* '''/usr/local/bin/x393sata.py''' loads it default bitstream if fpga has not been programmed yet.
	...		...
	DEFAULT_BITFILE="/usr/local/verilog/x393_sata.bit"		DEFAULT_BITFILE="/usr/local/verilog/x393_sata.bit"

Oleg: /* Bitstreams paths */

2017-04-20T21:39:16Z

Bitstreams paths

← Older revision		Revision as of 21:39, 20 April 2017
Line 7:		Line 7:

	==Bitstreams paths==		==Bitstreams paths==
	* ''/usr/local/verilog/''		* Location on target system: ''/usr/local/verilog/''
	{\| class='wikitable'		{\| class='wikitable'
	! name		! name
			! project
	! description		! description
	\|-		\|-
	\|x393_parallel.bit		\|x393_parallel.bit
			\|[https://git.elphel.com/Elphel/x393 x393]
	\|for 5MPix sensor with parallel interface + SATA		\|for 5MPix sensor with parallel interface + SATA
	\|-		\|-
	\|x393_hispi.bit		\|x393_hispi.bit
			\|[https://git.elphel.com/Elphel/x393 x393]
	\|for 14MPix sensor with serial interface + SATA		\|for 14MPix sensor with serial interface + SATA
	\|-		\|-
	\|x393_sata.bit		\|x393_sata.bit
			\|[https://git.elphel.com/Elphel/x393_sata x393_sata]
	\|SATA only		\|SATA only
	\|-		\|-
	\|x359.bit		\|x359.bit
			\|[https://git.elphel.com/Elphel/x359 x359]
	\|for external MUX 3-to-1 board		\|for external MUX 3-to-1 board
	\|}		\|}

Oleg at 21:36, 20 April 2017

2017-04-20T21:36:02Z

← Older revision		Revision as of 21:36, 20 April 2017
Line 37:		Line 37:
	* project: [https://git.elphel.com/Elphel/elphel-apps-autocampars elphel-apps-autocampars]		* project: [https://git.elphel.com/Elphel/elphel-apps-autocampars elphel-apps-autocampars]
	* top script: '''autocampars.php'''		* top script: '''autocampars.php'''
	** ~~location~~ on target: /usr/bin/		** Location on target system: ''/usr/bin/''
	** loads ''/usr/local/verilog/x359.bit'' to the external MUX board		** loads ''/usr/local/verilog/x359.bit'' to the external MUX board
	** depending on configuration (determined in init_elphel393.py) calls '''/usr/bin/autocampars.py''' with arguments listed in the files in ''/usr/local/verilog''. The default one is ''/usr/local/verilog/hargs'':		** depending on configuration (determined in init_elphel393.py) calls '''/usr/bin/autocampars.py''' with arguments listed in the files in ''/usr/local/verilog''. The default one is ''/usr/local/verilog/hargs'':
Line 53:		Line 53:
	The file with arguments can be found in the fpga projects, example:		The file with arguments can be found in the fpga projects, example:
	https://git.elphel.com/Elphel/x393/tree/master/py393		https://git.elphel.com/Elphel/x393/tree/master/py393
			Location on target system: ''/usr/local/verilog/''

	===sata===		===sata===
	* project [https://git.elphel.com/Elphel/x393_sata x393_sata]		* project [https://git.elphel.com/Elphel/x393_sata x393_sata]
			* Location on target system: ''/usr/local/verilog/''
	* '''/usr/local/bin/x393sata.py''' loads it default bitstream if fpga was not programmed yet.		* '''/usr/local/bin/x393sata.py''' loads it default bitstream if fpga was not programmed yet.
	...		...

Oleg: /* autocampars */

2017-04-20T21:32:00Z

autocampars

← Older revision		Revision as of 21:32, 20 April 2017
Line 37:		Line 37:
	* project: [https://git.elphel.com/Elphel/elphel-apps-autocampars elphel-apps-autocampars]		* project: [https://git.elphel.com/Elphel/elphel-apps-autocampars elphel-apps-autocampars]
	* top script: '''autocampars.php'''		* top script: '''autocampars.php'''
			** location on target: /usr/bin/
	** loads ''/usr/local/verilog/x359.bit'' to the external MUX board		** loads ''/usr/local/verilog/x359.bit'' to the external MUX board
	** depending on configuration (determined in init_elphel393.py) calls '''autocampars.py''' with arguments listed in the files in ''/usr/local/verilog''. The default one is ''/usr/local/verilog/hargs'':		** depending on configuration (determined in init_elphel393.py) calls '''/usr/bin/autocampars.py''' with arguments listed in the files in ''/usr/local/verilog''. The default one is ''/usr/local/verilog/hargs'':
	-d TARGET_MODE=1		-d TARGET_MODE=1
	-f /usr/local/verilog/system_defines.vh		-f /usr/local/verilog/system_defines.vh

Oleg at 21:27, 20 April 2017

2017-04-20T21:27:16Z

@@ Line 1: / Line 1: @@
 ==Description==
 The default bitstream is loaded from OS not from u-boot.
 Reasons:
 * Different banks have different (software - controlled and regulated) voltages and they need to be set up before loading.
@@ Line 33: / Line 34: @@
 ** the bitstream is loaded by '''autocampars''' or '''sata''' (if autocampars is skipped)
 [[Category:393]]

Oleg at 21:07, 20 April 2017

2017-04-20T21:07:45Z

← Older revision		Revision as of 21:07, 20 April 2017
Line 21:		Line 21:
	\|-		\|-
	\|x359.bit		\|x359.bit
	\|for external MUX 3-1 board		\|for external MUX 3-to-1 board
	\|}		\|}

Oleg at 21:07, 20 April 2017

2017-04-20T21:07:09Z

← Older revision		Revision as of 21:07, 20 April 2017
Line 5:		Line 5:
	** voltages are set by the software through i2c		** voltages are set by the software through i2c

	Bitstreams paths:		==Bitstreams paths==
	* ''/usr/local/verilog/''		* ''/usr/local/verilog/''
			{\| class='wikitable'
			! name
			! description
			\|-
			\|x393_parallel.bit
			\|for 5MPix sensor with parallel interface + SATA
			\|-
			\|x393_hispi.bit
			\|for 14MPix sensor with serial interface + SATA
			\|-
			\|x393_sata.bit
			\|SATA only
			\|-
			\|x359.bit
			\|for external MUX 3-1 board
			\|}

	Init:		==Init==
	* /etc/init.d/init_elphel393		* /etc/init.d/init_elphel393
	...		...