Mcontr - Revision history

Oleg at 16:49, 18 September 2008

2008-09-18T16:49:46Z

@@ Line 24: / Line 24: @@
 * maximum number of tiles in a row
 ==TODO==
 *bank interleaving
 *run-time programmable SDRAM sequencing

Oleg at 16:36, 18 September 2008

2008-09-18T16:36:43Z

← Older revision		Revision as of 16:36, 18 September 2008
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	==Programmable SDRAM sequence==		==Programmable SDRAM sequence==
			Programmable:
			* sequence length
			* tile length in column(x4 banks)
			* tile width in rows
			* address shift in a column for a new tile
			* address shift in a row for a new tile
			* maximum number of tiles in a column
			* maximum number of tiles in a row


	==TODO==		==TODO==
	*bank interleaving		*bank interleaving
	*run-time programmable SDRAM sequencing		*run-time programmable SDRAM sequencing

Oleg at 16:09, 18 September 2008

2008-09-18T16:09:46Z

← Older revision		Revision as of 16:09, 18 September 2008
Line 1:		Line 1:
	==Description==		==Description==
	FPGA module that controls reads and writes between FPGA and DDR SDRAM (boards 10353 & 10359).		FPGA module that controls reads and writes between FPGA and DDR SDRAM (boards 10353 & 10359).

			[[Image:Mcontr scheme.jpg\|center\|frame\|[[Media:Mcontr scheme.jpg\|Fig.1 Mcontr functional scheme]]]]

	==Bank interleaving==		==Bank interleaving==
Line 10:		Line 12:


	[[Image:Bank interleaving.jpg\|center\|frame\|[[Media:Bank interleaving.jpg\|Fig.1 Bank interleaving example]]]]		[[Image:Bank interleaving.jpg\|center\|frame\|[[Media:Bank interleaving.jpg\|Fig.2 Bank interleaving example]]]]

			==Programmable SDRAM sequence==

	==TODO==		==TODO==
	*bank interleaving		*bank interleaving
	*run-time programmable SDRAM sequencing		*run-time programmable SDRAM sequencing

Oleg at 15:37, 18 September 2008

2008-09-18T15:37:55Z

← Older revision		Revision as of 15:37, 18 September 2008
Line 1:		Line 1:
	==Description==		==Description==
	FPGA module that controls reads and writes between FPGA and DDR SDRAM (boards 10353 & 10359).		FPGA module that controls reads and writes between FPGA and DDR SDRAM (boards 10353 & 10359).

			==Bank interleaving==
			* Taken from Theora's code.
			* Banks addresses (SDA[14:13]) and order used in a single memory access: 00&10, 11&01, 10&00, 01&11.
			* Both banks are opened in the beginning of the sequence.
			* Write/read sequence is divided by 2 and all column addresses are the same.
			* Row address of the second bank in a sequence is the first bank's + 1.


			[[Image:Bank interleaving.jpg\|center\|frame\|[[Media:Bank interleaving.jpg\|Fig.1 Bank interleaving example]]]]


	==TODO==		==TODO==
	*bank interleaving		*bank interleaving
	*run-time programmable SDRAM sequencing		*run-time programmable SDRAM sequencing

Oleg at 08:24, 11 August 2008

2008-08-11T08:24:31Z

New page

==Description==
FPGA module that controls reads and writes between FPGA and DDR SDRAM (boards 10353 & 10359).

==TODO==
*bank interleaving
*run-time programmable SDRAM sequencing