Talk:10359 - Revision history

Oleg at 22:48, 8 November 2010

2010-11-08T22:48:45Z

@@ Line 177: / Line 177: @@
 [0] - global reset
 | Mode register
 |-
@@ Line 190: / Line 195: @@
 [0] - '1' - delays Hact of the 2nd frame in combined mode by 1 clock
 | delay hacts by 1 clock
 |-

Oleg at 20:43, 20 May 2010

2010-05-20T20:43:45Z

← Older revision		Revision as of 20:43, 20 May 2010
Line 186:		Line 186:
	\| 0x80d		\| 0x80d
	\|		\|
	[1] - '1' - delays Hact of the ~~2nd~~ frame in combined mode by 1 clock		[1] - '1' - delays Hact of the 3rd frame in combined mode by 1 clock

	[0] - '1' - delays Hact of the ~~3rd~~ frame in combined mode by 1 clock		[0] - '1' - delays Hact of the 2nd frame in combined mode by 1 clock
	\| delay hacts by 1 clock		\| delay hacts by 1 clock

Line 194:		Line 194:
	\| 0x813		\| 0x813
	\| default value:2596		\| default value:2596
	\| x size for read mcontr channel 1 (~~3rd~~ frame)		\| x size for read mcontr channel 1 (2nd frame)

	\|-		\|-
	\| 0x814		\| 0x814
	\| default value:1940		\| default value:1940
	\| y size for read mcontr channel 1 (~~3rd~~ frame)		\| y size for read mcontr channel 1 (2nd frame)

	\|-		\|-
	\| 0x815		\| 0x815
	\| default value:256		\| default value:256
	\| pause between the lines for frame from channel 1 (~~3rd~~ frame)		\| pause between the lines for frame from channel 1 (2nd frame)

	\|-		\|-
	\| 0x816		\| 0x816
	\| default value:0		\| default value:0
	\| number of blank lines before the channel 1 frame		\| number of blank lines before the channel 1 frame (2nd frame)


	\|-		\|-
	\| 0x823		\| 0x823
	\| default value:2596		\| default value:2596
	\| x size for read mcontr channel 3 (~~2nd~~ frame)		\| x size for read mcontr channel 3 (3rd frame)

	\|-		\|-
	\| 0x824		\| 0x824
	\| default value:1940		\| default value:1940
	\| y size for read mcontr channel 3 (~~2nd~~ frame)		\| y size for read mcontr channel 3 (3rd frame)

	\|-		\|-
	\| 0x825		\| 0x825
	\| default value:256		\| default value:256
	\| pause between the lines for frame from channel 3 (~~2nd~~ frame)		\| pause between the lines for frame from channel 3 (3rd frame)

	\|-		\|-
	\| 0x826		\| 0x826
	\| default value:0		\| default value:0
	\| number of blank lines before the channel 3 frame		\| number of blank lines before the channel 3 frame (3rd frame)

	\|-		\|-

Oleg at 03:10, 14 May 2010

2010-05-14T03:10:19Z

← Older revision		Revision as of 03:10, 14 May 2010
Line 183:		Line 183:
	\| delay between frames in alternation mode.		\| delay between frames in alternation mode.

			\|-
			\| 0x80d
			\|
			[1] - '1' - delays Hact of the 2nd frame in combined mode by 1 clock

			[0] - '1' - delays Hact of the 3rd frame in combined mode by 1 clock
			\| delay hacts by 1 clock

	\|-		\|-

Oleg at 18:08, 12 May 2010

2010-05-12T18:08:25Z

← Older revision		Revision as of 18:08, 12 May 2010
Line 309:		Line 309:
	[29:16] - the last SDRAM page address for current channel		[29:16] - the last SDRAM page address for current channel
	\| ch2,ch3 tile size register, part2		\| ch2,ch3 tile size register, part2

	\|}		\|}

Line 361:		Line 360:
	[15:0] - data		[15:0] - data
	\| Write/Read word		\| Write/Read word
	\|-

	\|}		\|}

Oleg at 17:59, 12 May 2010

2010-05-12T17:59:57Z

← Older revision		Revision as of 17:59, 12 May 2010
Line 232:		Line 232:
	====Mcontr write registers====		====Mcontr write registers====
	for the high 16 bits reg 0x850 is used. All the regs considered to be 32 bit wide.		for the high 16 bits reg 0x850 is used. All the regs considered to be 32 bit wide.

			even numbered channels - SDRAM write channels: ch0, ch2

			odd numbered channels - SDRAM read channels: ch1, ch3

	{\| border="1" cellpadding="2"		{\| border="1" cellpadding="2"
Line 258:		Line 262:
	\| 0x844		\| 0x844
	\|		\|
	\| ch0 start address, 12-bit ~~mem~~ page		\| ch0 start address, 12-bit SDRAM page

			\|-
			\| 0x845
			\|
			\| ch1 start address, 12-bit SDRAM page

			\|-
			\| 0x846
			\|
			\| ch2 start address, 12-bit SDRAM page

			\|-
			\| 0x847
			\|
			\| ch3 start address, 12-bit SDRAM page

	\|-		\|-
	\| ~~0x845~~		\| 0x84c
	\|		\|
	\| ch1 ~~start address~~, ~~12-bit mem page~~		[31:16] - number of writes before another type of shift

			[15: 8] - address shift after burst

			[ 7: 0] - number of 8-word bursts in one write
			\| ch0,ch1 tile size register, part1

			\|-
			\| 0x84e
			\| [29:16] - the last SDRAM page address for current channel
			\| ch0,ch1 tile size register, part2

	\|-		\|-
	\| ~~0x846~~		\| 0x84d
	\|		\|
	~~\| ch2 start address, 12~~-~~bit mem page~~		[31:16] - number of writes before another type of shift

			[15: 8] - address shift after burst

			[ 7: 0] - number of 8-word bursts in one write
			\| ch2,ch3 tile size register, part1

	\|-		\|-
	\| ~~0x847~~		\| 0x84f
	\|		\|
	\| ch3 ~~start address~~, ~~12-bit mem page~~		[29:16] - the last SDRAM page address for current channel
			\| ch2,ch3 tile size register, part2

	\|}		\|}

Oleg at 17:32, 12 May 2010

2010-05-12T17:32:23Z

@@ Line 228: / Line 228: @@
+|
 | upper 16-bit part for 0x84X mcontr registers
 |}

Oleg at 22:44, 10 May 2010

2010-05-10T22:44:56Z

← Older revision		Revision as of 22:44, 10 May 2010
Line 177:		Line 177:
	[0] - global reset		[0] - global reset
	\| Mode register		\| Mode register

			\|-
			\| 0x80c
			\| default value: 0x0
			\| delay between frames in alternation mode.


	\|-		\|-
Line 279:		Line 285:

	====Combined frame mode enable sequence====		====Combined frame mode enable sequence====
	i2c_send(0x809,2); // disable output		i2c_send(16,0,0x809,2,0); // disable output
	i2c_send(0x809,3); // disable output + reset to all regs		i2c_send(16,0,0x809,3,0); // disable output + reset to all regs

	i2c_send(0x813,2596); // pixels in line for read the 3rd frame from channel 1 from SDRAM		i2c_send(16,0,0x813,2596,0); // pixels in line for read the 3rd frame from channel 1 from SDRAM
	i2c_send(0x814,1940); // number of lines for read the 3rd frame from channel 1 from SDRAM		i2c_send(16,0,0x814,1940,0); // number of lines for read the 3rd frame from channel 1 from SDRAM

	i2c_send(0x823,2596); // pixels in line for read the 2nd frame from channel 3 from SDRAM		i2c_send(16,0,0x823,2596,0); // pixels in line for read the 2nd frame from channel 3 from SDRAM
	i2c_send(0x824,1940); // number of lines for read the 2nd frame from channel 3 from SDRAM		i2c_send(16,0,0x824,1940,0); // number of lines for read the 2nd frame from channel 3 from SDRAM

	i2c_send(0x850,0x0001); i2c_send(0x840,0x5555); // init all mcontr channels		i2c_send(16,0,0x850,0x0001,0); i2c_send(16,0,0x840,0x5555,0); // init all mcontr channels

	// SDRAM init sequence, not necessary		// SDRAM init sequence, not necessary
	i2c_send(0x850,0x0001); i2c_send(0x840,0x5555); // Disable DDR SDRAM read/write channels		i2c_send(16,0,0x850,0x0001,0); i2c_send(16,0,0x840,0x5555,0); // Disable DDR SDRAM read/write channels
	i2c_send(0x850,0x0001); i2c_send(0x841,0x7fff); // PRE : Addr[10] = 1, Bank = 11		i2c_send(16,0,0x850,0x0001,0); i2c_send(16,0,0x841,0x7fff,0); // PRE : Addr[10] = 1, Bank = 11
	i2c_send(0x850,0x0000); i2c_send(0x841,0x2002); // Extended mode register - Enable DLL		i2c_send(16,0,0x850,0x0000,0); i2c_send(16,0,0x841,0x2002,0); // Extended mode register - Enable DLL
	i2c_send(0x850,0x0000); i2c_send(0x841,0x0163); // Load Mode Register - Burst Length - 8, CAS latency - 2.5		i2c_send(16,0,0x850,0x0000,0); i2c_send(16,0,0x841,0x0163,0); // Load Mode Register - Burst Length - 8, CAS latency - 2.5
	i2c_send(0x850,0x0000); i2c_send(0x841,0x8000); // Refresh		i2c_send(16,0,0x850,0x0000,0); i2c_send(16,0,0x841,0x8000,0); // Refresh
	i2c_send(0x850,0x0000); i2c_send(0x841,0x8000); // Refresh		i2c_send(16,0,0x850,0x0000,0); i2c_send(16,0,0x841,0x8000,0); // Refresh
	i2c_send(0x850,0x0001); i2c_send(0x841,0x7fff); // PRE : Addr[10] = 1, Bank = 11		i2c_send(16,0,0x850,0x0001,0); i2c_send(16,0,0x841,0x7fff,0); // PRE : Addr[10] = 1, Bank = 11
	i2c_send(0x850,0x0001); i2c_send(0x840,0x0000); // Init auto refresh		i2c_send(16,0,0x850,0x0001,0); i2c_send(16,0,0x840,0x0000,0); // Init auto refresh
	i2c_send(0x850,0x0000); i2c_send(0x840,0x5555); // Disable DDR SDRAM read/write channels		i2c_send(16,0,0x850,0x0000,0); i2c_send(16,0,0x840,0x5555,0); // Disable DDR SDRAM read/write channels
	i2c_send(0x850,0x0002); i2c_send(0x840,0x0000); // Enable auto refresh		i2c_send(16,0,0x850,0x0002,0); i2c_send(16,0,0x840,0x0000,0); // Enable auto refresh

	i2c_send(0x850,0x0002); i2c_send(0x840,0xaaaa); // enable all mcontr channels		i2c_send(16,0,0x850,0x0002); i2c_send(16,0,0x840,0xaaaa,0); // enable all mcontr channels

	// mcontr channels configuration		// mcontr channels configuration

	i2c_send(0x850,0x000f); i2c_send(0x84c,0x020f); // parameters for write channel 0		i2c_send(16,0,0x850,0x000f,0); i2c_send(16,0,0x84c,0x020f,0); // parameters for write channel 0
	i2c_send(0x850,0x1fff); i2c_send(0x84e,0x10ff); // parameters for read channel 1		i2c_send(16,0,0x850,0x1fff,0); i2c_send(16,0,0x84e,0x10ff,0); // parameters for read channel 1

			i2c_send(16,0,0x850,0x000f,0); i2c_send(16,0,0x84d,0x020f,0); // parameters for write channel 2
			i2c_send(16,0,0x850,0x1fff,0); i2c_send(16,0,0x84f,0x10ff,0); // parameters for read channel 3

	i2c_send(0x850,~~0x000f~~); i2c_send(~~0x84d~~,~~0x020f); // parameters for write channel 2~~		i2c_send(16,0,0x850,0x1c00,0); i2c_send(16,0,0x843,0x0c21,0); // don't remember
	~~i2c_send(0x850~~,~~0x1fff); i2c_send(0x84f~~,~~0x10ff~~); // ~~parameters for read channel 3~~

	i2c_send(0x850,~~0x1c00~~); i2c_send(~~0x843~~,~~0x0c21~~); // ~~don't remember~~		i2c_send(16,0,0x850,0x0001,0); i2c_send(16,0,0x840,0x5555,0); // init to store channels parameters

	i2c_send(0x850,~~0x0001~~); i2c_send(~~0x840~~,~~0x5555~~); // ~~init to store channels parameters~~		i2c_send(16,0,0x850,0x0000,0); i2c_send(16,0,0x844,0x0000,0); // start address for channel 0?
			i2c_send(16,0,0x850,0x0000,0); i2c_send(16,0,0x845,0x0000,0); // start address for channel 1?

	i2c_send(0x850,~~0x0000~~); i2c_send(~~0x844~~,0x0000); // start address for channel 0?		i2c_send(16,0,0x850,0x0001,0); i2c_send(16,0,0x846,0x0000,0); // start address for channel 2?
	i2c_send(0x850,~~0x0000~~); i2c_send(~~0x845~~,0x0000); // start address for channel 1?		i2c_send(16,0,0x850,0x0001,0); i2c_send(16,0,0x847,0x0000,0); // start address for channel 3?

	i2c_send(0x850,~~0x0001~~); i2c_send(~~0x846~~,~~0x0000); // start address for channel 2?~~		i2c_send(16,0,0x850,0x0002,0); i2c_send(16,0,0x840,0xaaaa,0); // init to store channels parameters
	~~i2c_send(0x850~~,~~0x0001); i2c_send(0x847~~,~~0x0000~~); // ~~start address for channel 3?~~

	i2c_send(~~0x850~~,~~0x0002~~); i2c_send(~~0x840~~,~~0xaaaa~~); // ~~init to store channels parameters~~		i2c_send(16,0,0x809,3,0); // disable output + reset to all regs
			i2c_send(16,0,0x809,2,0); // disable output

	i2c_send(~~0x809~~,3); // ~~disable output + reset to all regs~~		i2c_send(16,0,0x815,0x0100,0); // set pause between lines for the 3rd frame
	i2c_send(~~0x809~~,2); // ~~disable output~~		i2c_send(16,0,0x816,0x0004,0); // set number of blank lines before the 3rd frame

	i2c_send(~~0x815~~,0x0100); // set pause between lines for the ~~3rd~~ frame		i2c_send(16,0,0x825,0x0100,0); // set pause between lines for the 2nd frame
	i2c_send(~~0x816~~,~~0x0002~~); // set number of blank lines before the ~~3rd~~ frame		i2c_send(16,0,0x826,0x0004,0); // set number of blank lines before the 2nd frame

	i2c_send(~~0x825~~,~~0x0100~~); // ~~set pause~~ between ~~lines for the 2nd frame~~		i2c_send(16,0,0x850,0x0000,0); // program the high part of the delay between frames from different channels
	i2c_send(~~0x826~~,~~0x0002~~); // set ~~number of blank lines before~~ the ~~2nd frame~~		i2c_send(16,0,0x80c,0x0000,0); // set the delay between frames from different channels to 0

	i2c_send(0x809,0x0004); // enable 'combined frame' mode		i2c_send(16,0,0x809,0x0004,0); // enable 'combined frame' mode

Oleg at 20:54, 7 May 2010

2010-05-07T20:54:08Z

← Older revision		Revision as of 20:54, 7 May 2010
Line 142:		Line 142:
	\| 0x806		\| 0x806
	\|		\|
	[2] - ~~enable~~ J4 ~~(ch2)~~		[5:4] - 2nd buffered channel, 0x0 - disabled?, 0x1 - J2, 0x2 - J3, 0x3 - J4

	[1] - ~~enable~~ J3 ~~(ch1)~~		[3:2] - 1st buffered channel, 0x0 - disabled?, 0x1 - J2, 0x2 - J3, 0x3 - J4

	[0] - ~~enable~~ J2 ~~(ch0)~~		[1:0] - direct channel, 0x0 - disabled?, 0x1 - J2, 0x2 - J3, 0x3 - J4
	\| switch direct channel		\| switch direct channel / channels order

	\|-		\|-
Line 180:		Line 180:
	\|-		\|-
	\| 0x813		\| 0x813
	\| default value:~~2592~~		\| default value:2596
	\| x size for read mcontr channel 1 (3rd frame)		\| x size for read mcontr channel 1 (3rd frame)

Line 200:		Line 200:
	\|-		\|-
	\| 0x823		\| 0x823
	\| default value:~~2592~~		\| default value:2596
	\| x size for read mcontr channel 3 (2nd frame)		\| x size for read mcontr channel 3 (2nd frame)

Line 282:		Line 282:
	i2c_send(0x809,3); // disable output + reset to all regs		i2c_send(0x809,3); // disable output + reset to all regs

	i2c_send(0x813,~~2592~~); // pixels in line for read the 3rd frame from channel 1 from SDRAM		i2c_send(0x813,2596); // pixels in line for read the 3rd frame from channel 1 from SDRAM
	i2c_send(0x814,~~2592~~); // number of lines for read the 3rd frame from channel 1 from SDRAM		i2c_send(0x814,1940); // number of lines for read the 3rd frame from channel 1 from SDRAM

	i2c_send(0x823,~~2592~~); // pixels in line for read the 2nd frame from channel 3 from SDRAM		i2c_send(0x823,2596); // pixels in line for read the 2nd frame from channel 3 from SDRAM
	i2c_send(0x824,~~2592~~); // number of lines for read the 2nd frame from channel 3 from SDRAM		i2c_send(0x824,1940); // number of lines for read the 2nd frame from channel 3 from SDRAM

	i2c_send(0x850,0x0001); i2c_send(0x840,0x5555); // init all mcontr channels		i2c_send(0x850,0x0001); i2c_send(0x840,0x5555); // init all mcontr channels

Oleg at 17:19, 7 May 2010

2010-05-07T17:19:58Z

← Older revision		Revision as of 17:19, 7 May 2010
Line 321:		Line 321:
	i2c_send(0x850,0x0001); i2c_send(0x846,0x0000); // start address for channel 2?		i2c_send(0x850,0x0001); i2c_send(0x846,0x0000); // start address for channel 2?
	i2c_send(0x850,0x0001); i2c_send(0x847,0x0000); // start address for channel 3?		i2c_send(0x850,0x0001); i2c_send(0x847,0x0000); // start address for channel 3?

	i2c_send(0x850,0x0002); i2c_send(0x840,0xaaaa); // init to store channels parameters		i2c_send(0x850,0x0002); i2c_send(0x840,0xaaaa); // init to store channels parameters

	i2c_send(0x809,3); // disable output + reset to all regs		i2c_send(0x809,3); // disable output + reset to all regs
	i2c_send(0x809,2); // disable output		i2c_send(0x809,2); // disable output

Oleg at 17:53, 6 May 2010

2010-05-06T17:53:06Z

← Older revision		Revision as of 17:53, 6 May 2010
Line 314:		Line 314:
	i2c_send(0x850,0x1c00); i2c_send(0x843,0x0c21); // don't remember		i2c_send(0x850,0x1c00); i2c_send(0x843,0x0c21); // don't remember

	//i2c_send(0x850,0x0001); i2c_send(0x840,0x5555); // ~~unexpected~~ init		i2c_send(0x850,0x0001); i2c_send(0x840,0x5555); // init to store channels parameters

	i2c_send(0x850,0x0000); i2c_send(0x844,0x0000); // start address for channel 0?		i2c_send(0x850,0x0000); i2c_send(0x844,0x0000); // start address for channel 0?
Line 321:		Line 321:
	i2c_send(0x850,0x0001); i2c_send(0x846,0x0000); // start address for channel 2?		i2c_send(0x850,0x0001); i2c_send(0x846,0x0000); // start address for channel 2?
	i2c_send(0x850,0x0001); i2c_send(0x847,0x0000); // start address for channel 3?		i2c_send(0x850,0x0001); i2c_send(0x847,0x0000); // start address for channel 3?

			i2c_send(0x850,0x0002); i2c_send(0x840,0xaaaa); // init to store channels parameters

	i2c_send(0x809,3); // disable output + reset to all regs		i2c_send(0x809,3); // disable output + reset to all regs
	i2c_send(0x809,2); // disable output		i2c_send(0x809,2); // disable output