Talk:USB FPGA CODE - Revision history

Andrey.filippov at 07:13, 7 November 2005

2005-11-07T07:13:17Z

← Older revision		Revision as of 07:13, 7 November 2005
Line 1:		Line 1:
	Below is just the discussion between --[[User:Andrey.filippov\|Andrey.filippov]] 22:46, 6 November 2005 (CST) and ~~Wensai~~		Below is just the discussion between --[[User:Andrey.filippov\|Andrey.filippov]] 22:46, 6 November 2005 (CST) Wensai and Dima

	I think it is possble.but need test.		I think it is possble.but need test.

Andrey.filippov at 06:52, 7 November 2005

2005-11-07T06:52:47Z

← Older revision		Revision as of 06:52, 7 November 2005
Line 174:		Line 174:

	To use the same I/O pins of the FPGA you need to modify just the top-level x333.v module where you add your module and connect these pins to it, just leaving the old destinations hanging.		To use the same I/O pins of the FPGA you need to modify just the top-level x333.v module where you add your module and connect these pins to it, just leaving the old destinations hanging.
			ver? can modify

			Unfortunately we will need to do it twice - for MJPEG and Theora separately. Let's start with MJPEG and the latest version of the Verilog files is in the CVS and current software distribution in fpga/x3x3 subdirectory.

			The only what is important - notify me so I will not overwrite your version. So far I was the only one working on the FPGA code.

			You will also need to work with Dima - he needs the same pins for lens control, so you two need to come to some agreed on usage - i.e. have some multiplexor in the FPGA code fro the pin functions.

			It will be a good Idea to keep the fresh information and the current usage of these pins on our wiki.elphel.com

	ver? can modify		ver? can modify

Andrey.filippov at 06:29, 7 November 2005

2005-11-07T06:29:36Z

← Older revision		Revision as of 06:29, 7 November 2005
Line 174:		Line 174:

	To use the same I/O pins of the FPGA you need to modify just the top-level x333.v module where you add your module and connect these pins to it, just leaving the old destinations hanging.		To use the same I/O pins of the FPGA you need to modify just the top-level x333.v module where you add your module and connect these pins to it, just leaving the old destinations hanging.
			ver? can modify

			Unfortunately we will need to do it twice - for MJPEG and Theora separately. Let's start with MJPEG and the latest version of the Verilog files is in the CVS and current software distribution in fpga/x3x3 subdirectory.

			The only what is important - notify me so I will not overwrite your version. So far I was the only one working on the FPGA code.

			You will also need to work with Dima - he needs the same pins for lens control, so you two need to come to some agreed on usage - i.e. have some multiplexor in the FPGA code fro the pin functions.

			It will be a good Idea to keep the fresh information and the current usage of these pins on our wiki.elphel.com

	ver? can modify		ver? can modify

Andrey.filippov at 04:53, 7 November 2005

2005-11-07T04:53:40Z

← Older revision		Revision as of 04:53, 7 November 2005
Line 58:		Line 58:

	To use the same I/O pins of the FPGA you need to modify just the top-level x333.v module where you add your module and connect these pins to it, just leaving the old destinations hanging.		To use the same I/O pins of the FPGA you need to modify just the top-level x333.v module where you add your module and connect these pins to it, just leaving the old destinations hanging.


			I think it is possble.but need test.

			But this is a goal

			You may use just 2 - 0 and 90, and then just put:

			always @ (posedge clk90)

			always @ (negedge clk90)

			Because now I don't remember if all 4 are actually present on chip.

			Maybe it is just 0, 90, 270? or 0, 90, 180 - just don't remember.

			Also the interface to the CPU shoul be consistent with the current one, and not use large address space - just

			It is possible to use interrupts, yes. How many bits?

			We can add more - anyway date is read in in 32 bit words.

			8 was selected fro vector interrupts, but now it is not used as there were some problems with ETRAX software. We should probably restore vector interrupt functionality as there are too many different sources for the interrupts now. Use INTA to put 8 bit on the bus.

			interrupts no use state words?
			I think beterr use state word register?

			Now most are how they are just by historical reasons. There is already a mess, but it should be fixed from both sides - software driver and ISR, and FPGA.

			But first we need to make sure that vector interrupts now work with ETRAX as expected, then modify the FPGA code and drivers to use it. I had vector interrupts even in model 303 camera, but later removed it having problem with it in software. Some problems were gone wiyth newer kernel but I haven't restored vector interrupts back.


			The interrupts mask and other register is 8 bit, I want modi to 16 bit,ok?

			I don't think it is really necessary, what we can do is just have a single (vector) interrupt for USB and have a separate 5-bit register in your module that will be polled to find out the exact source of the interrupt.

			Use a single (vector) interrupt

			For now - just have a single (1-bit) line and your register. We will have to change current 1-interrupt module to vector interrupts anyway. And for that we have just 8 bits, but you will use just 1.

			So we can work independently

			You may use bit 5, but it is easy to change. You see there are now 2 different code bases for 333 - with MJPEG and Ogg Theora, I will need to verify that the same number is free in both.

			I need repair the device program.how to work?
			I konw to do,but do not know tell who.

			Do you mean software driver?

			OK - We can discuss that online, I believe Mikhail (Spectr) is the best person to work on it.

			We also need to find out what exactly registers do you need to be ablle to read/write (in FPGA sysinterface) fro the USB module. I suggest using minimal address space - fro writing - just 2 registers - address and data, how I use it now. Also reading data from the FPGA to CPU is rather time-critical, so the best is to have it registered after your multixor, so there will be a single 32-bit read form the register.
			Other thing - normally (withe 0 wait states) ETRA{ does not provide means to know there was a read (you can not distinguish between 1 or 2 consecutive reads (can not make autoincrementing of the read address) so I use an extra CSP4 that has wait states and can be used with autoincrementing. It is how now reading of the blockRAM (SDRAM channel 3) is made. So you may just look at the code and ask more questions.

			Does it make sense or I'm not clear enough?

			the FPGA and software driver need remove old port and old-port device programm .Whose ver can I modify?

			To use the same I/O pins of the FPGA you need to modify just the top-level x333.v module where you add your module and connect these pins to it, just leaving the old destinations hanging.
			I think it is possble.but need test.

			But this is a goal

			You may use just 2 - 0 and 90, and then just put:

			always @ (posedge clk90)

			always @ (negedge clk90)

			Because now I don't remember if all 4 are actually present on chip.

			Maybe it is just 0, 90, 270? or 0, 90, 180 - just don't remember.

			Also the interface to the CPU shoul be consistent with the current one, and not use large address space - just

			It is possible to use interrupts, yes. How many bits?

			We can add more - anyway date is read in in 32 bit words.

			8 was selected fro vector interrupts, but now it is not used as there were some problems with ETRAX software. We should probably restore vector interrupt functionality as there are too many different sources for the interrupts now. Use INTA to put 8 bit on the bus.

			interrupts no use state words?
			I think beterr use state word register?

			Now most are how they are just by historical reasons. There is already a mess, but it should be fixed from both sides - software driver and ISR, and FPGA.

			But first we need to make sure that vector interrupts now work with ETRAX as expected, then modify the FPGA code and drivers to use it. I had vector interrupts even in model 303 camera, but later removed it having problem with it in software. Some problems were gone wiyth newer kernel but I haven't restored vector interrupts back.


			The interrupts mask and other register is 8 bit, I want modi to 16 bit,ok?

			I don't think it is really necessary, what we can do is just have a single (vector) interrupt for USB and have a separate 5-bit register in your module that will be polled to find out the exact source of the interrupt.

			Use a single (vector) interrupt

			For now - just have a single (1-bit) line and your register. We will have to change current 1-interrupt module to vector interrupts anyway. And for that we have just 8 bits, but you will use just 1.

			So we can work independently

			You may use bit 5, but it is easy to change. You see there are now 2 different code bases for 333 - with MJPEG and Ogg Theora, I will need to verify that the same number is free in both.

			I need repair the device program.how to work?
			I konw to do,but do not know tell who.

			Do you mean software driver?

			OK - We can discuss that online, I believe Mikhail (Spectr) is the best person to work on it.

			We also need to find out what exactly registers do you need to be ablle to read/write (in FPGA sysinterface) fro the USB module. I suggest using minimal address space - fro writing - just 2 registers - address and data, how I use it now. Also reading data from the FPGA to CPU is rather time-critical, so the best is to have it registered after your multixor, so there will be a single 32-bit read form the register.
			Other thing - normally (withe 0 wait states) ETRA{ does not provide means to know there was a read (you can not distinguish between 1 or 2 consecutive reads (can not make autoincrementing of the read address) so I use an extra CSP4 that has wait states and can be used with autoincrementing. It is how now reading of the blockRAM (SDRAM channel 3) is made. So you may just look at the code and ask more questions.

			Does it make sense or I'm not clear enough?

			the FPGA and software driver need remove old port and old-port device programm .Whose ver can I modify?

			To use the same I/O pins of the FPGA you need to modify just the top-level x333.v module where you add your module and connect these pins to it, just leaving the old destinations hanging.
			ver? can modify

			Unfortunately we will need to do it twice - for MJPEG and Theora separately. Let's start with MJPEG and the latest version of the Verilog files is in the CVS and current software distribution in fpga/x3x3 subdirectory.

			The only what is important - notify me so I will not overwrite your version. So far I was the only one working on the FPGA code.

			You will also need to work with Dima - he needs the same pins for lens control, so you two need to come to some agreed on usage - i.e. have some multiplexor in the FPGA code fro the pin functions.

			It will be a good Idea to keep the fresh information and the current usage of these pins on our wiki.elphel.com

Andrey.filippov at 04:46, 7 November 2005

2005-11-07T04:46:58Z

New page

Below is just the discussion between --[[User:Andrey.filippov|Andrey.filippov]] 22:46, 6 November 2005 (CST) and Wensai

I think it is possble.but need test.

But this is a goal

You may use just 2 - 0 and 90, and then just put:

always @ (posedge clk90)

always @ (negedge clk90)

Because now I don't remember if all 4 are actually present on chip.

Maybe it is just 0, 90, 270? or 0, 90, 180 - just don't remember.

Also the interface to the CPU shoul be consistent with the current one, and not use large address space - just

It is possible to use interrupts, yes. How many bits?

We can add more - anyway date is read in in 32 bit words.

8 was selected fro vector interrupts, but now it is not used as there were some problems with ETRAX software. We should probably restore vector interrupt functionality as there are too many different sources for the interrupts now. Use INTA to put 8 bit on the bus.

interrupts no use state words?
I think beterr use state word register?

Now most are how they are just by historical reasons. There is already a mess, but it should be fixed from both sides - software driver and ISR, and FPGA.

But first we need to make sure that vector interrupts now work with ETRAX as expected, then modify the FPGA code and drivers to use it. I had vector interrupts even in model 303 camera, but later removed it having problem with it in software. Some problems were gone wiyth newer kernel but I haven't restored vector interrupts back.

The interrupts mask and other register is 8 bit, I want modi to 16 bit,ok?

I don't think it is really necessary, what we can do is just have a single (vector) interrupt for USB and have a separate 5-bit register in your module that will be polled to find out the exact source of the interrupt.

Use a single (vector) interrupt

For now - just have a single (1-bit) line and your register. We will have to change current 1-interrupt module to vector interrupts anyway. And for that we have just 8 bits, but you will use just 1.

So we can work independently

You may use bit 5, but it is easy to change. You see there are now 2 different code bases for 333 - with MJPEG and Ogg Theora, I will need to verify that the same number is free in both.

I need repair the device program.how to work?
I konw to do,but do not know tell who.

Do you mean software driver?

OK - We can discuss that online, I believe Mikhail (Spectr) is the best person to work on it.

We also need to find out what exactly registers do you need to be ablle to read/write (in FPGA sysinterface) fro the USB module. I suggest using minimal address space - fro writing - just 2 registers - address and data, how I use it now. Also reading data from the FPGA to CPU is rather time-critical, so the best is to have it registered after your multixor, so there will be a single 32-bit read form the register.
Other thing - normally (withe 0 wait states) ETRA{ does not provide means to know there was a read (you can not distinguish between 1 or 2 consecutive reads (can not make autoincrementing of the read address) so I use an extra CSP4 that has wait states and can be used with autoincrementing. It is how now reading of the blockRAM (SDRAM channel 3) is made. So you may just look at the code and ask more questions.

Does it make sense or I'm not clear enough?

the FPGA and software driver need remove old port and old-port device programm .Whose ver can I modify?

To use the same I/O pins of the FPGA you need to modify just the top-level x333.v module where you add your module and connect these pins to it, just leaving the old destinations hanging.