USB FPGA CODE - Revision history

Dimon: /* FPGA code to accomodate USB host module */

2005-12-16T11:36:58Z

FPGA code to accomodate USB host module

← Older revision		Revision as of 11:36, 16 December 2005
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	See discussion also		See discussion also
	==FPGA code to accomodate USB host module==		==FPGA code to accomodate USB host module==
	The code of the JPEG branch of the model 333 camera is modified (in rev 333100e) to accomodate new USB host module currently under development. These modifications also provide vector interrupts (from up to 16 sources) and simplifies the use of 6 FPGA pins connected to the inter-~~baord~~ connector J2 (and so available at the extension boards).		The code of the JPEG branch of the model 333 camera is modified (in rev 333100e) to accomodate new USB host module currently under development. These modifications also provide vector interrupts (from up to 16 sources) and simplifies the use of 6 FPGA pins connected to the inter-board connector J2 (and so available at the extension boards).

	===Vector Interrupts===		===Vector Interrupts===

Andrey.filippov: /* I/O pins control */

2005-12-14T23:51:38Z

I/O pins control

← Older revision		Revision as of 23:51, 14 December 2005
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	=== I/O pins control ===		=== I/O pins control ===
	FPGA on the model 333 main board traditionally has 6 pins connected to the inter-board 16-pin connector J2. "Traditionally" because the same pins were used in earlier models 303 and 313. Previously these pins were designated for the particular functions, but it turned out that it is more convinient to have a uniform interface to control all of them. State (0/1) of each pin can be read by software as a 6-bit word at address 0x70, each pin can individually and dynamically be programmed as an output and output particular bit.		FPGA on the model 333 main board traditionally has 6 pins connected to the inter-board 16-pin connector J2. "Traditionally" because the same pins were used in earlier models 303 and 313. Previously these pins were designated for the particular functions, but it turned out that it is more convinient to have a uniform interface to control all of them. State (0/1) of each pin can be read by software as a 6-bit word at address 0x70, each pin can individually and dynamically be programmed as an input or an output and in the latter case output particular bit.

	In addition to per-bit software control of the I/O pins the six_ios module also can delegate direct control to one of 3 possible FPGA additionlal modules, currently USB host interface is under development.		In addition to per-bit software control of the I/O pins the six_ios module also can delegate direct control to one of 3 possible FPGA additionlal modules, currently USB host interface is under development.

Andrey.filippov: /* I/O pins control */

2005-12-14T23:50:20Z

I/O pins control

← Older revision		Revision as of 23:50, 14 December 2005
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			Output functions of these pins are controlled by writing a 14-bit to location 0x70 in the FPGA address space. Two MSBs (13:12) control the multiplexer that selects the source of the pin control:

	// ~~those~~ pins ~~were~~ controlled (~~in models 303~~, ~~313~~, ~~323 and earlier 333~~) by ~~the control register, status was~~		0 - I/O pins are controlled by buts [11:0] of the same control word
	/~~/ read through the status register.~~		1 - I/O pins are controlled by source "A" - USB module. Two sets of 6-bit data buses are provide - one - for per-bit direction (0 - input, 1 - output), the other - for the value (disregarded in input mode).
			2 - I/O pins are controlled by source "B" (not assigned yet)
			3 - I/O pins are controlled by source "C" (not assigned yet)

	~~// Now~~ each ~~pin will be controlled by 2 bits~~ (~~data+enable), total 12 bits~~ that ~~will come from one of 4 sources~~		Lower significant bits make pairs that control each individual pins (provided that bits 12 and 13 are both zeros - see above). In each pair the lower bit provides the pin value (output mode only), the higher - pin direction (0-input), 1 - output.
	~~// selected by~~ bits [13~~:12] of~~ the ~~new control word:~~
	~~// 0 - use bits [11:0] of~~ the ~~control word~~
	~~// 1 - use channel A~~ (~~USB~~)?
	~~// 2~~ - ~~use channel B~~ (~~tbd~~)
	~~// 3~~ - ~~use channel C (tbd)~~

	// 1 - SDA1		So writing 0x1000 selects USB as a source (12 LSBs are ignored), 0xb will program pin 0 (SCL1) to output "1", pin 1 (SDA1) - to output "0", all the rest pins will be used as inputs.
	~~// 2~~ - ~~XRST~~
	~~// 3 - AUXCLK~~
	~~// 4 - EXPS~~		Reading from address 0x70 will return current state or the pins as a 6-bit word in any mode.
	~~// 5~~ - ~~TRIG~~

Andrey.filippov: /* I/O pins control */

2005-12-14T23:27:51Z

I/O pins control

← Older revision		Revision as of 23:27, 14 December 2005
Line 72:		Line 72:

	=== I/O pins control ===		=== I/O pins control ===
	FPGA on the model 333 main board traditionally has 6 pins connected to the inter-board 16-pin connector. "Traditionally" because the same pins were used in earlier models 303 and 313. Previously these pins were designated for the particular functions, but it turned out that it is more convinient to have a uniform interface to control all of them. State (0/1) of each pin can be read by software as a 6-bit word at address 0x70, each pin can individually and dynamically be programmed as an output and output particular bit.		FPGA on the model 333 main board traditionally has 6 pins connected to the inter-board 16-pin connector J2. "Traditionally" because the same pins were used in earlier models 303 and 313. Previously these pins were designated for the particular functions, but it turned out that it is more convinient to have a uniform interface to control all of them. State (0/1) of each pin can be read by software as a 6-bit word at address 0x70, each pin can individually and dynamically be programmed as an output and output particular bit.

	In addition to per-bit software control of the I/O pins the six_ios module also can delegate direct control to one of 3 possible FPGA additionlal modules, currently USB host interface is under development.		In addition to per-bit software control of the I/O pins the six_ios module also can delegate direct control to one of 3 possible FPGA additionlal modules, currently USB host interface is under development.

Andrey.filippov at 23:27, 14 December 2005

2005-12-14T23:27:26Z

@@ Line 75: / Line 75: @@
 In addition to per-bit software control of the I/O pins the six_ios module also can delegate direct control to one of 3 possible FPGA additionlal modules, currently USB host interface is under development.
 // those pins were controlled (in models 303, 313, 323 and earlier 333) by the control register, status was
 // read through the status register.

Andrey.filippov: /* I/O pins control */

2005-12-14T23:19:51Z

I/O pins control

← Older revision		Revision as of 23:19, 14 December 2005
Line 72:		Line 72:

	=== I/O pins control ===		=== I/O pins control ===
			FPGA on the model 333 main board traditionally has 6 pins connected to the inter-board 16-pin connector. "Traditionally" because the same pins were used in earlier models 303 and 313. Previously these pins were designated for the particular functions, but it turned out that it is more convinient to have a uniform interface to control all of them. State (0/1) of each pin can be read by software as a 6-bit word at address 0x70, each pin can individually and dynamically be programmed as an output and output particular bit.

			In addition to per-bit software control of the I/O pins the six_ios module also can delegate direct control to one of 3 possible FPGA additionlal modules, currently USB host interface is under development.
			// those pins were controlled (in models 303, 313, 323 and earlier 333) by the control register, status was
			// read through the status register.

			// Now each pin will be controlled by 2 bits (data+enable), total 12 bits that will come from one of 4 sources
			// selected by bits [13:12] of the new control word:
			// 0 - use bits [11:0] of the control word
			// 1 - use channel A (USB)?
			// 2 - use channel B (tbd)
			// 3 - use channel C (tbd)

			// 1 - SDA1
			// 2 - XRST
			// 3 - AUXCLK
			// 4 - EXPS
			// 5 - TRIG

Andrey.filippov: /* Reading Interrupt Status */

2005-12-14T22:59:38Z

Reading Interrupt Status

← Older revision		Revision as of 22:59, 14 December 2005
Line 69:		Line 69:
	The lower 16 bits are masked interrupt requests - those that OR-ed define the interrupt request to the CPU.		The lower 16 bits are masked interrupt requests - those that OR-ed define the interrupt request to the CPU.

	The 16 highest bits are the same interrupt bits before the mask, so ~~it includes~~ all the bits in the lower 16 and possiblyy some other interrupt bits that are triggered but masked out.		The 16 highest bits are the same interrupt bits before the mask, so they are set for all the same bits in the lower 16 and possiblyy some other interrupt bits that are triggered but masked out.

	=== I/O pins control ===		=== I/O pins control ===

Andrey.filippov: /* Reading Interrupt Status */

2005-12-14T22:58:36Z

Reading Interrupt Status

← Older revision		Revision as of 22:58, 14 December 2005
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	==== Reading Interrupt Status ====		==== Reading Interrupt Status ====
	It is possible to read the current state of all 16 possible interrupts throuhg the 32-bit register		It is possible to read the current state of all 16 possible interrupts throuhg the 32-bit register
	#define X313__RA__IRQS 0x11 // read interrupt register		#define X313__RA__IRQS 0x11 // read interrupt register
	The lower 16 bits are masked interrupt requests - those that OR-ed define the interrupt request to the CPU.		The lower 16 bits are masked interrupt requests - those that OR-ed define the interrupt request to the CPU.

Andrey.filippov: /* Interrupt Map */

2005-12-14T22:58:04Z

Interrupt Map

← Older revision		Revision as of 22:58, 14 December 2005
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	\|}		\|}

			==== Reading Interrupt Status ====
			It is possible to read the current state of all 16 possible interrupts throuhg the 32-bit register
			#define X313__RA__IRQS 0x11 // read interrupt register
			The lower 16 bits are masked interrupt requests - those that OR-ed define the interrupt request to the CPU.

			The 16 highest bits are the same interrupt bits before the mask, so it includes all the bits in the lower 16 and possiblyy some other interrupt bits that are triggered but masked out.

	=== I/O pins control ===		=== I/O pins control ===

Andrey.filippov at 22:50, 14 December 2005

2005-12-14T22:50:28Z

← Older revision		Revision as of 22:50, 14 December 2005
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	\|}		\|}

			=== I/O pins control ===