Difference between revisions of "Trigger 353"
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Master | Master | ||
* TRIG_OUT=0x80000 (J12) | * TRIG_OUT=0x80000 (J12) | ||
| − | * set the TRIG_PERIOD=0x5B8D800 (=96000000, =1sec =1fps) | + | * set the TRIG_PERIOD=0x5B8D800 (=96000000 dec, =1sec =1fps) |
* TRIG_CONDITION=0x20000 | * TRIG_CONDITION=0x20000 | ||
* TRIG=0x4 | * TRIG=0x4 | ||
| Line 110: | Line 110: | ||
* TRIG_OUT=0x80000 | * TRIG_OUT=0x80000 | ||
| − | * set the TRIG_PERIOD=0x5B8D800 (=96000000, =1sec =1fps) | + | * set the TRIG_PERIOD=0x5B8D800 (=96000000 dec, =1sec =1fps) |
* TRIG_CONDITION=0x20000 (J14) | * TRIG_CONDITION=0x20000 (J14) | ||
* TRIG=0x4 | * TRIG=0x4 | ||
Revision as of 11:08, 18 January 2016
Contents
Description
10369 board is required.
The triggering is used for one or several cameras synchronization or setting the Frame Rate (or FPS). The conditions of the trigger can be generated either internally or externally. For external triggering a phone cable with RJ14 is used. To program trigger go to: http://192.168.0.9/parsedit.php -> External Trigger Controls
Note!
Be careful with changing parameters when TRIG=4. Camera drivers are driven by the frame sync interrupts from the sensor, so if the sensor is not triggered - everything can get stuck. The Program Ahead value sets the number of frame sync interrupts the camera will wait wait for until a parameter is reprogrammed.
Parameters
| parameter | description |
| TRIG | Trigger mode enable. Currently 0 - free running, 4 - triggered by external signal or internal FPGA timing generator. |
| TRIG_PERIOD | FPGA trigger sequencer output sync period (32 bits, in pixel clocks). 0- stop. 1 - single, >=256 repetitive with specified period (values 2..255 are reserved for programming timestamp communication) |
| TRIG_DELAY | FPGA trigger sequencer trigger delay, 32 bits in pixel clocks |
| EARLY_TIMESTAMP | When 0 - frame sync (start of the frame readout) will be used for timestamping of the images, when 1 and the trigger mode is external (physically external to the camera or just when sensor runs from the FPGA timing generator) the start of exposure will be used for time stamping (exposure time earlier). This is the default mode to prevent recorded frame period jitter caused by automatic exposure adjustments |
| TRIG_CONDITION | FPGA trigger sequencer trigger condition, 0 - internal, else dibits ((use<<1) | level) for each GPIO[11:0] pin). Example:0x200000 - input from external connector (J15 - http://wiki.elphel.com/index.php?title=10369#J15_-_SYNC_.28external.29 ), 0x20000 - input from internal (J13/J14 - http://wiki.elphel.com/index.php?title=10369#J13_-_SYNC_.28internal.2C_slave.29 ) |
| TRIG_OUT | level_when_active). Bit 24 - test mode, when GPIO[11:10] are controlled by other internal signals. Example: 0x800000 - output to external (J15 - http://wiki.elphel.com/index.php?title=10369#J15_-_SYNC_.28external.29 ) connector, 0x80000 - to internal (J12 - http://wiki.elphel.com/index.php?title=10369#J12_-_SYNC_.28internal.2C_master.29 ) |
Single frame triggering from PC
Enable
http://192.168.0.9:8081/trig/pointers
- TRIG=4 should be set in advance
- The command automatically sets a single-shot trigger mode with TRIG_PERIOD=0x1, but it writes the register directly into the FPGA,
not updating the TRIG_PERIOD in the PHP interface:
http://192.168.0.9/parsedit.php?TRIG&TRIG_CONDITION&TRIG_DELAY&TRIG_OUT&TRIG_PERIOD&TRIG_BITLENGTH&EXTERN_TIMESTAMP&XMIT_TIMESTAMP&IRQ_SMART&refresh
Trigger/Refresh
http://192.168.0.9:8081/trig/pointers
Status
http://192.168.0.9/parsedit.php?immediate&TRIG&TRIG_PERIOD&IRQ_SMART&SENS_AVAIL&FRAME
Disable
- Update the TRIG_PERIOD in the PHP interface - or simply check the box and hit Apply:
http://192.168.0.9/parsedit.php?TRIG&TRIG_CONDITION&TRIG_DELAY&TRIG_OUT&TRIG_PERIOD&TRIG_BITLENGTH&EXTERN_TIMESTAMP&XMIT_TIMESTAMP&IRQ_SMART&refresh
- Refresh until the changes are applied (with Program Ahead = 3 it's 3 times):
http://192.168.0.9:8081/trig/pointers
Examples
Before setting trigger options it's better not to launch the Camera Control Interface after booting. Go straight to Parameter Editor.
Internal (from fpga generator)
- TRIG_CONDITION=0x0
- set the TRIG_PERIOD
- TRIG=0x4
OR
- set the TRIG_PERIOD
- http://192.168.0.9/sync.php?role=detect&channel=internal
Internal (from fpga generator) + output the trigger signal
- TRIG_CONDITION=0x0
- set the TRIG_PERIOD
- TRIG=0x4
- TRIG_OUT=0x800000
External (J15)
Receive: GPIO[10] needs to be configured to receive the trigger signal -
- TRIG_OUT=0x800000
- set the TRIG_PERIOD=0x5B8D800 (=96000000, =1sec= 1fps)
- TRIG_CONDITION=0x200000
- TRIG=0x4
Generate: GPIO[11] needs to be programmed - set TRIG_OUT=0x800000
Notes: TRIG_CONDITION: a 22-bit register where 2 bits are used for programming each GPIO (from 0 to 11, e.g., TRIG_CONDITION[1:0] will program GPIO[0]) - MSB enables input and LSB selects active trigger signal level. TRIG_OUT: Same as in TRIG_CONDITION register - MSB enables and LSB selects level.
OR
GPIO[11] & GPIO[10] can be set by following http://192.168.0.9/sync.php?role=detect&channel=external
External (J12-J14)
Master
- TRIG_OUT=0x80000 (J12)
- set the TRIG_PERIOD=0x5B8D800 (=96000000 dec, =1sec =1fps)
- TRIG_CONDITION=0x20000
- TRIG=0x4
Slave
- TRIG_OUT=0x80000
- set the TRIG_PERIOD=0x5B8D800 (=96000000 dec, =1sec =1fps)
- TRIG_CONDITION=0x20000 (J14)
- TRIG=0x4
