Difference between revisions of "Load custom bitstream"

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(Created page with "==from u-boot== ==from OS== Category:393")
 
 
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==from u-boot==
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==Description==
−
==from OS==
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The default bitstream is loaded from OS not from u-boot.
 +
 
 +
Reasons:
 +
* Different banks have different (software controlled and regulated) voltages and they need to be set up before loading.
 +
** voltages are set by the software through i2c
 +
 
 +
==Bitstreams paths==
 +
* Location on target system: ''/usr/local/verilog/''
 +
{| class='wikitable'
 +
! name
 +
! project
 +
! description
 +
|-
 +
|x393_parallel.bit
 +
|[https://git.elphel.com/Elphel/x393 x393]
 +
|for 5MPix sensor with parallel interface + SATA
 +
|-
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|x393_hispi.bit
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|[https://git.elphel.com/Elphel/x393 x393]
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|for 14MPix sensor with serial interface + SATA
 +
|-
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|x393_sata.bit
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|[https://git.elphel.com/Elphel/x393_sata x393_sata]
 +
|SATA only
 +
|-
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|x359.bit
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|[https://git.elphel.com/Elphel/x359 x359]
 +
|for external MUX 3-to-1 board
 +
|}
 +
 
 +
==Init==
 +
* '''detect_sensors''' driver reads the device tree to get the default system configuration which gets later updated by '''autocampars''' application
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* /etc/init.d/init_elphel393
 +
...
 +
$CONFDIR/init_elphel393.py "{\"usb_hub\":1, \"ip\":1,\"imgsrv\":1, \"autoexp_daemon\":1, \"autocampars\":1, \"sata\":1, \"gps\":1, \"eyesis\":0 }"
 +
...
 +
** in this line the extra init procedures are listed, to disable/skip certain procedure set 0, to enable - set 1
 +
** everything is done in ''/etc/elphel393/init_elphel393.py'' which runs other scripts.
 +
** the bitstream is loaded by '''autocampars''' or '''sata''' (if autocampars is skipped)
 +
 
 +
===autocampars===
 +
* project: [https://git.elphel.com/Elphel/elphel-apps-autocampars elphel-apps-autocampars]
 +
* top script: '''autocampars.php'''
 +
** Location on target system: ''/usr/bin/''
 +
** loads ''/usr/local/verilog/x359.bit'' to the external MUX board
 +
** depending on configuration (determined in init_elphel393.py) calls '''/usr/bin/autocampars.py''' with arguments listed in the files in ''/usr/local/verilog''. The default one is ''/usr/local/verilog/hargs'':
 +
-d TARGET_MODE=1
 +
-f /usr/local/verilog/system_defines.vh
 +
-f /usr/local/verilog/x393_parameters.vh  /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh
 +
-l /usr/local/verilog/x393_cur_params_target.vh
 +
-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
 +
-c bitstream_set_path /usr/local/verilog/x393_parallel.bit
 +
-c setupSensorsPower  "PAR12"  all  0  0.1
 +
-c measure_all "*DI"
 +
-c setSensorClock 24.0 "2V5_LVDS"
 +
-c set_rtc
 +
 
 +
The file with arguments can be found in the fpga projects, example:
 +
https://git.elphel.com/Elphel/x393/tree/master/py393
 +
Location on target system: ''/usr/local/verilog/''
 +
 
 +
===sata===
 +
* project [https://git.elphel.com/Elphel/x393_sata x393_sata]
 +
* Location on target system: ''/usr/local/verilog/''
 +
* '''/usr/local/bin/x393sata.py''' loads it default bitstream if fpga has not been programmed yet.
 +
...
 +
DEFAULT_BITFILE="/usr/local/verilog/x393_sata.bit"
 +
...
 +
 
 
[[Category:393]]
 
[[Category:393]]

Latest revision as of 13:50, 20 April 2017

Description

The default bitstream is loaded from OS not from u-boot.

Reasons:

  • Different banks have different (software controlled and regulated) voltages and they need to be set up before loading.
    • voltages are set by the software through i2c

Bitstreams paths

  • Location on target system: /usr/local/verilog/
name project description
x393_parallel.bit x393 for 5MPix sensor with parallel interface + SATA
x393_hispi.bit x393 for 14MPix sensor with serial interface + SATA
x393_sata.bit x393_sata SATA only
x359.bit x359 for external MUX 3-to-1 board

Init

  • detect_sensors driver reads the device tree to get the default system configuration which gets later updated by autocampars application
  • /etc/init.d/init_elphel393
...
$CONFDIR/init_elphel393.py "{\"usb_hub\":1, \"ip\":1,\"imgsrv\":1, \"autoexp_daemon\":1, \"autocampars\":1, \"sata\":1, \"gps\":1, \"eyesis\":0 }"
...
    • in this line the extra init procedures are listed, to disable/skip certain procedure set 0, to enable - set 1
    • everything is done in /etc/elphel393/init_elphel393.py which runs other scripts.
    • the bitstream is loaded by autocampars or sata (if autocampars is skipped)

autocampars

  • project: elphel-apps-autocampars
  • top script: autocampars.php
    • Location on target system: /usr/bin/
    • loads /usr/local/verilog/x359.bit to the external MUX board
    • depending on configuration (determined in init_elphel393.py) calls /usr/bin/autocampars.py with arguments listed in the files in /usr/local/verilog. The default one is /usr/local/verilog/hargs:
-d TARGET_MODE=1
-f /usr/local/verilog/system_defines.vh
-f /usr/local/verilog/x393_parameters.vh   /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh
-l /usr/local/verilog/x393_cur_params_target.vh
-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
-c bitstream_set_path /usr/local/verilog/x393_parallel.bit
-c setupSensorsPower  "PAR12"  all  0  0.1
-c measure_all "*DI"
-c setSensorClock 24.0 "2V5_LVDS"
-c set_rtc

The file with arguments can be found in the fpga projects, example: 

https://git.elphel.com/Elphel/x393/tree/master/py393

Location on target system: /usr/local/verilog/

sata

  • project x393_sata
  • Location on target system: /usr/local/verilog/
  • /usr/local/bin/x393sata.py loads it default bitstream if fpga has not been programmed yet.
...
DEFAULT_BITFILE="/usr/local/verilog/x393_sata.bit"
...
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