Difference between revisions of "USB FPGA CODE"

Revision as of 14:19, 14 December 2005

See discussion also

FPGA code to accomodate USB host module

The code of the JPEG branch of the model 333 camera is modified (in rev 333100e) to accomodate new USB host module currently under development. These modifications also provide vector interrupts (from up to 16 sources) and simplifies the use of 6 FPGA pins connected to the inter-baord connector J2 (and so available at the extension boards).

Vector Interrupts

Axis ETRAX100LX processor [1] supports two modes for external interrupts - with internally generated vector number and with externally generated. In the latter case CPU generates INTA pulse and the peripheral places an 8-bit vector code on the data bus. New (>=333100e) FPGA code supports both modes, for each of 16 intrerrupts individual vector code can be programmed. Four locations in the FPGA address space (CSP0,CSP4) are writable to control interrupts_vector333 module:

Reset Interrupt Requests

 #define   X313_WA_IRQ_RST   0x1c // reset selected interrupt bits

This register resets the selected bits (having ones in a word written to this location) of the source interrupt request register that is positive edge triggered from asynchronous signal in FPGA and reset by either of two reasons:

• writing to the X313_WA_IRQ_RST (0x1c) register with ones in the bits to be reset and
• servicing thisinterrupt with externally generated vector number. When the INTA is generated the interrupt request bit that caused the interrupt (or at least the one which had it's number placed on data bus in responce to INTA) is reset so software does not need to do it again.

Interrupt MAsk Register

 #define   X313_WA_IRQ_DIS   0x1d // disable selected interrupt bits (mask)
 #define   X313_WA_IRQ_ENA   0x1e // enable selected interrupt bits

These two locations control the interrupt mask register. Ones written to X313_WA_IRQ_DIS disable propagation of the interrupt(s) in the selected bit(s), ones written to X313_WA_IRQ_ENA enable them. After initial FPGA configuration all the interrupts are disabled. Enabling and disabling individual interrupt bits do not change the status of the interrupt requests, so if the interrupt causing event happened while this interrupt was disabled (masked out) and enabled later, the interrupt request to the CPU will be generated.

Programming Interrupt Vectors

#define   X313_WA_IRQ_WVECT 0x1f // write vector number (in bits [0:7], [11:8] - interrupt number (0..15)

In responce to the INTA pulse from the CPU (it will be generated if "extrernally generated vector number" is selected) one of the 16 pre-programmed 8-bit vectors will be placed on the data bus. You need to initialize the vectors before using them, initially all vectors are zeros. To program particular interrupt vector you need to combine the 8-bit vector for the selected interrupt and the interrupt bit number (0..15) by shifting the latter left by 8 and writing the 12-bit result to X313_WA_IRQ_WVECT.

If more than 1 interrupt are active (not reset and not masked) the one with the lower number will have higher priority.

When servicing one of the simultaneously active interrupts only one will be reset by INTA (the one that is being served), so immidiately after returning from servicing one request, CPU will generate INTA to serve the next remaining one.

Interrupt Map

Currently the following interrupts exist in the FPGA code of the Model 333 camera

assign irq_in= {2'b0, // extra

               usb_irqs[5:0],            // generated in USB module (edge, low-to-high transitions)
               compressor_done_compress, // 7 - will go high after all data is sent out (reset by compressor)
               compressor_done_input,    // 6 - will go high after EOT and persist until DCT is enabled (reset by compressor)
               dcc_rdy,                  // 5 - obsolete in 333 - channel3 has 128 more dc coefficients (or some if the compression is finished)
               compressor_eot,           // 4 - compressor read in the last MCU (predictable time to end of transfer
               sr_sensortrig[2],         // 3 - (sync to pclk) - level, reset by writing to sensor triggering command register
               xfer_over_irq,            // 2 - (sync to pclk) - frame acquisition over
               trig_irq,                 // 1 - (sync to pclk) - external trigger
               vacts};                   // 0 - (sync to pclk) - frame sync

1. define X313_IR__VACT 0 // start of VACT pulse
2. define X313_IR__XINT 1 // external enterrupt
3. define X313_IR__XFEROVR 2 // DMA xfer over
4. define X313_IR__DONE 3 // DMA xfer over, persistent till reset through...
5. define X313_IR__EOT 4
6. define X313_IR__OVERRUN 5 // *** OBSOLETE ***
7. define X313_IR__DCC 5 // Next 128 16-bit DC components (and HF too) are ready (or the partial block - last in frame).