Difference between revisions of "USB FPGA CODE"

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See discussion also
 
See discussion also
 
==FPGA code to accomodate USB host module==
 
==FPGA code to accomodate USB host module==
−
The code of the JPEG branch of the model 333 camera is modified (in rev 333100e) to accomodate new USB host module currently under development. These modifications also provide vector interrupts (from up to 16 sources) and simplifies the use of 6 FPGA pins connected to the inter-baord connector J2 (and so available at the extension boards).
+
The code of the JPEG branch of the model 333 camera is modified (in rev 333100e) to accomodate new USB host module currently under development. These modifications also provide vector interrupts (from up to 16 sources) and simplifies the use of 6 FPGA pins connected to the inter-board connector J2 (and so available at the extension boards).
  
 
===Vector Interrupts===
 
===Vector Interrupts===
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{| border="1" cellpadding="2"
 
{| border="1" cellpadding="2"
 
|-
 
|-
−
| bit || FPGA || Driver  || Used? || Description
+
| bit || vector || FPGA || Driver  || Used? || Description
 
|-
 
|-
−
| 0 || vacts || VACT || Y || frame sync
+
| 0 || || vacts || VACT || Y || frame sync
 
|-
 
|-
−
| 1 || trig_irq || XINT || Y || external trigger
+
| 1 || || trig_irq || XINT ||N || external trigger
 
|-
 
|-
−
| 2 || xfer_over_irq || XFEROVR || Y || frame acquisition over
+
| 2 || || xfer_over_irq || XFEROVR || N || frame acquisition over
 
|-
 
|-
−
| 0 || vacts || VACT || Y || Frame Sync
+
| 3 || || sr_sensortrig[2] || DONE || N || level, reset by writing to sensor triggering command register (FPGA != driver!)
 
|-
 
|-
−
| 0 || vacts || VACT || Y || Frame Sync
+
| 4 || || compressor_eot || EOT || N || Frame Sync
 
|-
 
|-
−
| 0 || vacts || VACT || Y || Frame Sync
+
| 5 || || dcc_rdy || DCC || N || (Next 128 16-bit DC components (and HF too) are ready (or the partial block - last in frame).)
 
|-
 
|-
−
| 0 || vacts || VACT || Y || Frame Sync
+
| 6 || ||compressor_done_input || DONE_INPUT || N || will go high after EOT and persist until DCT is enabled (source reset by compressor)
 +
|-
 +
| 7 || ||compressor_done_compress || DONE_COMPRESS || Y || will go high after all data is sent out (source reset by compressor)
 +
|-
 +
| 8 || ||usb_irqs[0] || --- || N || USB interrupt 0
 +
|-
 +
| 9 || ||usb_irqs[1] || --- || N || USB interrupt 1
 +
|-
 +
|10 || ||usb_irqs[2] || --- || N || USB interrupt 2
 +
|-
 +
|11 || ||usb_irqs[3] || --- || N || USB interrupt 3
 +
|-
 +
|12 || ||usb_irqs[4] || --- || N || USB interrupt 4
 +
|-
 +
|13 || ||usb_irqs[5] || --- || N || USB interrupt 5
 +
|-
 +
|14 || || --- || --- || N || ---
 +
|-
 +
|15 || || --- || --- || N || ---
 +
|-
 +
|}
 +
 
 +
==== Reading Interrupt Status ====
 +
It is possible to read the current state of all 16 possible interrupts throuhg the 32-bit register
 +
#define X313__RA__IRQS  0x11    // read interrupt register
 +
The lower 16 bits are masked interrupt requests - those that OR-ed define the interrupt request to the CPU.
 +
 
 +
The 16 highest bits are the same interrupt bits before the mask, so they are set for all the same bits in the lower 16 and possiblyy some other interrupt bits that are triggered but masked out.
 +
 
 +
=== I/O pins control ===
 +
FPGA on the model 333 main board traditionally has 6 pins connected to the inter-board 16-pin connector J2. "Traditionally" because the same pins were used in earlier models 303 and 313. Previously these pins were designated for the particular functions, but it turned out that it is more convinient to have a uniform interface to control all of them. State (0/1) of each pin can be read by software as a 6-bit word at address 0x70, each pin can individually and dynamically be programmed as an input or an output and in the latter case output particular bit.
 +
 
 +
In addition to per-bit software control of the I/O pins the six_ios module also can delegate direct control to one of 3 possible FPGA additionlal modules, currently USB host interface is under development.
 +
{| border="1" cellpadding="2"
 +
|-
 +
| bit || FPGA name || PCB name|| conector (J2) pin
 +
|-
 +
| 0 || SCL1 || EXT_SCL || 1
 +
|-
 +
| 1 || SDA1 || EXT_SDA || 2
 +
|-
 +
| 2 || XRST || EXT_RST || 3
 +
|-
 +
| 3 || AUXCLK ||EXT_CLK || 4
 +
|-
 +
| 4 || EXPS ||EXT_EXPOS || 5
 +
|-
 +
| 5 || TRIG || EXT_TRIG || 6
 
|-
 
|-
 
|}
 
|}
  
 +
Output functions of these pins are controlled by writing a 14-bit to location 0x70 in the FPGA address space. Two MSBs (13:12) control the multiplexer that selects the source of the pin control:
 +
 +
0 - I/O pins are controlled by buts [11:0] of the same control word
 +
1 - I/O pins are controlled by source "A" - USB module. Two sets of 6-bit data buses are provide - one - for per-bit direction (0 - input, 1 - output), the other - for the value (disregarded in input mode).
 +
2 - I/O pins are controlled by source "B" (not assigned yet)
 +
3 - I/O pins are controlled by source "C" (not assigned yet)
 +
 +
Lower significant bits make pairs that control each individual pins (provided that bits 12 and 13 are both zeros - see above). In each pair the lower bit provides the pin value (output mode only), the higher - pin direction (0-input), 1 - output.
 +
 +
So writing 0x1000 selects USB as a source (12 LSBs are ignored), 0xb will program pin 0 (SCL1) to output "1", pin 1 (SDA1) - to output "0", all the rest pins will be used as inputs.
  
−
assign irq_in= {2'b0, // extra
 
−
                usb_irqs[5:0],            // generated in USB module (edge, low-to-high transitions)
 
−
                compressor_done_compress, // 7 - will go high after all data is sent out (reset by compressor)
 
−
                compressor_done_input,    // 6 - will go high after EOT and persist until DCT is enabled (reset by compressor)
 
−
                dcc_rdy,                  // 5 - obsolete in 333 - channel3 has 128 more dc coefficients (or some if the compression is finished)
 
−
                compressor_eot,          // 4 - compressor read in the last MCU (predictable time to end of transfer
 
−
                sr_sensortrig[2],        // 3 - (sync to pclk) - level, reset by writing to sensor triggering command register
 
−
                xfer_over_irq,            // 2 - (sync to pclk) - frame acquisition over
 
−
                trig_irq,                // 1 - (sync to pclk) - external trigger
 
−
                vacts};                  // 0 - (sync to pclk) - frame sync
 
  
−
#define X313_IR__VACT          0 // start of VACT pulse
+
Reading from address 0x70 will return current state or the pins as a 6-bit word in any mode.
−
#define X313_IR__XINT          1 // external enterrupt
 
−
#define X313_IR__XFEROVR      2 // DMA xfer over
 
−
#define X313_IR__DONE          3 // DMA xfer over, persistent till reset through...
 
−
#define X313_IR__EOT          4
 
−
#define X313_IR__OVERRUN      5 // *** OBSOLETE ***
 
−
#define X313_IR__DCC          5 // Next 128 16-bit DC components (and HF too) are ready (or the partial block - last in frame).
 

Latest revision as of 03:36, 16 December 2005

See discussion also

FPGA code to accomodate USB host module

The code of the JPEG branch of the model 333 camera is modified (in rev 333100e) to accomodate new USB host module currently under development. These modifications also provide vector interrupts (from up to 16 sources) and simplifies the use of 6 FPGA pins connected to the inter-board connector J2 (and so available at the extension boards).

Vector Interrupts

Axis ETRAX100LX processor [1] supports two modes for external interrupts - with internally generated vector number and with externally generated. In the latter case CPU generates INTA pulse and the peripheral places an 8-bit vector code on the data bus. New (>=333100e) FPGA code supports both modes, for each of 16 intrerrupts individual vector code can be programmed. Four locations in the FPGA address space (CSP0,CSP4) are writable to control interrupts_vector333 module:

Reset Interrupt Requests

 #define   X313_WA_IRQ_RST   0x1c // reset selected interrupt bits

This register resets the selected bits (having ones in a word written to this location) of the source interrupt request register that is positive edge triggered from asynchronous signal in FPGA and reset by either of two reasons:

  • writing to the X313_WA_IRQ_RST (0x1c) register with ones in the bits to be reset and
  • servicing thisinterrupt with externally generated vector number. When the INTA is generated the interrupt request bit that caused the interrupt (or at least the one which had it's number placed on data bus in responce to INTA) is reset so software does not need to do it again.

Interrupt MAsk Register

 #define   X313_WA_IRQ_DIS   0x1d // disable selected interrupt bits (mask)
 #define   X313_WA_IRQ_ENA   0x1e // enable selected interrupt bits

These two locations control the interrupt mask register. Ones written to X313_WA_IRQ_DIS disable propagation of the interrupt(s) in the selected bit(s), ones written to X313_WA_IRQ_ENA enable them. After initial FPGA configuration all the interrupts are disabled. Enabling and disabling individual interrupt bits do not change the status of the interrupt requests, so if the interrupt causing event happened while this interrupt was disabled (masked out) and enabled later, the interrupt request to the CPU will be generated.

Programming Interrupt Vectors

#define   X313_WA_IRQ_WVECT 0x1f // write vector number (in bits [0:7], [11:8] - interrupt number (0..15)

In responce to the INTA pulse from the CPU (it will be generated if "extrernally generated vector number" is selected) one of the 16 pre-programmed 8-bit vectors will be placed on the data bus. You need to initialize the vectors before using them, initially all vectors are zeros. To program particular interrupt vector you need to combine the 8-bit vector for the selected interrupt and the interrupt bit number (0..15) by shifting the latter left by 8 and writing the 12-bit result to X313_WA_IRQ_WVECT.

If more than 1 interrupt are active (not reset and not masked) the one with the lower number will have higher priority.

When servicing one of the simultaneously active interrupts only one will be reset by INTA (the one that is being served), so immidiately after returning from servicing one request, CPU will generate INTA to serve the next remaining one.

Interrupt Map

Currently the following interrupts exist in the FPGA code of the Model 333 camera

bit vector FPGA Driver Used? Description
0 vacts VACT Y frame sync
1 trig_irq XINT N external trigger
2 xfer_over_irq XFEROVR N frame acquisition over
3 sr_sensortrig[2] DONE N level, reset by writing to sensor triggering command register (FPGA != driver!)
4 compressor_eot EOT N Frame Sync
5 dcc_rdy DCC N (Next 128 16-bit DC components (and HF too) are ready (or the partial block - last in frame).)
6 compressor_done_input DONE_INPUT N will go high after EOT and persist until DCT is enabled (source reset by compressor)
7 compressor_done_compress DONE_COMPRESS Y will go high after all data is sent out (source reset by compressor)
8 usb_irqs[0] --- N USB interrupt 0
9 usb_irqs[1] --- N USB interrupt 1
10 usb_irqs[2] --- N USB interrupt 2
11 usb_irqs[3] --- N USB interrupt 3
12 usb_irqs[4] --- N USB interrupt 4
13 usb_irqs[5] --- N USB interrupt 5
14 --- --- N ---
15 --- --- N ---

Reading Interrupt Status

It is possible to read the current state of all 16 possible interrupts throuhg the 32-bit register 

#define X313__RA__IRQS  	0x11    // read interrupt register

The lower 16 bits are masked interrupt requests - those that OR-ed define the interrupt request to the CPU.

The 16 highest bits are the same interrupt bits before the mask, so they are set for all the same bits in the lower 16 and possiblyy some other interrupt bits that are triggered but masked out.

I/O pins control

FPGA on the model 333 main board traditionally has 6 pins connected to the inter-board 16-pin connector J2. "Traditionally" because the same pins were used in earlier models 303 and 313. Previously these pins were designated for the particular functions, but it turned out that it is more convinient to have a uniform interface to control all of them. State (0/1) of each pin can be read by software as a 6-bit word at address 0x70, each pin can individually and dynamically be programmed as an input or an output and in the latter case output particular bit.

In addition to per-bit software control of the I/O pins the six_ios module also can delegate direct control to one of 3 possible FPGA additionlal modules, currently USB host interface is under development.

bit FPGA name PCB name conector (J2) pin
0 SCL1 EXT_SCL 1
1 SDA1 EXT_SDA 2
2 XRST EXT_RST 3
3 AUXCLK EXT_CLK 4
4 EXPS EXT_EXPOS 5
5 TRIG EXT_TRIG 6

Output functions of these pins are controlled by writing a 14-bit to location 0x70 in the FPGA address space. Two MSBs (13:12) control the multiplexer that selects the source of the pin control:

0 - I/O pins are controlled by buts [11:0] of the same control word 1 - I/O pins are controlled by source "A" - USB module. Two sets of 6-bit data buses are provide - one - for per-bit direction (0 - input, 1 - output), the other - for the value (disregarded in input mode). 2 - I/O pins are controlled by source "B" (not assigned yet) 3 - I/O pins are controlled by source "C" (not assigned yet)

Lower significant bits make pairs that control each individual pins (provided that bits 12 and 13 are both zeros - see above). In each pair the lower bit provides the pin value (output mode only), the higher - pin direction (0-input), 1 - output.

So writing 0x1000 selects USB as a source (12 LSBs are ignored), 0xb will program pin 0 (SCL1) to output "1", pin 1 (SDA1) - to output "0", all the rest pins will be used as inputs.


Reading from address 0x70 will return current state or the pins as a 6-bit word in any mode.

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