Difference between revisions of "Porting Theora to 353 cameras"

Latest revision as of 06:16, 16 April 2008

Elphel model 333 cameras were able to encode and stream Ogg Theora with 6.3.9 firmware. However, this model is no longer produced by Elphel. The goal of this project is to use the full potential of 353 cameras (larger FPGA, faster CPU) in order to port the Ogg Theora feature on the new hardware. First, the camera should be able to upload small Theora clips via FTP.

Different solutions are possible as previously mentioned in the Theora page :

• Instantiate both the Theora compressor and the MJPEG compressor in the FPGA since the new Spartan 3E seems to be large enough to handle the two features.
• Replace the existing MJPEG compressor with the Theora compressor and implement software Theora to JPEG conversion if JPEG is needed.
• Replace the existing MJPEG compressor in the 353 camera with the Theora compressor and keep two configuration files on the camera filesystem (one for Theora the other for MJPEG). FPGA code could be changed at run-time according to the needs.

Dealing with the last solution seems to be a good start for this project as the other features mentioned can be added later. In all cases, both FPGA code and software code will need to be adapted.

The source code of this project is available at http://elphel.cvs.sourceforge.net/elphel/fpga/theora_353/

Hardware updates

Compressor

333 Theora design with the 2 stage compressor and the 8-channel memory controller

Replace the MJPEG compressor in the 353 with the 333 Theora compressor (333 Theora FPGA code). Maybe some adaptations need to be done within the Theora compressor itself. However, assuming that the compressor worked in 333 cameras a simple instantiation should suffice.

Memory controller

Replace the 4-channel memory controller with an 8 channel memory interface as in the 333 model in order to handle Theora specific data.

Sensor interface

sensorpix block must be adapted in order to provide a coherent interface between the memory controller and the sensor (channels 0 and 1)

System Interface

Adapt the system interface to assure communication between FPGA and its environment.

A feature of the system interface is to establish communication between the system CPU and the different blocks within the FPGA (compressor, memory controller etc). This is done by selecting a block with the address bus a[12:0] connected to the internal address bus ial[7:0]:

x353.v
always @ (posedge cwr) begin
   a0[7:0]<=ial[7:0];  // may want to change to just ia if ia will be late enough;
   wnr0                <= ~irnw;
   da_ctl0             <= (ial[7:0]==8'h00);  // 0x00 WE to control 32-bit register (1 loc)
   da_dmamode0         <= (ial[7:0]==8'h01);  // 0x01 select writing to dma_cntr/dma_raw (1 loc)
   da_sensormode0      <= (ial[7:0]==8'h02);  // 0x02 select writing to sensorpix (1 loc)
   ...
   da_compressor0      <= (ial[7:1]==7'h06);  // 0x0c..0x0d - will be farther decoded in the compressor module
   ...

Since memory controller and compressor are to be replaced these addresses have to be adapted.

353 system interface address table

333 system interface address table

Addresses 0x01,2,3,4,5,6,8 and 0x30 can be kept in the 353 system interface. The interrupt mask address 0x06 in the 333 sys interface is no longer used (353 uses interrupt vectors). The Theora compressor and the new memory controller addresses have to be mapped again in the new design (addresses 0x0c..0x0d and 0x20 to 0x2f in the 353 sys interface).

Interrupts

Adapt the Theora compressor interrupts to the 353 interrupt vector .

The 353 interrupt vector can handle up to 16 different irq. However, only irq 0 to 7 are used :

x353.v

assign irq_in= {8'b0,                    // extra
               compressor_done_compress, // 7 - will go high after all data is sent out (reset by compressor)
               compressor_done_input,    // 6 - will go high after EOT and persist until DCT is enabled (reset by compressor)
               dcc_rdy,                  // 5 - obsolete in 333 - channel3 has 128 more dc coefficients (or some if the compression is finished)
               compressor_eot,           // 4 - compressor read in the last MCU (predictable time to end of transfer)
               sr_sensortrig[2],         // 3 - (sync to pclk) - level, reset by writing to sensor triggering command register
               xfer_over_irq,            // 2 - (sync to pclk) - frame acquisition over
               trig_irq,                 // 1 - (sync to pclk) - external trigger
               vacts};                   // 0 - (sync to pclk) - frame sync

353 MJPEG compressor triggers irqs 4, 6 and 7. 333 Theora compressor is the source of two irqs :

compressor_all.v

done,           // single-cycle pulse when the compressed frame is sent out (IRQ source).
reset_compress, // reset compressor done interrupt (writing any compressor command)

Adaptation should consist of assigning Theora compressor irq sources to vectors 6 and 7 for example if the MJPEG compressor is to be replaced.

DMA FIFOs

353 design uses 2 DMA FIFOs between the compressor and the system interface instead of one for the 333 Theora compressor. The two DMA FIFOs have also slight differences between the two design. Maybe a single 333 FIFO should be kept for the final design (?)

FPGA -> CPU data out MUX

The purpose of this MUX is to route data out from the different FPGA blocks to the system interface and then to the data bus to the CPU. The selection is made with the internal address bus ia.

                                  _
                               --| \
                               --|  |
                               --|  |
                               --|  |--- iod[31:0] -> to system interface
                               --|  |
                               --|  |
                                 |_/
from system interface -> ia[7:0]__|

333 MUX

353 MUX

Internal registers MUX and status register

333 MUX

353 MUX

333 status register

353 status register

Control register

The dcr[31:0] bus is used to control the different blocks according to the control register values. The control register can be directly written by the CPU at the address 0x00.

333 control register

353 control register

Others

• Looks like Theora compressor requires 90° phase clock that was abandoned in the 353 design.

Using different phases reduces AC component of the current through the power/ground lines of the FPGA by spreading register transitions. Theora has larger core so it may help spreading phases.--Andrey.filippov 13:45, 25 February 2008 (CST)

• ...?

Software updates

• Adapt FPGA definitions (x353.h) and most likely some other FPGA drivers.
• ...?

These lists of update are obviously incomplete. They need to be more detailed in order to make an exhaustive list of the changes that have to be done.

353 Theora new design

Compressor

Writing tables in compressor (and mcontr8ch) is the same than the 333 design :

• ia = 0x2d and idi = table address (X313_WA_COMP_TA=0x2d)

then

• ia = 0x2c and idi = table data (X313_WA_COMP_TD=0x2c)

Example : Writing zerobin and quantization tables in 353 Theora design

Sensorpix

Most of the 353 design was used for the new design. Writing procedure for gamma tables in sensorpix block is the same than in 353 (ie with ta bus and twr_gamma signal).

• ia = 0x0e and idi = table address

then

• ia = 0x0f and idi = table data

Table address is not autoincremented within the sensorpix block but is fed externally with the ta bus.

Memory controller

System interface

Interrupts

DMA FIFOs

A single DMA FIFO from the 333 design will be instanciated.

FPGA -> CPU data out MUX

Internal registers MUX and status register

Status register

Control register

Others

See also

• 353 Theora CVS
• Theora
• FPGA Development in Elphel cameras
• FPGA Theora Encoder for Videoconferencing
• 10353