Difference between revisions of "Si5338 driver"

Revision as of 15:21, 15 December 2013

The drivers/misc/si5338.c driver allows real-time control of the Silicon Labs si5338 Clock Generator using Linux sysfs interface. It also allows setting up parameters using the Device Tree.

It is also possible to use the register map file generated by Silicon Labs software, converted by a Python script to a Device Tree fragment (or fed to the driver with sysfs interface)

Reference Documentation

This driver is developed using excellent documentation provided by the chip manufacturer: [1] - detailed description of the device registers [2] - overall chip documentation including configuration procedure

sysfs interface

top level files

outputs (read only)

Provides information about each of the 4 outputs, like in the example below:

root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat outputs
0: 1V5_HSTL_A+, output frequency: 15000000 Hz, output route: MS0:1, ms_power_up, disabled state: dis_hi-z, output_power_up, output_en, Spread spectrum is ON, down amplitude= 500 ( *0.01%), spread rate= 31500 Hz
1: 2V5_LVPECL, output frequency: 0 Hz, output route: No clock, disabled state: dis_hi-z, output_power_down, output_en, Spread spectrum is OFF, down amplitude= 50 ( *0.01%), spread rate= 31500 Hz
2: 2V5_LVPECL, output frequency: 0 Hz, output route: No clock, disabled state: dis_hi-z, output_power_down, output_en, Spread spectrum is OFF, down amplitude= 50 ( *0.01%), spread rate= 31500 Hz
3: 1V8_LVDS, output frequency: 150000000 Hz, output route: MS3:1, ms_power_up, disabled state: dis_hi-z, output_power_up, output_en, Spread spectrum is ON, down amplitude= 50 ( *0.01%), spread rate= 31500 Hz

This includes:

• output voltage (1V5 - 1.5V)
• standard (HSTL)
• output inversion for of the 2 paired outputs in single-ended mode ("A+B-" A positive, B - inverted; "A+" - output B is disabled)
• output frequency
• output route - each output can be fed from multiple sources, for example "IN3:2:8" means signal from input 3 divided by 2 in the input stage and by 8 in the output stage. "MS0:1" means that output is connected to the MultiSynth output 0 with no divider
• disable state - low, high, hi-z or always on - state of the output pin when it is disabled
• output stage (and divider) power up/down state
• output enable/disable state (all outputs can be independently disabled by the global output disable)
• spread spectrum: on/off state, amplitude (in 0.01% of the output frequency steps) and the sweep rate. Only down spread is supported, so the center frequency is half-amplitude less than with spread spectrum disabled

status (read only)

Read and interpret status register.

root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat status
0x8 input clock: OK, feedback clock: LOST, PLL lock: OK, calibration: DONE

pre_init (write only)

root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# echo "0" > pre_init

Disables all outputs, loss of lock signal before setting parameters and initializing PLL

pre_init_clear (write only)

root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# echo "0" > pre_init_clear

Same as pre_init, but additionally clears all output routes and input multiplexers before setting up the needed ones

post_init (write only)

root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# echo "0" > post_init

Initializes and calibrates PLL - should be called after the PLL parameters (or the whole frequency plan) are set up.