Difference between revisions of "RTC"
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=== FPGA Timer === | === FPGA Timer === | ||
| + | Now FPGA code has a replacement RTC with digitally adjustable rate (so it is possible to calculate and apply correction). The timer data consists of 32-bit seconds counter and 20 bit counter from 0 to 999999 (0xf423f) of microseconds, provisions are made to freeze 52=32+20 bits during reading so seconds are not incremented between to reads. | ||
| + | |||
| + | Timer is be programmed by writing data to the FPGA registers | ||
| + | Writing to X313_WA_RTC_CORR (0x46) sets the 16-bit (signed) correction value (positive - make clock faster, negative - slower). Correction work in the following way. Each 0.5 microsecond (10*period of 20MHz master crystal oscillator) 24-bit accumulator is incremented by 0x800000+correction_value (0x7f8000 to 0x807fff) and the carry out increments microsecond counter - that usually happens each other time. | ||
| + | |||
| + | Writing to X313_WA_RTC_USEC (0x44) presets microsecond counter. Actually it is applied to the counter only together with the write value to the next register - X313_WA_RTC_SEC (0x45) - seconds. | ||
| + | |||
| + | To read | ||
Revision as of 16:14, 21 September 2005
Contents
Real Time Clock
Absolute date/time in Elphel cameras
Elphel model 333 (as well as older ones) camera does not have a hardware clock with battery backup so each time it wakes up it is January, 1 1970. We made a simple hack to automatically setup date and time - camera web interface uses javascript code that sends host computer time (UTC) to the camera as one parameters for image acquisitions (originally the purpose was just to make all URLs unique to prevent caching of images by the browser).
Timekeeping in Elphel cameras
After the date/time are set cameras use internal CPU timer (baased on the master crystal oscillator) to maintain current time. There are several restrictions of these method:
1 - the precision of the clock is limited to that of the crystal oscillator. Actually the clock IC allows fine-tune oscillator varying capacitance load but it is not really easy to calculate required change to apply;
2 - FPGA, that performs most of the data processing in the camera does not have direct access to the CPU timer. Precise timer in the FPGA might simplify image synchronization and timestamping with no uncertainty of the software responce.
FPGA Timer
Now FPGA code has a replacement RTC with digitally adjustable rate (so it is possible to calculate and apply correction). The timer data consists of 32-bit seconds counter and 20 bit counter from 0 to 999999 (0xf423f) of microseconds, provisions are made to freeze 52=32+20 bits during reading so seconds are not incremented between to reads.
Timer is be programmed by writing data to the FPGA registers Writing to X313_WA_RTC_CORR (0x46) sets the 16-bit (signed) correction value (positive - make clock faster, negative - slower). Correction work in the following way. Each 0.5 microsecond (10*period of 20MHz master crystal oscillator) 24-bit accumulator is incremented by 0x800000+correction_value (0x7f8000 to 0x807fff) and the carry out increments microsecond counter - that usually happens each other time.
Writing to X313_WA_RTC_USEC (0x44) presets microsecond counter. Actually it is applied to the counter only together with the write value to the next register - X313_WA_RTC_SEC (0x45) - seconds.
To read
