Difference between revisions of "Trigger 393"
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Revision as of 17:41, 20 December 2016
Contents
Description
10389 board is required.
The triggering is used for one or several cameras synchronization or setting the frame rate (or fps). The conditions of the trigger can be generated either internally or externally. For external triggering a 4-conductor 2.5mm audio plug with cable (example: digikey) is required.
To program trigger go to: http://192.168.0.9/parsedit.php => External Trigger Controls
NOTE: Be careful with changing parameters when TRIG=4. Camera drivers are driven by the frame sync interrupts from the sensor, so if the sensor is not triggered - everything can get stuck. The Program Ahead value sets the number of frame sync interrupts the camera will wait wait for until a parameter is reprogrammed.
Parameters
| parameter | description |
| TRIG | Trigger mode enable. 0 - free running, 4 - triggered by external signal or internal FPGA timing generator. |
| TRIG_PERIOD | FPGA trigger sequencer output sync period (32 bits, in pixel clocks (100MHz or 10ns)). 0- stop. 1 - single, >=256 repetitive with specified period (values 2..255 are reserved for programming timestamp communication) |
| TRIG_DELAY | FPGA trigger sequencer trigger delay, 32 bits in pixel clocks (100MHz or 10ns) |
| EXTERN_TIMESTAMP | When 1 camera will use external timestamp (received over inter-camera synchronization cable) if it is available (no action when external syncronization is not connected), when 0 - local timestamp will be used |
| TRIG_BITLENGTH | Bit length minus 1 (in pixel clock cycles) when transmitting/receiving timestamps, without timestamps the output pulse width is 8*(TRIG_BITLENGTH+1). Legal values 2..255 |
| XMIT_TIMESTAMP | Specify output signal sent through internal/external connector (defined by TRIG_OUT). 0 - transmit just sync pulse (8*(TRIG_BITLENGTH+1) pixel clock periods long), 1 - pulse+timestamp 64*(TRIG_BITLENGTH+1) pixel clock periods long |
| TRIG_CONDITION | level) for each GPIO[11:0] pin 0x0 - from FPGA, 0x80000 - ext, 0x8000 - int, 0x88000 - any, 0x95555 - add ext, 0x59999 - add int |
| TRIG_OUT | level_when_active). Bit 24 - test mode, when GPIO[11:10] are controlled by other internal signals 0x56555 - ext connector, 0x65555 - internal connector 0x66555 - both, 0x55555 - none |
Examples
Manual triggering from PC
Enable
http://192.168.0.9:2323/trig/pointers
- TRIG=4 should be set in advance
- The command automatically sets a single-shot trigger mode with TRIG_PERIOD=0x1, but it writes the register directly into the FPGA,
not updating the TRIG_PERIOD in the PHP interface:
http://192.168.0.9/parsedit.php?TRIG&TRIG_CONDITION&TRIG_DELAY&TRIG_OUT&TRIG_PERIOD&TRIG_BITLENGTH&EXTERN_TIMESTAMP&XMIT_TIMESTAMP&IRQ_SMART&refresh
Trigger/Refresh
http://192.168.0.9:8081/trig/pointers
Check status
http://192.168.0.9/parsedit.php?immediate&TRIG&TRIG_PERIOD&IRQ_SMART&SENS_AVAIL&FRAME
Disable
- Update the TRIG_PERIOD in the PHP interface - or simply check the box and hit Apply:
http://192.168.0.9/parsedit.php?TRIG&TRIG_CONDITION&TRIG_DELAY&TRIG_OUT&TRIG_PERIOD&TRIG_BITLENGTH&EXTERN_TIMESTAMP&XMIT_TIMESTAMP&IRQ_SMART&refresh
- Refresh until the changes are applied (with Program Ahead = 3 it's 3 times):
http://192.168.0.9:8081/trig/pointers
Internal periodic trigger (from fpga generator)
- TRIG_CONDITION=0x0
- set the TRIG_PERIOD (values 256+ are clock intervals - 10ns)
- TRIG=0x4
Internal periodic trigger (from fpga generator) + output the trigger signal
- TRIG_CONDITION=0x0
- set the TRIG_PERIOD
- TRIG=0x4
- TRIG_OUT=0x66555
External trigger
Receive
GPIO[10] needs to be configured to receive the trigger signal:
- (Same parameters for master and slave)
TRIG_OUT=0x565555 set the TRIG_PERIOD=100000000 (dec,=1fps) TRIG=0x4
Generate
- TRIG_CONDITION=0x0
- set the TRIG_PERIOD
- TRIG=0x4
- TRIG_OUT=0x66555
Links
- 10389 extension board
