Difference between revisions of "USB FPGA CODE"
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| + | == FPGA code to accomodate USB host module == | ||
| + | The code of the JPEG branch of the model 333 camera is modified (in rev 333100e) to accomodate new USB host module currently under development. These modifications also provide vector interrupts (from up to 16 sources) and simplifies the use of 6 FPGA pins connected to the inter-baord connector J2 (and so available at the extension boards). | ||
| + | |||
| + | === Vector Interrupts === | ||
| + | Axis ETRAX100LX processor [http://developer.axis.com/doc/old/hardware/etrax100lx/des_ref.html] supports two modes for external interrupts - with internally generated vector number and with externally generated. In that case CPU generates INTA pulse and the peripheral places an 8-bit vector code on the data bus. New (>=333100e) FPGA code supports both modes, for each of 16 intrerrupts individual vector code can be programmed. Four locations in the FPGA address space (CSP0,CSP4) are writable to control interrupts_vector333 module: | ||
| + | |||
| + | #define X313_WA_IRQ_RST 0x1c // reset selected interrupt bits | ||
| + | #define X313_WA_IRQ_DIS 0x1d // disable selected interrupt bits (mask) | ||
| + | #define X313_WA_IRQ_ENA 0x1e // enable selected interrupt bits | ||
| + | #define X313_WA_IRQ_WVECT 0x1f // write vector number (in bits [0:7], [11:8] - interrupt number (0..15) | ||
| + | |||
| + | The first one resets the selected bits (having ones in a word written to this location) of the source interrupt request register that is positive edge triggered from asynchronous signal in FPGA and reset by either of two reasons: | ||
| + | * writing to the X313_WA_IRQ_RST (0x1c) register with ones in the bits to be reset and | ||
| + | * servicing ''this''interrupt with externally generated vector number. When the INTA is generated the interrupt request bit that caused the interrupt (or at least the one which had it's number placed on data bus in responce to INTA) is reset so software does not need to do it again | ||
Revision as of 13:03, 14 December 2005
See discussion also
FPGA code to accomodate USB host module
The code of the JPEG branch of the model 333 camera is modified (in rev 333100e) to accomodate new USB host module currently under development. These modifications also provide vector interrupts (from up to 16 sources) and simplifies the use of 6 FPGA pins connected to the inter-baord connector J2 (and so available at the extension boards).
Vector Interrupts
Axis ETRAX100LX processor [1] supports two modes for external interrupts - with internally generated vector number and with externally generated. In that case CPU generates INTA pulse and the peripheral places an 8-bit vector code on the data bus. New (>=333100e) FPGA code supports both modes, for each of 16 intrerrupts individual vector code can be programmed. Four locations in the FPGA address space (CSP0,CSP4) are writable to control interrupts_vector333 module:
#define X313_WA_IRQ_RST 0x1c // reset selected interrupt bits #define X313_WA_IRQ_DIS 0x1d // disable selected interrupt bits (mask) #define X313_WA_IRQ_ENA 0x1e // enable selected interrupt bits #define X313_WA_IRQ_WVECT 0x1f // write vector number (in bits [0:7], [11:8] - interrupt number (0..15)
The first one resets the selected bits (having ones in a word written to this location) of the source interrupt request register that is positive edge triggered from asynchronous signal in FPGA and reset by either of two reasons:
- writing to the X313_WA_IRQ_RST (0x1c) register with ones in the bits to be reset and
- servicing thisinterrupt with externally generated vector number. When the INTA is generated the interrupt request bit that caused the interrupt (or at least the one which had it's number placed on data bus in responce to INTA) is reset so software does not need to do it again
