Si5338 driver
The drivers/misc/si5338.c driver allows real-time control of the Silicon Labs si5338 Clock Generator using Linux sysfs interface. It also allows setting up parameters using the Device Tree.
It is also possible to use the register map file generated by Silicon Labs software, converted by a Python script to a Device Tree fragment (or fed to the driver using sysfs interface).
Contents
- 1 Reference Documentation
- 2 sysfs interface
- 2.1 top level files
- 2.2 input/ folder
- 2.2.1 input/in_frequency12
- 2.2.2 input/in_frequency12xo
- 2.2.3 input/in_frequency3
- 2.2.4 input/in_frequency4
- 2.2.5 input/in_frequency56
- 2.2.6 input/in_mux
- 2.2.7 input/ref_mux
- 2.2.8 input/in_mux_txt (read only)
- 2.2.9 input/ref_mux_txt (read only)
- 2.2.10 input/in_p1_div
- 2.2.11 input/in_p2_div
- 2.2.12 input/in_pfd_ref
- 2.2.13 input/in_pfd_fb
- 2.2.14 input/in_pfd_ref_txt (read only)
- 2.2.15 input/in_pfd_fb_txt (read only)
- 2.2.16 input/fb_external
- 2.2.17 input/xtal_freq_txt (read only)
- 2.2.18 input/pll_ref_frequency (read only)
- 2.2.19 input/pll_fb_frequency (read only)
- 2.3 pll/ folder
- 2.4 multiSynth/ folder
- 2.4.1 multiSynth/ms0_p123
- 2.4.2 multiSynth/ms1_p123
- 2.4.3 multiSynth/ms2_p123
- 2.4.4 multiSynth/ms3_p123
- 2.4.5 multiSynth/msn_p123
- 2.4.6 multiSynth/ms0_abc
- 2.4.7 multiSynth/ms1_abc
- 2.4.8 multiSynth/ms2_abc
- 2.4.9 multiSynth/ms3_abc
- 2.4.10 multiSynth/msn_abc
- 2.4.11 multiSynth/ms0_freq_int
- 2.4.12 multiSynth/ms0_freq_fract
- 2.4.13 multiSynth/ms1_freq_int
- 2.4.14 multiSynth/ms1_freq_fract
- 2.4.15 multiSynth/ms2_freq_int
- 2.4.16 multiSynth/ms2_freq_fract
- 2.4.17 multiSynth/ms3_freq_int
- 2.4.18 multiSynth/ms3_freq_fract
- 2.4.19 multiSynth/ms_power_up
- 2.4.20 multiSynth/ms_power_down
- 2.4.21 multiSynth/ms_reset
- 2.5 spread_spectrum/ folder
- 2.6 output_clocks/ folder
- 2.6.1 output_clocks/out0_div
- 2.6.2 output_clocks/out1_div
- 2.6.3 output_clocks/out2_div
- 2.6.4 output_clocks/out3_div
- 2.6.5 output_clocks/out0_div_by_freq (write only)
- 2.6.6 output_clocks/out1_div_by_freq (write only)
- 2.6.7 output_clocks/out2_div_by_freq (write only)
- 2.6.8 output_clocks/out3_div_by_freq (write only)
- 2.6.9 output_clocks/out0_source
- 2.6.10 output_clocks/out1_source
- 2.6.11 output_clocks/out2_source
- 2.6.12 output_clocks/out3_source
- 2.6.13 output_clocks/out0_source_txt (read only)
- 2.6.14 output_clocks/out1_source_txt (read only)
- 2.6.15 output_clocks/out2_source_txt (read only)
- 2.6.16 output_clocks/out3_source_txt (read only)
- 2.6.17 output_clocks/out0_source_freq (read only)
- 2.6.18 output_clocks/out1_source_freq (read only)
- 2.6.19 output_clocks/out2_source_freq (read only)
- 2.6.20 output_clocks/out3_source_freq (read only)
- 2.6.21 output_clocks/out0_route
- 2.6.22 output_clocks/out1_route
- 2.6.23 output_clocks/out2_route
- 2.6.24 output_clocks/out3_route
- 2.6.25 output_clocks/out0_freq_int
- 2.6.26 output_clocks/out0_freq_fract
- 2.6.27 output_clocks/out1_freq_int
- 2.6.28 output_clocks/out1_freq_fract
- 2.6.29 output_clocks/out2_freq_int
- 2.6.30 output_clocks/out2_freq_fract
- 2.6.31 output_clocks/out3_freq_int
- 2.6.32 output_clocks/out3_freq_fract
- 2.7 output_drivers/ folder
- 2.7.1 output_drivers/1V5_HSTL_A+
- 2.7.2 output_drivers/1V5_HSTL_A+B+
- 2.7.3 output_drivers/1V5_HSTL_A+B-
- 2.7.4 output_drivers/1V5_HSTL_A-
- 2.7.5 output_drivers/1V5_HSTL_A-B+
- 2.7.6 output_drivers/1V5_HSTL_A-B-
- 2.7.7 output_drivers/1V5_HSTL_B+
- 2.7.8 output_drivers/1V5_HSTL_B-
- 2.7.9 output_drivers/1V8_CMOS_A+
- 2.7.10 output_drivers/1V8_CMOS_A+B+
- 2.7.11 output_drivers/1V8_CMOS_A+B-
- 2.7.12 output_drivers/1V8_CMOS_A-
- 2.7.13 output_drivers/1V8_CMOS_A-B+
- 2.7.14 output_drivers/1V8_CMOS_A-B-
- 2.7.15 output_drivers/1V8_CMOS_B+
- 2.7.16 output_drivers/1V8_CMOS_B-
- 2.7.17 output_drivers/1V8_LVDS
- 2.7.18 output_drivers/1V8_SSTL_A+
- 2.7.19 output_drivers/1V8_SSTL_A+B+
- 2.7.20 output_drivers/1V8_SSTL_A+B-
- 2.7.21 output_drivers/1V8_SSTL_A-
- 2.7.22 output_drivers/1V8_SSTL_A-B+
- 2.7.23 output_drivers/1V8_SSTL_A-B-
- 2.7.24 output_drivers/1V8_SSTL_B+
- 2.7.25 output_drivers/1V8_SSTL_B-
- 2.7.26 output_drivers/2V5_CMOS_A+
- 2.7.27 output_drivers/2V5_CMOS_A+B+
- 2.7.28 output_drivers/2V5_CMOS_A+B-
- 2.7.29 output_drivers/2V5_CMOS_A-
- 2.7.30 output_drivers/2V5_CMOS_A-B+
- 2.7.31 output_drivers/2V5_CMOS_A-B-
- 2.7.32 output_drivers/2V5_CMOS_B+
- 2.7.33 output_drivers/2V5_CMOS_B-
- 2.7.34 output_drivers/2V5_LVDS
- 2.7.35 output_drivers/2V5_LVPECL
- 2.7.36 output_drivers/2V5_SSTL_A+
- 2.7.37 output_drivers/2V5_SSTL_A+B+
- 2.7.38 output_drivers/2V5_SSTL_A+B-
- 2.7.39 output_drivers/2V5_SSTL_A-
- 2.7.40 output_drivers/2V5_SSTL_A-B+
- 2.7.41 output_drivers/2V5_SSTL_A-B-
- 2.7.42 output_drivers/2V5_SSTL_B+
- 2.7.43 output_drivers/2V5_SSTL_B-
- 2.7.44 output_drivers/3V3_CMOS_A+
- 2.7.45 output_drivers/3V3_CMOS_A+B+
- 2.7.46 output_drivers/3V3_CMOS_A+B-
- 2.7.47 output_drivers/3V3_CMOS_A-
- 2.7.48 output_drivers/3V3_CMOS_A-B+
- 2.7.49 output_drivers/3V3_CMOS_A-B-
- 2.7.50 output_drivers/3V3_CMOS_B+
- 2.7.51 output_drivers/3V3_CMOS_B-
- 2.7.52 output_drivers/3V3_LVDS
- 2.7.53 output_drivers/3V3_LVPECL
- 2.7.54 output_drivers/3V3_SSTL_A+
- 2.7.55 output_drivers/3V3_SSTL_A+B+
- 2.7.56 output_drivers/3V3_SSTL_A+B-
- 2.7.57 output_drivers/3V3_SSTL_A-
- 2.7.58 output_drivers/3V3_SSTL_A-B+
- 2.7.59 output_drivers/3V3_SSTL_A-B-
- 2.7.60 output_drivers/3V3_SSTL_B+
- 2.7.61 output_drivers/3V3_SSTL_B-
- 2.7.62 output_drivers/dis_always_on
- 2.7.63 output_drivers/dis_hi-z
- 2.7.64 output_drivers/dis_high
- 2.7.65 output_drivers/dis_low
- 2.7.66 output_drivers/output_dis
- 2.7.67 output_drivers/output_en
- 2.7.68 output_drivers/output_power_up
- 2.7.69 output_drivers/output_power_down
- 2.7.70 output_drivers/output0 (read only)
- 2.7.71 output_drivers/output1 (read only)
- 2.7.72 output_drivers/output2 (read only)
- 2.7.73 output_drivers/output3 (read only)
- 2.7.74 output_drivers/outputs (read only)
Reference Documentation
This driver is developed using excellent documentation provided by the chip manufacturer: [1] - detailed description of the device registers [2] - overall chip documentation including configuration procedure
sysfs interface
top level files
outputs (read only)
Provides information about each of the 4 outputs, like in the example below:
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat outputs 0: 1V5_HSTL_A+, output frequency: 15000000 Hz, output route: MS0:1, ms_power_up, disabled state: dis_hi-z, output_power_up, output_en, Spread spectrum is ON, down amplitude= 500 ( *0.01%), spread rate= 31500 Hz 1: 2V5_LVPECL, output frequency: 0 Hz, output route: No clock, disabled state: dis_hi-z, output_power_down, output_en, Spread spectrum is OFF, down amplitude= 50 ( *0.01%), spread rate= 31500 Hz 2: 2V5_LVPECL, output frequency: 0 Hz, output route: No clock, disabled state: dis_hi-z, output_power_down, output_en, Spread spectrum is OFF, down amplitude= 50 ( *0.01%), spread rate= 31500 Hz 3: 1V8_LVDS, output frequency: 150000000 Hz, output route: MS3:1, ms_power_up, disabled state: dis_hi-z, output_power_up, output_en, Spread spectrum is ON, down amplitude= 50 ( *0.01%), spread rate= 31500 Hz
This includes:
- output voltage (1V5 - 1.5V)
- standard (HSTL)
- output inversion for of the 2 paired outputs in single-ended mode ("A+B-" A positive, B - inverted; "A+" - output B is disabled)
- output frequency
- output route - each output can be fed from multiple sources, for example "IN3:2:8" means signal from input 3 divided by 2 in the input stage and by 8 in the output stage. "MS0:1" means that output is connected to the MultiSynth output 0 with no divider
- disable state - low, high, hi-z or always on - state of the output pin when it is disabled
- output stage (and divider) power up/down state
- output enable/disable state (all outputs can be independently disabled by the global output disable)
- spread spectrum: on/off state, amplitude (in 0.01% of the output frequency steps) and the sweep rate. Only down spread is supported, so the center frequency is half-amplitude less than with spread spectrum disabled
status (read only)
Read and interpret status register.
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat status 0x8 input clock: OK, feedback clock: LOST, PLL lock: OK, calibration: DONE
pre_init (write only)
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# echo "0" > pre_init
Disables all outputs, loss of lock signal before setting parameters and initializing PLL
pre_init_clear (write only)
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# echo "0" > pre_init_clear
Same as pre_init, but additionally clears all output routes and input multiplexers before setting up the needed ones
post_init (write only)
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# echo "0" > post_init
Initializes and calibrates PLL - should be called after the PLL parameters (or the whole frequency plan) are set up.
input/ folder
input/in_frequency12
input/in_frequency12xo
input/in_frequency3
input/in_frequency4
input/in_frequency56
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# echo "25000000" > input/in_frequency3 root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat input/in_frequency3 25000000
Set the input frequency applied to one of the differential input pairs (12, 56) or single-ended (3,4). "in_frequency12xo: is used to specify the frequency of the crystal connected between inputs 1 and 2. While the driver tries to make as little assumptions as possible and reads data from the si5338 registers (or actually from their cached shadows), the input frequency has to be stored off-chip and may be needed to be set up if you plan to use high-level functions to change frequency parameters even if the registers where initialized from the pre-calculated register map. Each write to these nodes also programs the input multiplexers and routes the specified pin (pin pair) to the PLL reference input, so if there are several active inputs, the last specified input will be routed.
input/in_mux
input/ref_mux
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# echo "1" input/in_mux root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat input/in_mux 1
Directly control in input and feedback multiplexers
input/in_mux_txt (read only)
input/ref_mux_txt (read only)
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat input/in_mux_txt IN3(single ended)
Interpret the state of the input and feedback multiplexers
input/in_p1_div
input/in_p2_div
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# echo "32" > input/in_p1_div root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat input/in_p1_div 32
Read/write input dividers, valid values are 1,2,4,8,16 and 32
input/in_pfd_ref
input/in_pfd_fb
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# echo "0" > input/in_pfd_ref root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat input/in_pfd_ref 0
Read/write PLL reference and feedback multiplexers selections. The feedback input can be switched to the output of the feedback multiplexer from the MSn MultiSynth output with the "input/fb_external".
input/in_pfd_ref_txt (read only)
input/in_pfd_fb_txt (read only)
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat input/in_pfd_ref_txt p1div_in(refclk)
Read and interpret the state of the reference and feedback multiplexers.
input/fb_external
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# echo "0" > input/fb_external root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat input/fb_external 0
Switch between internal PLL feedback from the MSn divider (0) and the external input (1). The external feedback can be used in the zero-delay buffer mode, most applications use internal feedback mode.
input/xtal_freq_txt (read only)
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat input/xtal_freq_txt 26MHz..30Mhz
Read crystal oscillator mode settings. Appropriate settings are selected by writing to "input/in_frequency12xo" or loading the register map prepared by the Silicon Labs software.
input/pll_ref_frequency (read only)
input/pll_fb_frequency (read only)
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat input/pll_ref_frequency 25000000 root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat input/pll_fb_frequency 0
Read reference and feedback frequency values. Determined by the input frequency settings, dividers and multiplexers.
pll/ folder
VCO frequency (use in PLL) can be set up either directly, or to match specified output frequency (one of the 4 channels). The valid range is 2.2GHz to 2.84GHz (2200000000 to 2840000000). Frequencies are specified in Hz with possible fractional part (numerator then denominator), so "2550000000 0 1" is the same as just "2550000000". In both cases "_int" and "_fract" applies to the feedback divider, the lowest jitter is achieved with integer dividers. Reading any of these nodes return the PLL frequency in Hz. "pll/pll_freq_int" is the most common option to use.
pll/pll_freq_int
Specify VCO frequency in HZ, require integer divider. Read VCO frequency in Hz.
pll/pll_freq_fract
Specify VCO frequency in HZ, allow fractional divider. Read VCO frequency in Hz.
pll/pll_by_out_int
Match VCO frequency to the required output frequency in HZ, require integer divider in both feedback and output dividers. Read VCO frequency in Hz.
pll/pll_by_out_fract
Match VCO frequency to the required output frequency in HZ, allow fractional feedback (MSn) divider. Read VCO frequency in Hz.
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat pll/pll_by_out_int 2550000000 0 1
multiSynth/ folder
The si5338 chip uses 5 "multiSynth" fractional dividers - 4 of them (MS0..MS3) are used for the output frequencies generations, and the fifth one (MSn) is used as the PLL feeback divider. This subdirectory allows low-level control of these dividers - in most cases they can be set up indirectly by specifying the required frequencies.
multiSynth/ms0_p123
multiSynth/ms1_p123
multiSynth/ms2_p123
multiSynth/ms3_p123
multiSynth/msn_p123
Read/write a set of 3 registers as defined in the Reference Manual (P1, P2 and P3):
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# echo "21248 0 1" multiSynth/ms0_p123 root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat multiSynth/ms0_p123 21248 0 1
multiSynth/ms0_abc
multiSynth/ms1_abc
multiSynth/ms2_abc
multiSynth/ms3_abc
multiSynth/msn_abc
Read/write MultiSynth dividers using integer part, numerator and denominator (a,b and c) as referenced in the manual
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat multiSynth/ms0_abc 170 0 1
multiSynth/ms0_freq_int
multiSynth/ms0_freq_fract
multiSynth/ms1_freq_int
multiSynth/ms1_freq_fract
multiSynth/ms2_freq_int
multiSynth/ms2_freq_fract
multiSynth/ms3_freq_int
multiSynth/ms3_freq_fract
Setting integer/fractional MultiSynth dividers by the required output frequency (single integer or 3 numbers - integer, numerator and denominator). Reading back provides actual value of the frequency.
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat multiSynth/ms0_freq_int 15000000 0 1
multiSynth/ms_power_up
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# echo "0 3" > multiSynth/ms_power_up root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat multiSynth/ms_power_up 0 3
Power up selected channels, read returns the list of the powered up channels
multiSynth/ms_power_down
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# echo "1 2" > multiSynth/ms_power_down root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat multiSynth/ms_power_down 1 2
Power down selected channels, read returns the list of the powered down channels
multiSynth/ms_reset
Reset multiSynth dividers (not clear when exactly they should be reset - possibly after spread spectrum changes).
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# echo "0" > multiSynth/ms_reset
spread_spectrum/ folder
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# ls -all spread_spectrum/ drwxr-xr-x 2 root root 0 Dec 12 09:30 . drwxr-xr-x 10 root root 0 Dec 12 08:12 .. --w------- 1 root root 4096 Dec 12 09:30 ms_reset -rw-r--r-- 1 root root 4096 Dec 12 09:30 ss0_regs_hex -rw-r--r-- 1 root root 4096 Dec 12 09:30 ss0_values -rw-r--r-- 1 root root 4096 Dec 12 09:30 ss1_regs_hex -rw-r--r-- 1 root root 4096 Dec 12 09:30 ss1_values -rw-r--r-- 1 root root 4096 Dec 12 09:30 ss2_regs_hex -rw-r--r-- 1 root root 4096 Dec 12 09:30 ss2_values -rw-r--r-- 1 root root 4096 Dec 12 09:30 ss3_regs_hex -rw-r--r-- 1 root root 4096 Dec 12 09:30 ss3_values -rw-r--r-- 1 root root 4096 Dec 12 09:30 ss_change_freq_mode
output_clocks/ folder
output_clocks/out0_div
output_clocks/out1_div
output_clocks/out2_div
output_clocks/out3_div
Direct setting of the output divider, that can be 1,2,4,8,16 and 32. In most applications this divider is automatically set by specifying the output frequency.
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# echo "8" > output_clocks/out0_div root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat output_clocks/out0_div 8
output_clocks/out0_div_by_freq (write only)
output_clocks/out1_div_by_freq (write only)
output_clocks/out2_div_by_freq (write only)
output_clocks/out3_div_by_freq (write only)
Set just the divider to match the required frequency. Frequency is specified in Hz.
output_clocks/out0_source
output_clocks/out1_source
output_clocks/out2_source
output_clocks/out3_source
Set/read the output multiplexer selection (as a number).
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# echo "6" > output_clocks/out0_source root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat output_clocks/out0_source 6
output_clocks/out0_source_txt (read only)
output_clocks/out1_source_txt (read only)
output_clocks/out2_source_txt (read only)
output_clocks/out3_source_txt (read only)
Read and interpret the output multiplexer selection.
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat output_clocks/out0_source_txt MS0
output_clocks/out0_source_freq (read only)
output_clocks/out1_source_freq (read only)
output_clocks/out2_source_freq (read only)
output_clocks/out3_source_freq (read only)
Get the frequency on the input of the output divider.
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat output_clocks/out0_source_freq 15000000 0 1
output_clocks/out0_route
output_clocks/out1_route
output_clocks/out2_route
output_clocks/out3_route
Read/write the full route of the output clock, including the divider. Here are some examples:
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# echo "IN3:2:8" >output_clocks/out1_route
Route clock from input 3 through input divider 2 and output divider 8
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat output_clocks/out2_route No clock
Output 2 is not connected to any source
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat output_clocks/out0_route MS0:1
Output 0 is connected to MultiSynth divider channel 0, output divider 1:1
output_clocks/out0_freq_int
output_clocks/out0_freq_fract
output_clocks/out1_freq_int
output_clocks/out1_freq_fract
output_clocks/out2_freq_int
output_clocks/out2_freq_fract
output_clocks/out3_freq_int
output_clocks/out3_freq_fract
Most common way to specify output frequency and route. Output is routed to the same channel MultiSynth divider, MS divider and output divider are set to match the specified frequency. "_int" suffix rounds the MS divider to the nearest integer, "_fract" allows fractional dividers. Output frequency specified in Hz as a single number or a triad of integer, numerator and denominator. When read returns the actual frequency of the output
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# echo "150000 1 2" > output_clocks/out2_freq_fract sh: write error: Invalid argument
Specified frequency (150KHz) is too low even with the 1:32 output divider
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# echo "200000 1 2" > output_clocks/out2_freq_fract root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat output_clocks/out2_freq_fract 200000 6250 12207 root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# echo "200000 1 2" > output_clocks/out2_freq_int root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat output_clocks/out2_freq_int 200219 169 199 root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat output_clocks/out2_route MS2:32 Output frequency for the channel 2 is set to the 200000.5 Hz first with fractional MS2 divider (resulting in 200000.512Hz), then with integer divider - 200219.8 Hz
output_drivers/ folder
Configuring output drivers - voltage, I/O standard, inversion, power up/down, output enable and state when the output is disabled
output_drivers/1V5_HSTL_A+
output_drivers/1V5_HSTL_A+B+
output_drivers/1V5_HSTL_A+B-
output_drivers/1V5_HSTL_A-
output_drivers/1V5_HSTL_A-B+
output_drivers/1V5_HSTL_A-B-
output_drivers/1V5_HSTL_B+
output_drivers/1V5_HSTL_B-
output_drivers/1V8_CMOS_A+
output_drivers/1V8_CMOS_A+B+
output_drivers/1V8_CMOS_A+B-
output_drivers/1V8_CMOS_A-
output_drivers/1V8_CMOS_A-B+
output_drivers/1V8_CMOS_A-B-
output_drivers/1V8_CMOS_B+
output_drivers/1V8_CMOS_B-
output_drivers/1V8_LVDS
output_drivers/1V8_SSTL_A+
output_drivers/1V8_SSTL_A+B+
output_drivers/1V8_SSTL_A+B-
output_drivers/1V8_SSTL_A-
output_drivers/1V8_SSTL_A-B+
output_drivers/1V8_SSTL_A-B-
output_drivers/1V8_SSTL_B+
output_drivers/1V8_SSTL_B-
output_drivers/2V5_CMOS_A+
output_drivers/2V5_CMOS_A+B+
output_drivers/2V5_CMOS_A+B-
output_drivers/2V5_CMOS_A-
output_drivers/2V5_CMOS_A-B+
output_drivers/2V5_CMOS_A-B-
output_drivers/2V5_CMOS_B+
output_drivers/2V5_CMOS_B-
output_drivers/2V5_LVDS
output_drivers/2V5_LVPECL
output_drivers/2V5_SSTL_A+
output_drivers/2V5_SSTL_A+B+
output_drivers/2V5_SSTL_A+B-
output_drivers/2V5_SSTL_A-
output_drivers/2V5_SSTL_A-B+
output_drivers/2V5_SSTL_A-B-
output_drivers/2V5_SSTL_B+
output_drivers/2V5_SSTL_B-
output_drivers/3V3_CMOS_A+
output_drivers/3V3_CMOS_A+B+
output_drivers/3V3_CMOS_A+B-
output_drivers/3V3_CMOS_A-
output_drivers/3V3_CMOS_A-B+
output_drivers/3V3_CMOS_A-B-
output_drivers/3V3_CMOS_B+
output_drivers/3V3_CMOS_B-
output_drivers/3V3_LVDS
output_drivers/3V3_LVPECL
output_drivers/3V3_SSTL_A+
output_drivers/3V3_SSTL_A+B+
output_drivers/3V3_SSTL_A+B-
output_drivers/3V3_SSTL_A-
output_drivers/3V3_SSTL_A-B+
output_drivers/3V3_SSTL_A-B-
output_drivers/3V3_SSTL_B+
output_drivers/3V3_SSTL_B-
Set voltage, standard and inversion of the paired outputs (A,B) where applicable by writing list of channels to one of the nodes. When read, node returns the list of outputs that have the specified parameters:
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# echo "1 2" > output_drivers/2V5_SSTL_A+B+ root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat output_drivers/2V5_SSTL_A+B+ 1 2
To find out the standard of the particular output (or all of them) it is possible to read output_drivers/output<n> or just "outputs". Not all of the combinations of the low-level register values correspond to one of the valid output driver configuration listed above, these combinations will be listed as "Invalid output configuration" and provide the values of the relevant register fields, described in the Reference Manual.
output_drivers/dis_always_on
output_drivers/dis_hi-z
output_drivers/dis_high
output_drivers/dis_low
Setting (and reading back) the behavior of the outputs in the disabled state. Note output state is synchronous and requires clock to run, so if output is already in disable state, switching form "dis_low" to "dis_high" will not take effect. Switching "dis_low" -> "dis_always_on" -> "dis_high" works, as "dis_always_on" temporarily provides output clock.
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat output_drivers/dis_hi-z 0 1 2 3 root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# echo "1 2" >output_drivers/dis_low root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat output_drivers/dis_hi-z 0 3
output_drivers/output_dis
output_drivers/output_en
Enables/disables specified channels, reads back the list of enabled/disabled ones
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat output_drivers/output_en 0 1 2 3
output_drivers/output_power_up
output_drivers/output_power_down
Turns on/off power to the output driver and divider, reads back the list of powered up/down output channels
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat output_drivers/output_power_up 0 2 3 root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# echo "2 3" > output_drivers/output_power_down root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat output_drivers/output_power_up 0
output_drivers/output0 (read only)
output_drivers/output1 (read only)
output_drivers/output2 (read only)
output_drivers/output3 (read only)
output_drivers/outputs (read only)
List settings related to individual output channel or all of them (the last node is duplicated on the top hierarchy level):
root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat output_drivers/output0 1V5_HSTL_A+, output frequency: 15000000 Hz, output route: MS0:1, ms_power_up, disabled state: dis_hi-z, output_power_up, output_en, Spread spectrum is ON, down amplitude= 500 ( *0.01%), spread rate= 31500 Hz root@elphel393:/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070# cat output_drivers/outputs 0: 1V5_HSTL_A+, output frequency: 15000000 Hz, output route: MS0:1, ms_power_up, disabled state: dis_hi-z, output_power_up, output_en, Spread spectrum is ON, down amplitude= 500 ( *0.01%), spread rate= 31500 Hz 1: 2V5_SSTL_A+B+, output frequency: 1562500 Hz, output route: IN3:2:8, disabled state: dis_low, output_power_down, output_en, Spread spectrum is OFF, down amplitude= 50 ( *0.01%), spread rate= 31500 Hz 2: 2V5_SSTL_A+B+, output frequency: 200219-169/199 Hz, output route: MS2:32, ms_power_up, disabled state: dis_low, output_power_down, output_en, Spread spectrum is OFF, down amplitude= 50 ( *0.01%), spread rate= 31500 Hz 3: 1V8_LVDS, output frequency: 150000000 Hz, output route: MS3:1, ms_power_up, disabled state: dis_hi-z, output_power_down, output_en, Spread spectrum is ON, down amplitude= 50 ( *0.01%), spread rate= 31500 Hz