Difference between revisions of "10359 FPGA Simulation"
From ElphelWiki
Okdzhimiev (talk | contribs) |
Okdzhimiev (talk | contribs) |
||
| Line 8: | Line 8: | ||
==Board tests== | ==Board tests== | ||
| − | 1. | + | 1. I2c check |
| + | a. It doesn't work when i assemled project with mcontr and 2 DCMs. | ||
| + | b. Started from the beginning. Works. | ||
| + | c. Checked i2c four read with 1 start. Works fine. | ||
| + | d. Adding DCMs. | ||
| − | 2. Check DDR read/write. | + | 2. Check BRAM read/write. |
| + | |||
| + | 3. Check DDR read/write. | ||
Revision as of 11:23, 15 February 2008
The main page for the board is 10359.
Verification
1. Channel 3 simulation:
- DDR initialization through i2c - done.
- write to DDR - done.
- read from DDR - done.
Board tests
1. I2c check
a. It doesn't work when i assemled project with mcontr and 2 DCMs. b. Started from the beginning. Works. c. Checked i2c four read with 1 start. Works fine. d. Adding DCMs.
2. Check BRAM read/write.
3. Check DDR read/write.
