Difference between revisions of "10359 FPGA Simulation"

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* write to DDR - done.
 
* write to DDR - done.
 
* read from DDR - done.
 
* read from DDR - done.
 +
 +
2. PHASE_SHIFT in DCM is not available currently, because the model had bad constructs
  
 
==Board tests==
 
==Board tests==

Revision as of 15:16, 19 February 2008

The main page for the board is 10359.

Verification

1. Channel 3 simulation:

  • DDR initialization through i2c - done.
  • write to DDR - done.
  • read from DDR - done.

2. PHASE_SHIFT in DCM is not available currently, because the model had bad constructs

Board tests

1. I2c check

a. It doesn't work when i assemled project with mcontr and 2 DCMs.
b. Started from the beginning. Works.
c. Checked i2c four read with 1 start. Works fine.
d. Adding DCMs.

2. Check BRAM read/write.

3. Check DDR read/write.