Difference between revisions of "FPGA Development in Elphel cameras"
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==FPGA design flow== | ==FPGA design flow== | ||
| + | There are two main activities during development of the FPGA code: synthesis and simulation. | ||
| + | * Synthesis (the whole process involves more steps in addition to just strictly "synthesis" itself) is needed to translate the source code into the "executable" and | ||
| + | * Simulation - software emulation of the FPGA functionality. Simulation runs about million times slower than the real thing, but it allows easy analysis of what is going inside the design, provides ability to test and troubleshoot project as a whole or individual modules. | ||
Revision as of 17:27, 28 January 2008
Introduction
Much of the performance and flexibility of the Elphel cameras are provided by the reconfigurable FPGA chips. FPGA is used on the main camera board (currently it is 10353) and on some of the extension ones (10347, 10359, 10357). On the main board the FPGA chip complements CPU to perform video processing and compression - it does this nearly 100 times faster than the CPU alone, but generally it is significantly more difficult to implement some functionality in the FPGA than it can be done in the software. And so the camera (like many other modern devices) combines the strong features of both: FPGA performs computationally intensive but algorithmically relatively simple operations (working with the images on the pixel level, providing image compression) and the CPU is responsible for the higher level functions, interface and overall control of the camera.
Elphel does not make secrets of the FPGA code, all the source code is available under GNU GPL v 3.0 license, the same one as used for the camera software. Elphel software distribution (available both on Sourceforge project page and inside each camera file system) includes both binary FPGA image ("bit file") and the source code needed to re-create the FPGA image and/or simulate the design. Also included are the log files generated by the FPGA "compiler" during creation of the provided bit file so you may look inside even if you do not have the necessary FPGA tools, you may also find these files useful to compare with the output that you get from those tools.
FPGA design flow
There are two main activities during development of the FPGA code: synthesis and simulation.
- Synthesis (the whole process involves more steps in addition to just strictly "synthesis" itself) is needed to translate the source code into the "executable" and
- Simulation - software emulation of the FPGA functionality. Simulation runs about million times slower than the real thing, but it allows easy analysis of what is going inside the design, provides ability to test and troubleshoot project as a whole or individual modules.
