Difference between revisions of "Load custom bitstream"
From ElphelWiki
| Line 1: | Line 1: | ||
==Description== | ==Description== | ||
The default bitstream is loaded from OS not from u-boot. | The default bitstream is loaded from OS not from u-boot. | ||
| + | |||
Reasons: | Reasons: | ||
* Different banks have different (software - controlled and regulated) voltages and they need to be set up before loading. | * Different banks have different (software - controlled and regulated) voltages and they need to be set up before loading. | ||
| Line 33: | Line 34: | ||
** the bitstream is loaded by '''autocampars''' or '''sata''' (if autocampars is skipped) | ** the bitstream is loaded by '''autocampars''' or '''sata''' (if autocampars is skipped) | ||
| + | ===autocampars=== | ||
| + | * project: [https://git.elphel.com/Elphel/elphel-apps-autocampars elphel-apps-autocampars] | ||
| + | * top script: '''autocampars.php''' | ||
| + | ** loads ''/usr/local/verilog/x359.bit'' to the external MUX board | ||
| + | ** depending on configuration (determined in init_elphel393.py) calls '''autocampars.py''' with arguments listed in the files in ''/usr/local/verilog''. The default one is ''/usr/local/verilog/hargs'': | ||
| + | -d TARGET_MODE=1 | ||
| + | -f /usr/local/verilog/system_defines.vh | ||
| + | -f /usr/local/verilog/x393_parameters.vh /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh | ||
| + | -l /usr/local/verilog/x393_cur_params_target.vh | ||
| + | -p PICKLE="/usr/local/verilog/x393_mcntrl.pickle | ||
| + | -c bitstream_set_path /usr/local/verilog/x393_parallel.bit | ||
| + | -c setupSensorsPower "PAR12" all 0 0.1 | ||
| + | -c measure_all "*DI" | ||
| + | -c setSensorClock 24.0 "2V5_LVDS" | ||
| + | -c set_rtc | ||
| + | |||
| + | The file with arguments can be found in the fpga projects, example: | ||
| + | https://git.elphel.com/Elphel/x393/tree/master/py393 | ||
| + | ===sata=== | ||
| + | * project [https://git.elphel.com/Elphel/x393_sata x393_sata] | ||
| + | * '''/usr/local/bin/x393sata.py''' loads it default bitstream if fpga was not programmed yet. | ||
| + | ... | ||
| + | DEFAULT_BITFILE="/usr/local/verilog/x393_sata.bit" | ||
| + | ... | ||
[[Category:393]] | [[Category:393]] | ||
Revision as of 14:27, 20 April 2017
Description
The default bitstream is loaded from OS not from u-boot.
Reasons:
- Different banks have different (software - controlled and regulated) voltages and they need to be set up before loading.
- voltages are set by the software through i2c
Bitstreams paths
- /usr/local/verilog/
| name | description |
|---|---|
| x393_parallel.bit | for 5MPix sensor with parallel interface + SATA |
| x393_hispi.bit | for 14MPix sensor with serial interface + SATA |
| x393_sata.bit | SATA only |
| x359.bit | for external MUX 3-to-1 board |
Init
- /etc/init.d/init_elphel393
...
$CONFDIR/init_elphel393.py "{\"usb_hub\":1, \"ip\":1,\"imgsrv\":1, \"autoexp_daemon\":1, \"autocampars\":1, \"sata\":1, \"gps\":1, \"eyesis\":0 }"
...
- in this line the extra init procedures are listed, to disable/skip certain procedure set 0, to enable - set 1
- everything is done in /etc/elphel393/init_elphel393.py which runs other scripts.
- the bitstream is loaded by autocampars or sata (if autocampars is skipped)
autocampars
- project: elphel-apps-autocampars
- top script: autocampars.php
- loads /usr/local/verilog/x359.bit to the external MUX board
- depending on configuration (determined in init_elphel393.py) calls autocampars.py with arguments listed in the files in /usr/local/verilog. The default one is /usr/local/verilog/hargs:
-d TARGET_MODE=1 -f /usr/local/verilog/system_defines.vh -f /usr/local/verilog/x393_parameters.vh /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh -l /usr/local/verilog/x393_cur_params_target.vh -p PICKLE="/usr/local/verilog/x393_mcntrl.pickle -c bitstream_set_path /usr/local/verilog/x393_parallel.bit -c setupSensorsPower "PAR12" all 0 0.1 -c measure_all "*DI" -c setSensorClock 24.0 "2V5_LVDS" -c set_rtc
The file with arguments can be found in the fpga projects, example:
https://git.elphel.com/Elphel/x393/tree/master/py393
sata
- project x393_sata
- /usr/local/bin/x393sata.py loads it default bitstream if fpga was not programmed yet.
... DEFAULT_BITFILE="/usr/local/verilog/x393_sata.bit" ...
