Difference between revisions of "Talk:Mcontr"
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==Programmable SDRAM sequencing== | ==Programmable SDRAM sequencing== | ||
* add/remove bank interleaving?--[[User:Oleg|Oleg]] 06:57, 11 August 2008 (CDT) | * add/remove bank interleaving?--[[User:Oleg|Oleg]] 06:57, 11 August 2008 (CDT) | ||
| + | no --[[User:Oleg|Oleg]] 05:49, 14 August 2008 (CDT) | ||
* program CL= "2,2.5,3" and BL= "2,4,8"?--[[User:Oleg|Oleg]] 06:57, 11 August 2008 (CDT) | * program CL= "2,2.5,3" and BL= "2,4,8"?--[[User:Oleg|Oleg]] 06:57, 11 August 2008 (CDT) | ||
| + | no --[[User:Oleg|Oleg]] 05:49, 14 August 2008 (CDT) | ||
| + | * programmable block size --[[User:Oleg|Oleg]] 05:49, 14 August 2008 (CDT) | ||
Latest revision as of 03:50, 14 August 2008
Bank interleaving
Interleaving like in Theora? Even/odd row switching in different banks.--Oleg 06:57, 11 August 2008 (CDT)
- bank interleaving for one-channel access
- 2 banks for one read/write sequence (b0-b2, b1-b3)
- b=bank, r=active row
(b0.r0 - b2.r1), (b1.r0 - b3.r1), (b2.r0 - b0.r1), (b3.r0 - b1.r1), (b0.r2 - b2.r3), (b1.r2 - b3.r3), (b2.r2 - b0.r3), (b3.r2 - b1.r3), ... (b0.r[even]- b2.r[odd]),(b1.r[even]- b3.r[odd]),(b2.r[even]- b0.r[odd]),(b3.r[even]- b1.r[odd])
--Oleg 19:23, 12 August 2008 (UTC)
Programmable SDRAM sequencing
- add/remove bank interleaving?--Oleg 06:57, 11 August 2008 (CDT)
no --Oleg 05:49, 14 August 2008 (CDT)
- program CL= "2,2.5,3" and BL= "2,4,8"?--Oleg 06:57, 11 August 2008 (CDT)
no --Oleg 05:49, 14 August 2008 (CDT)
- programmable block size --Oleg 05:49, 14 August 2008 (CDT)
