Difference between revisions of "10359 FPGA Simulation"
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==Understanding how 353's mcontr works== | ==Understanding how 353's mcontr works== | ||
| − | + | 02/28/08: | |
| − | + | 15:04 | |
| + | for mode=0 ( 8 - burst length) | ||
| + | TileX - number of (32x8) blocks | ||
| + | Seq_par(or Param) - the last write block length - (Seq_par)x8 | ||
| + | TileY - number of TileX | ||
| + | All this starts from StartAddress | ||
Revision as of 14:05, 28 February 2008
The main page for the board is 10359.
Verification
1. Channel 3 simulation:
- DDR initialization through i2c - done.
- write to DDR - done.
- read from DDR - done.
2. PHASE_SHIFT in DCM is not available currently, because the model had bad constructs, but SDCLK(SDNCLK) can be controlled by "phsel".
For correct writing/reading from DDR in model set phsel="01" (register=0x1008, value=0x00000004).
Board tests
1. I2c check
a. It doesn't work when assemled with mcontr and 2 DCMs. b. Started from the beginning. Works. c. Checked i2c four read with 1 start. Works fine. d. Adding DCMs.
2. Check BRAM read/write.
3. Check DDR read/write.
Understanding how 353's mcontr works
02/28/08: 15:04 for mode=0 ( 8 - burst length)
TileX - number of (32x8) blocks Seq_par(or Param) - the last write block length - (Seq_par)x8 TileY - number of TileX All this starts from StartAddress
