Difference between revisions of "10359 FPGA Simulation"

Revision as of 08:12, 19 March 2008

The main page for the board is 10359.

10359 work journal.

2008/03/18

1. Initialize/Write/Read DDR @96MHz

2008/03/18

1. make i2c work @96MHz

There's a suspicion it works unstable, so TODO is:
a. read an internal counter
b. write/read BRAM - done

All's fine. Next Step - Initialize/Write/Read DDR @96MHz. This was unstable because of the need to adjust phase.

2. make the image look like as if data doesn't go through DDR. There're small differences.

All's good
Reg Address: 0x0835 
Data:
bits[4:0]=00001 - channel1 -> DDR -> 359 -> 353
bits[4:0]=00010 - channel2 -> DDR -> 359 -> 353
bits[4:0]=00100 - channel3 -> DDR -> 359 -> 353
bits[4:0]=01001 - counter (accompanied with syncs from sensor1) -> DDR -> 359 -> 353
bits[4]=1       - counter (accompanied with syncs from sensor1) -> 353

2008/03/17

1. Put all FFs to negedge.And verify it. - done

2. Make i2c channels switching work fine - it's ok? but ->

3. i2c first work @96MHz

2008/03/13

TODO:

1. Mistakes during reads?! Check read and write addresses.

!!!! FORGOT TO INITIALIZE CHANNEL 2 !!!!

This chain works fine now:

"sensor -> channel's 0 buffer -> DDR -> channel's 2 line buffer -> to 353"

2008/03/12

1. DDR channel 3 has no problems @48MHz

2. DCM stops working after first try to get the image. It needs to be reseted.

(Address:0x810, Data:0x00000001)
(Address:0x810, Data:0x00000000)

3. Simulation model works fine: the stream from "the 3rd" sensor is written line by line to DDR and is read back (line by line as well).

4. The board doesn't work properly (behaviour is different from the simulation model's ).

a. data written to buf0 is ok
b. data read from buf2 is not.

2008/02/20

1. I2c check

a. It doesn't work when assemled with mcontr and 2 DCMs.
b. Started from the beginning. Works.
c. Checked i2c four read with 1 start. Works fine.
d. Adding DCMs.

2. Check BRAM read/write. All's fine

3. Check DDR read/write. Some problems. not solved All's fine now

4. Three different boards operate identically: BRAM - ok, DDR - not

       a. not marked 359
          acquired data is 0x05020306
          acquired data is 0x05060706
          acquired data is 0x090a0b16
          acquired data is 0x0d0e1f16
          acquired data is 0x11121316
          acquired data is 0x15161716
          acquired data is 0x191a1b06
          acquired data is 0x1d1e0f26
          acquired data is 0x21222326
          acquired data is 0x25262726
          acquired data is 0x292a2b36
          acquired data is 0x2d2e3f36
          acquired data is 0x31323336
          acquired data is 0x35363736
          acquired data is 0x393a3b26
          acquired data is 0x3d3e2f46

       b. yellow circle marked 359
          acquired data is 0x01020306
          acquired data is 0x05060706
          acquired data is 0x090a0b16
          acquired data is 0x0d0e1f16
          acquired data is 0x11121316
          acquired data is 0x15161716
          acquired data is 0x191a1b06
          acquired data is 0x1d1e0f26
          acquired data is 0x21222326
          acquired data is 0x25262726
          acquired data is 0x292a2b36
          acquired data is 0x2d2e3f36
          acquired data is 0x31323336
          acquired data is 0x35363736
          acquired data is 0x393a3b26
          acquired data is 0x3d3e2f46

Channel 3 (test channel) now works fine. And DDR is ok now.

2008/02/20. Understanding how 353's mcontr works

02/28/08: 15:04 for mode=0 ( 8 - burst length)

TileX - number of (32x8) blocks
Seq_par(or Param) - the last write block length - (Seq_par)x8
TileY - number of TileX
All this starts from StartAddress

2008/02/14

1. Channel 3 simulation:

• DDR initialization through i2c - done.
• write to DDR - done.
• read from DDR - done.

2. PHASE_SHIFT in DCM is not available currently, because the model had bad constructs, but SDCLK(SDNCLK) can be controlled by "phsel".

For correct writing/reading from DDR in model set phsel="01" (register=0x1008, value=0x00000004).