Difference between revisions of "Talk:10359"

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01. Apply clock to 10359
 
01. Apply clock to 10359
  
−
02. '''fpcf -i2cw16 806 100''' - switch i2c bus to EEPROM & CY22393
+
02. '''fpcf -i2cw16 807 1''' - switch i2c bus to EEPROM & CY22393
  
 
03. '''fpcf -X 4 96''' - switch internal 96MHz on the 10359
 
03. '''fpcf -X 4 96''' - switch internal 96MHz on the 10359
  
−
04. '''fpcf -i2cw16 806 1''' - switch i2c bus back to sensors
+
04. '''fpcf -i2cw16 808 1''' - switch from the 10353's clock to the 10359's generated clock
  
−
05. '''fpcf -i2cw16 807 1''' - switch from the 10353's clock to the 10359's generated clock
+
05. '''fpcf -i2cw16 801 3''' - reset system clock DCM
  
−
06. '''fpcf -i2cw16 801 3''' - reset system clock DCM
+
06. '''fpcf -i2cw16 802 3''' - reset SDRAM clock DCM
  
−
07. '''fpcf -i2cw16 802 3''' - reset SDRAM clock DCM
+
07. '''fpcf -i2cw16 803 3''' - reset J2 DCM
  
−
08. '''fpcf -i2cw16 803 3''' - reset J2 DCM
+
08. '''fpcf -i2cw16 804 3''' - reset J3 DCM
  
−
09. '''fpcf -i2cw16 804 3''' - reset J3 DCM
+
09. '''fpcf -i2cw16 805 3''' - reset J4 DCM
  
−
10. '''fpcf -i2cw16 805 3''' - reset J4 DCM
+
10. '''fpcf -i2cw16 807 0''' - switch i2c bus back to sensors
 +
 
 +
===SDRAM initialization sequence===
 +
for SDRAM clock phase - see reg '''0x802'''
 +
 
 +
i2c_send(0x850,0x0001); i2c_send(0x840,0x5555); // Disable DDR SDRAM read/write channels
 +
i2c_send(0x850,0x0001); i2c_send(0x841,0x7fff); // PRE : Addr[10] = 1, Bank = 11
 +
i2c_send(0x850,0x0000); i2c_send(0x841,0x2002); // Extended mode register - Enable DLL
 +
i2c_send(0x850,0x0000); i2c_send(0x841,0x0163); // Load Mode Register - Burst Length - 8, CAS latency - 2.5
 +
i2c_send(0x850,0x0000); i2c_send(0x841,0x8000); // Refresh
 +
i2c_send(0x850,0x0000); i2c_send(0x841,0x8000); // Refresh
 +
i2c_send(0x850,0x0001); i2c_send(0x841,0x7fff); // PRE : Addr[10] = 1, Bank = 11
 +
i2c_send(0x850,0x0001); i2c_send(0x840,0x0000); // Init auto refresh
 +
i2c_send(0x850,0x0000); i2c_send(0x840,0x5555); // Disable DDR SDRAM read/write channels
 +
i2c_send(0x850,0x0002); i2c_send(0x840,0x0000); // Enable auto refresh
 +
 
 +
===Write registers===
 +
All the registers are 16 bit wide
 +
{| border="1" cellpadding="2"
 +
| Address
 +
| Bits/Values
 +
| Description
 +
|-
 +
| 0x801
 +
|
 +
0x01 - "+"
 +
 
 +
0x02 - "-"
 +
 
 +
0x03 - reset small steps
 +
 
 +
0x04 - "+90"
 +
 
 +
0x08 - "-90"
 +
 
 +
0x0c - reset quarter
 +
 
 +
| system clock DCM
 +
 
 +
|-
 +
| 0x802
 +
|
 +
0x01 - "+"
 +
 
 +
0x02 - "-"
 +
 
 +
0x03 - reset small steps
 +
 
 +
0x04 - "+90"
 +
 
 +
0x08 - "-90"
 +
 
 +
0x0c - reset quarter
 +
| SDRAM clock DCM
 +
 
 +
|-
 +
| 0x803
 +
|
 +
0x01 - "+"
 +
 
 +
0x02 - "-"
 +
 
 +
0x03 - reset small steps
 +
 
 +
0x04 - "+90"
 +
 
 +
0x08 - "-90"
 +
 
 +
0x0c - reset quarter
 +
 
 +
0x10,0x20 - add hact-data shift
 +
 
 +
0x30 - reset hact-data shift
 +
| ch0 receive clock DCM
 +
 
 +
|-
 +
| 0x804
 +
|
 +
0x01 - "+"
 +
 
 +
0x02 - "-"
 +
 
 +
0x03 - reset small steps
 +
 
 +
0x04 - "+90"
 +
 
 +
0x08 - "-90"
 +
 
 +
0x0c - reset quarter
 +
 
 +
0x10,0x20 - add hact-data shift
 +
 
 +
0x30 - reset hact-data shift
 +
| ch1 receive clock DCM
 +
 
 +
|-
 +
| 0x805
 +
|
 +
0x01 - "+"
 +
 
 +
0x02 - "-"
 +
 
 +
0x03 - reset small steps
 +
 
 +
0x04 - "+90"
 +
 
 +
0x08 - "-90"
 +
 
 +
0x0c - reset quarter
 +
 
 +
0x10,0x20 - add hact-data shift
 +
 
 +
0x30 - reset hact-data shift
 +
| ch2 receive clock DCM
 +
 
 +
|-
 +
| 0x806
 +
|
 +
[5:4] - 2nd buffered channel, 0x0 - disabled?, 0x1 - J2, 0x2 - J3, 0x3 - J4
 +
 
 +
[3:2] - 1st buffered channel, 0x0 - disabled?, 0x1 - J2, 0x2 - J3, 0x3 - J4
 +
 
 +
[1:0] - direct channel, 0x0 - disabled?, 0x1 - J2, 0x2 - J3, 0x3 - J4
 +
| switch direct channel / channels order
 +
 
 +
|-
 +
| 0x807
 +
|
 +
[0] - i2c bus select, 0 - sensors, 1 - CY22393 & EEPROM
 +
| i2c bus select
 +
 
 +
|-
 +
| 0x808
 +
|
 +
[0] - 10359 sensors clock source, 0 - from 10353, 1 - onboard generator CY22393
 +
| system clock source
 +
 
 +
 
 +
|-
 +
| 0x809
 +
|
 +
[5] - test pattern from the 10359 to 10353
 +
 
 +
[4] - '0' - combine into one frame (one vact for all), '1' - separate frames
 +
 
 +
[3] - '1' - J4 frame, '0' - J3 frame - is buffered with mcontr channels 2-3
 +
 
 +
[2] - combined frames mode
 +
 
 +
[1] - output disable
 +
 
 +
[0] - global reset
 +
| Mode register
 +
 
 +
|-
 +
| 0x80a
 +
| default value: 0xa24 (2596)
 +
| regenerated Hact width (affects all input modules). Is used when hact_regen[i]=1 (hact regeneration mode for corresponding sensor), where i=0..2
 +
 
 +
|-
 +
| 0x80c
 +
| default value: 0x0
 +
| delay between frames in alternation mode.
 +
 
 +
|-
 +
| 0x80d
 +
|
 +
[1] - '1' - delays Hact of the 3rd frame in combined mode by 1 clock
 +
 
 +
[0] - '1' - delays Hact of the 2nd frame in combined mode by 1 clock
 +
| delay hacts by 1 clock
 +
 
 +
 
 +
|-
 +
| 0x80e
 +
| default value: 0x0 (is set by 10353 to 0x7)
 +
|
 +
[2] - '0' - use 3rd(J4) sensor's hact, '1' - regenerate hact, reg 0x80a value is used
 +
 
 +
[1] - '0' - use 2nd(J3) sensor's hact, '1' - regenerate hact, reg 0x80a value is used
 +
 
 +
[0] - '0' - use 1st(J2) sensor's hact, '1' - regenerate hact, reg 0x80a value is used
 +
 
 +
|-
 +
| 0x813
 +
| default value:2596
 +
| x size for read mcontr channel 1 (2nd frame)
 +
 
 +
|-
 +
| 0x814
 +
| default value:1940
 +
| y size for read mcontr channel 1 (2nd frame)
 +
 
 +
|-
 +
| 0x815
 +
| default value:256
 +
| pause between the lines for frame from channel 1 (2nd frame)
 +
 
 +
|-
 +
| 0x816
 +
| default value:0
 +
| number of blank lines before the channel 1 frame (2nd frame)
 +
 
 +
 
 +
|-
 +
| 0x823
 +
| default value:2596
 +
| x size for read mcontr channel 3 (3rd frame)
 +
 
 +
|-
 +
| 0x824
 +
| default value:1940
 +
| y size for read mcontr channel 3 (3rd frame)
 +
 
 +
|-
 +
| 0x825
 +
| default value:256
 +
| pause between the lines for frame from channel 3 (3rd frame)
 +
 
 +
|-
 +
| 0x826
 +
| default value:0
 +
| number of blank lines before the channel 3 frame (3rd frame)
 +
 
 +
|-
 +
| 0x850
 +
|
 +
| upper 16-bit part for 0x84X mcontr registers
 +
|}
 +
 
 +
====Mcontr write registers====
 +
for the high 16 bits reg 0x850 is used. All the regs considered to be 32 bit wide.
 +
 
 +
even numbered channels - SDRAM write channels: ch0, ch2
 +
 
 +
odd numbered channels  - SDRAM  read channels: ch1, ch3
 +
 
 +
{| border="1" cellpadding="2"
 +
| Address
 +
| Bits/Values
 +
| Description
 +
 
 +
|-
 +
| 0x840
 +
|
 +
[17:16], [2n+1:2n], n=0..7
 +
 
 +
0x0  - pause,
 +
 
 +
0x1  - init,
 +
 
 +
0x2  - enable
 +
| mcontr channels enable register
 +
 
 +
|-
 +
| 0x841
 +
|
 +
| direct commands to SDRAM interface (values appear on the address and control buses), used for memory initialization
 +
 
 +
|-
 +
| 0x844
 +
|
 +
| ch0 start address, 12-bit SDRAM page
 +
 
 +
|-
 +
| 0x845
 +
|
 +
| ch1 start address, 12-bit SDRAM page
 +
 
 +
|-
 +
| 0x846
 +
|
 +
| ch2 start address, 12-bit SDRAM page
 +
 
 +
|-
 +
| 0x847
 +
|
 +
| ch3 start address, 12-bit SDRAM page
 +
 
 +
|-
 +
| 0x84c
 +
|
 +
[31:16] - number of writes before another type of shift
 +
 
 +
[15: 8] - address shift after burst
 +
 
 +
[ 7: 0] - number of 8-word bursts in one write
 +
| ch0,ch1 tile size register, part1
 +
 
 +
|-
 +
| 0x84e
 +
| [29:16] - the last SDRAM page address for current channel
 +
| ch0,ch1 tile size register, part2
 +
 
 +
|-
 +
| 0x84d
 +
|
 +
[31:16] - number of writes before another type of shift
 +
 
 +
[15: 8] - address shift after burst
 +
 
 +
[ 7: 0] - number of 8-word bursts in one write
 +
| ch2,ch3 tile size register, part1
 +
 
 +
|-
 +
| 0x84f
 +
|
 +
[29:16] - the last SDRAM page address for current channel
 +
| ch2,ch3 tile size register, part2
 +
|}
 +
 
 +
====DDR SDRAM test write registers====
 +
Phase adjust register - 0x802
 +
 
 +
1 page = 64 words
 +
 
 +
Channels buffers sizes:
 +
 
 +
write channel - 2048 words
 +
 
 +
read channel  - 1024 words
 +
 
 +
=====Test channels reinitialization sequence=====
 +
 
 +
autorefresh:          0x850 bits[ 1: 0]
 +
 
 +
test write channel 4: 0x840 bits[ 9: 8]
 +
 
 +
test  read channel 5: 0x840 bits[11:10]
 +
 
 +
i2c_send(0x850,0x0001); i2c_send(0x840,0x0500);
 +
i2c_send(0x850,0x0002); i2c_send(0x840,0x0a00);
 +
 
 +
to check:
 +
 
 +
'''fpcf -i2cr16 841''' - [15:8] - number of page_read commands, [7:0] number of page_write commands
 +
 
 +
'''fpcf -i2cr16 845''' - write buffer current address
 +
 
 +
'''fpcf -i2cr16 846''' - read buffer current address
 +
 
 +
=====Registers=====
 +
{|  border="1" cellpadding="2"
 +
| 0x863
 +
|
 +
[15:0] - any value - page(64 words) write
 +
| page write
 +
|-
 +
 
 +
| 0x864
 +
|
 +
[15:0] - any value - page(64 words) read
 +
| page read
 +
|-
 +
 
 +
 
 +
| 0x870
 +
|
 +
[15:0] - data
 +
| Write/Read word
 +
|}
 +
 
 +
 
 +
====Combined frame mode enable sequence====
 +
i2c_send(16,0,0x809,2,0); // disable output
 +
i2c_send(16,0,0x809,3,0); // disable output + reset to all regs
 +
 +
i2c_send(16,0,0x813,2596,0); // pixels in line  for read the 3rd frame from channel 1 from SDRAM
 +
i2c_send(16,0,0x814,1940,0); // number of lines for read the 3rd frame from channel 1 from SDRAM
 +
 +
i2c_send(16,0,0x823,2596,0); // pixels in line  for read the 2nd frame from channel 3 from SDRAM
 +
i2c_send(16,0,0x824,1940,0); // number of lines for read the 2nd frame from channel 3 from SDRAM
 +
 +
i2c_send(16,0,0x850,0x0001,0); i2c_send(16,0,0x840,0x5555,0); // init all mcontr channels
 +
 +
// SDRAM init sequence, not necessary
 +
i2c_send(16,0,0x850,0x0001,0); i2c_send(16,0,0x840,0x5555,0); // Disable DDR SDRAM read/write channels
 +
i2c_send(16,0,0x850,0x0001,0); i2c_send(16,0,0x841,0x7fff,0); // PRE : Addr[10] = 1, Bank = 11
 +
i2c_send(16,0,0x850,0x0000,0); i2c_send(16,0,0x841,0x2002,0); // Extended mode register - Enable DLL
 +
i2c_send(16,0,0x850,0x0000,0); i2c_send(16,0,0x841,0x0163,0); // Load Mode Register - Burst Length - 8, CAS latency - 2.5
 +
i2c_send(16,0,0x850,0x0000,0); i2c_send(16,0,0x841,0x8000,0); // Refresh
 +
i2c_send(16,0,0x850,0x0000,0); i2c_send(16,0,0x841,0x8000,0); // Refresh
 +
i2c_send(16,0,0x850,0x0001,0); i2c_send(16,0,0x841,0x7fff,0); // PRE : Addr[10] = 1, Bank = 11
 +
i2c_send(16,0,0x850,0x0001,0); i2c_send(16,0,0x840,0x0000,0); // Init auto refresh
 +
i2c_send(16,0,0x850,0x0000,0); i2c_send(16,0,0x840,0x5555,0); // Disable DDR SDRAM read/write channels
 +
i2c_send(16,0,0x850,0x0002,0); i2c_send(16,0,0x840,0x0000,0); // Enable auto refresh
 +
 +
i2c_send(16,0,0x850,0x0002); i2c_send(16,0,0x840,0xaaaa,0); // enable all mcontr channels
 +
 +
// mcontr channels configuration
 +
 +
i2c_send(16,0,0x850,0x000f,0); i2c_send(16,0,0x84c,0x020f,0); // parameters for write channel 0
 +
i2c_send(16,0,0x850,0x1fff,0); i2c_send(16,0,0x84e,0x10ff,0); // parameters for  read channel 1
 +
 +
i2c_send(16,0,0x850,0x000f,0); i2c_send(16,0,0x84d,0x020f,0); // parameters for write channel 2
 +
i2c_send(16,0,0x850,0x1fff,0); i2c_send(16,0,0x84f,0x10ff,0); // parameters for  read channel 3
 +
 +
i2c_send(16,0,0x850,0x1c00,0); i2c_send(16,0,0x843,0x0c21,0); // don't remember
 +
 +
i2c_send(16,0,0x850,0x0001,0); i2c_send(16,0,0x840,0x5555,0); // init to store channels parameters
 +
 +
i2c_send(16,0,0x850,0x0000,0); i2c_send(16,0,0x844,0x0000,0); // start address for channel 0?
 +
i2c_send(16,0,0x850,0x0000,0); i2c_send(16,0,0x845,0x0000,0); // start address for channel 1?
 +
 +
i2c_send(16,0,0x850,0x0001,0); i2c_send(16,0,0x846,0x0000,0); // start address for channel 2?
 +
i2c_send(16,0,0x850,0x0001,0); i2c_send(16,0,0x847,0x0000,0); // start address for channel 3?
 +
 +
i2c_send(16,0,0x850,0x0002,0); i2c_send(16,0,0x840,0xaaaa,0); // init to store channels parameters
 +
 +
i2c_send(16,0,0x809,3,0); // disable output + reset to all regs
 +
i2c_send(16,0,0x809,2,0); // disable output
 +
 +
i2c_send(16,0,0x815,0x0100,0); // set pause between lines for the 3rd frame
 +
i2c_send(16,0,0x816,0x0004,0); // set number of blank lines before the 3rd frame
 +
 +
i2c_send(16,0,0x825,0x0100,0); // set pause between lines for the 2nd frame
 +
i2c_send(16,0,0x826,0x0004,0); // set number of blank lines before the 2nd frame
 +
 +
i2c_send(16,0,0x850,0x0000,0); // program the high part of the delay between frames from different channels
 +
i2c_send(16,0,0x80c,0x0000,0); // set the delay between frames from different channels to 0
 +
 +
i2c_send(16,0,0x809,0x0004,0); // enable 'combined frame' mode

Latest revision as of 14:48, 8 November 2010

Sensors addresses

0x48 - broadcast
0x4a - J2
0x4c - J3
0x4e - J4

Initialization sequence

01. Apply clock to 10359

02. fpcf -i2cw16 807 1 - switch i2c bus to EEPROM & CY22393

03. fpcf -X 4 96 - switch internal 96MHz on the 10359

04. fpcf -i2cw16 808 1 - switch from the 10353's clock to the 10359's generated clock

05. fpcf -i2cw16 801 3 - reset system clock DCM

06. fpcf -i2cw16 802 3 - reset SDRAM clock DCM

07. fpcf -i2cw16 803 3 - reset J2 DCM

08. fpcf -i2cw16 804 3 - reset J3 DCM

09. fpcf -i2cw16 805 3 - reset J4 DCM

10. fpcf -i2cw16 807 0 - switch i2c bus back to sensors

SDRAM initialization sequence

for SDRAM clock phase - see reg 0x802 

i2c_send(0x850,0x0001); i2c_send(0x840,0x5555); // Disable DDR SDRAM read/write channels
i2c_send(0x850,0x0001); i2c_send(0x841,0x7fff); // PRE : Addr[10] = 1, Bank = 11
i2c_send(0x850,0x0000); i2c_send(0x841,0x2002); // Extended mode register - Enable DLL
i2c_send(0x850,0x0000); i2c_send(0x841,0x0163); // Load Mode Register - Burst Length - 8, CAS latency - 2.5
i2c_send(0x850,0x0000); i2c_send(0x841,0x8000); // Refresh
i2c_send(0x850,0x0000); i2c_send(0x841,0x8000); // Refresh
i2c_send(0x850,0x0001); i2c_send(0x841,0x7fff); // PRE : Addr[10] = 1, Bank = 11
i2c_send(0x850,0x0001); i2c_send(0x840,0x0000); // Init auto refresh
i2c_send(0x850,0x0000); i2c_send(0x840,0x5555); // Disable DDR SDRAM read/write channels
i2c_send(0x850,0x0002); i2c_send(0x840,0x0000); // Enable auto refresh

Write registers

All the registers are 16 bit wide

Address Bits/Values Description
0x801

0x01 - "+"

0x02 - "-"

0x03 - reset small steps

0x04 - "+90"

0x08 - "-90"

0x0c - reset quarter

system clock DCM
0x802

0x01 - "+"

0x02 - "-"

0x03 - reset small steps

0x04 - "+90"

0x08 - "-90"

0x0c - reset quarter

SDRAM clock DCM
0x803

0x01 - "+"

0x02 - "-"

0x03 - reset small steps

0x04 - "+90"

0x08 - "-90"

0x0c - reset quarter

0x10,0x20 - add hact-data shift

0x30 - reset hact-data shift

ch0 receive clock DCM
0x804

0x01 - "+"

0x02 - "-"

0x03 - reset small steps

0x04 - "+90"

0x08 - "-90"

0x0c - reset quarter

0x10,0x20 - add hact-data shift

0x30 - reset hact-data shift

ch1 receive clock DCM
0x805

0x01 - "+"

0x02 - "-"

0x03 - reset small steps

0x04 - "+90"

0x08 - "-90"

0x0c - reset quarter

0x10,0x20 - add hact-data shift

0x30 - reset hact-data shift

ch2 receive clock DCM
0x806

[5:4] - 2nd buffered channel, 0x0 - disabled?, 0x1 - J2, 0x2 - J3, 0x3 - J4

[3:2] - 1st buffered channel, 0x0 - disabled?, 0x1 - J2, 0x2 - J3, 0x3 - J4

[1:0] - direct channel, 0x0 - disabled?, 0x1 - J2, 0x2 - J3, 0x3 - J4

switch direct channel / channels order
0x807

[0] - i2c bus select, 0 - sensors, 1 - CY22393 & EEPROM

i2c bus select
0x808

[0] - 10359 sensors clock source, 0 - from 10353, 1 - onboard generator CY22393

system clock source


0x809

[5] - test pattern from the 10359 to 10353

[4] - '0' - combine into one frame (one vact for all), '1' - separate frames

[3] - '1' - J4 frame, '0' - J3 frame - is buffered with mcontr channels 2-3

[2] - combined frames mode

[1] - output disable

[0] - global reset

Mode register
0x80a default value: 0xa24 (2596) regenerated Hact width (affects all input modules). Is used when hact_regen[i]=1 (hact regeneration mode for corresponding sensor), where i=0..2
0x80c default value: 0x0 delay between frames in alternation mode.
0x80d

[1] - '1' - delays Hact of the 3rd frame in combined mode by 1 clock

[0] - '1' - delays Hact of the 2nd frame in combined mode by 1 clock

delay hacts by 1 clock


0x80e default value: 0x0 (is set by 10353 to 0x7)

[2] - '0' - use 3rd(J4) sensor's hact, '1' - regenerate hact, reg 0x80a value is used

[1] - '0' - use 2nd(J3) sensor's hact, '1' - regenerate hact, reg 0x80a value is used

[0] - '0' - use 1st(J2) sensor's hact, '1' - regenerate hact, reg 0x80a value is used

0x813 default value:2596 x size for read mcontr channel 1 (2nd frame)
0x814 default value:1940 y size for read mcontr channel 1 (2nd frame)
0x815 default value:256 pause between the lines for frame from channel 1 (2nd frame)
0x816 default value:0 number of blank lines before the channel 1 frame (2nd frame)


0x823 default value:2596 x size for read mcontr channel 3 (3rd frame)
0x824 default value:1940 y size for read mcontr channel 3 (3rd frame)
0x825 default value:256 pause between the lines for frame from channel 3 (3rd frame)
0x826 default value:0 number of blank lines before the channel 3 frame (3rd frame)
0x850 upper 16-bit part for 0x84X mcontr registers

Mcontr write registers

for the high 16 bits reg 0x850 is used. All the regs considered to be 32 bit wide.

even numbered channels - SDRAM write channels: ch0, ch2

odd numbered channels - SDRAM read channels: ch1, ch3

Address Bits/Values Description
0x840

[17:16], [2n+1:2n], n=0..7

0x0 - pause,

0x1 - init,

0x2 - enable

mcontr channels enable register
0x841 direct commands to SDRAM interface (values appear on the address and control buses), used for memory initialization
0x844 ch0 start address, 12-bit SDRAM page
0x845 ch1 start address, 12-bit SDRAM page
0x846 ch2 start address, 12-bit SDRAM page
0x847 ch3 start address, 12-bit SDRAM page
0x84c

[31:16] - number of writes before another type of shift

[15: 8] - address shift after burst

[ 7: 0] - number of 8-word bursts in one write

ch0,ch1 tile size register, part1
0x84e [29:16] - the last SDRAM page address for current channel ch0,ch1 tile size register, part2
0x84d

[31:16] - number of writes before another type of shift

[15: 8] - address shift after burst

[ 7: 0] - number of 8-word bursts in one write

ch2,ch3 tile size register, part1
0x84f

[29:16] - the last SDRAM page address for current channel

ch2,ch3 tile size register, part2

DDR SDRAM test write registers

Phase adjust register - 0x802

1 page = 64 words

Channels buffers sizes:

write channel - 2048 words

read channel - 1024 words

Test channels reinitialization sequence

autorefresh: 0x850 bits[ 1: 0]

test write channel 4: 0x840 bits[ 9: 8]

test read channel 5: 0x840 bits[11:10] 

i2c_send(0x850,0x0001); i2c_send(0x840,0x0500);
i2c_send(0x850,0x0002); i2c_send(0x840,0x0a00);

to check:

fpcf -i2cr16 841 - [15:8] - number of page_read commands, [7:0] number of page_write commands

fpcf -i2cr16 845 - write buffer current address

fpcf -i2cr16 846 - read buffer current address

Registers
0x863

[15:0] - any value - page(64 words) write

page write
0x864

[15:0] - any value - page(64 words) read

page read
0x870

[15:0] - data

Write/Read word


Combined frame mode enable sequence

i2c_send(16,0,0x809,2,0); // disable output
i2c_send(16,0,0x809,3,0); // disable output + reset to all regs

i2c_send(16,0,0x813,2596,0); // pixels in line  for read the 3rd frame from channel 1 from SDRAM
i2c_send(16,0,0x814,1940,0); // number of lines for read the 3rd frame from channel 1 from SDRAM

i2c_send(16,0,0x823,2596,0); // pixels in line  for read the 2nd frame from channel 3 from SDRAM
i2c_send(16,0,0x824,1940,0); // number of lines for read the 2nd frame from channel 3 from SDRAM

i2c_send(16,0,0x850,0x0001,0); i2c_send(16,0,0x840,0x5555,0); // init all mcontr channels

// SDRAM init sequence, not necessary
i2c_send(16,0,0x850,0x0001,0); i2c_send(16,0,0x840,0x5555,0); // Disable DDR SDRAM read/write channels
i2c_send(16,0,0x850,0x0001,0); i2c_send(16,0,0x841,0x7fff,0); // PRE : Addr[10] = 1, Bank = 11
i2c_send(16,0,0x850,0x0000,0); i2c_send(16,0,0x841,0x2002,0); // Extended mode register - Enable DLL
i2c_send(16,0,0x850,0x0000,0); i2c_send(16,0,0x841,0x0163,0); // Load Mode Register - Burst Length - 8, CAS latency - 2.5
i2c_send(16,0,0x850,0x0000,0); i2c_send(16,0,0x841,0x8000,0); // Refresh
i2c_send(16,0,0x850,0x0000,0); i2c_send(16,0,0x841,0x8000,0); // Refresh
i2c_send(16,0,0x850,0x0001,0); i2c_send(16,0,0x841,0x7fff,0); // PRE : Addr[10] = 1, Bank = 11
i2c_send(16,0,0x850,0x0001,0); i2c_send(16,0,0x840,0x0000,0); // Init auto refresh
i2c_send(16,0,0x850,0x0000,0); i2c_send(16,0,0x840,0x5555,0); // Disable DDR SDRAM read/write channels
i2c_send(16,0,0x850,0x0002,0); i2c_send(16,0,0x840,0x0000,0); // Enable auto refresh

i2c_send(16,0,0x850,0x0002); i2c_send(16,0,0x840,0xaaaa,0); // enable all mcontr channels

// mcontr channels configuration

i2c_send(16,0,0x850,0x000f,0); i2c_send(16,0,0x84c,0x020f,0); // parameters for write channel 0
i2c_send(16,0,0x850,0x1fff,0); i2c_send(16,0,0x84e,0x10ff,0); // parameters for  read channel 1

i2c_send(16,0,0x850,0x000f,0); i2c_send(16,0,0x84d,0x020f,0); // parameters for write channel 2
i2c_send(16,0,0x850,0x1fff,0); i2c_send(16,0,0x84f,0x10ff,0); // parameters for  read channel 3

i2c_send(16,0,0x850,0x1c00,0); i2c_send(16,0,0x843,0x0c21,0); // don't remember

i2c_send(16,0,0x850,0x0001,0); i2c_send(16,0,0x840,0x5555,0); // init to store channels parameters

i2c_send(16,0,0x850,0x0000,0); i2c_send(16,0,0x844,0x0000,0); // start address for channel 0?
i2c_send(16,0,0x850,0x0000,0); i2c_send(16,0,0x845,0x0000,0); // start address for channel 1? 

i2c_send(16,0,0x850,0x0001,0); i2c_send(16,0,0x846,0x0000,0); // start address for channel 2?
i2c_send(16,0,0x850,0x0001,0); i2c_send(16,0,0x847,0x0000,0); // start address for channel 3?

i2c_send(16,0,0x850,0x0002,0); i2c_send(16,0,0x840,0xaaaa,0); // init to store channels parameters 

i2c_send(16,0,0x809,3,0); // disable output + reset to all regs
i2c_send(16,0,0x809,2,0); // disable output

i2c_send(16,0,0x815,0x0100,0); // set pause between lines for the 3rd frame
i2c_send(16,0,0x816,0x0004,0); // set number of blank lines before the 3rd frame

i2c_send(16,0,0x825,0x0100,0); // set pause between lines for the 2nd frame
i2c_send(16,0,0x826,0x0004,0); // set number of blank lines before the 2nd frame

i2c_send(16,0,0x850,0x0000,0); // program the high part of the delay between frames from different channels
i2c_send(16,0,0x80c,0x0000,0); // set the delay between frames from different channels to 0

i2c_send(16,0,0x809,0x0004,0); // enable 'combined frame' mode
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