Difference between revisions of "10359 FPGA Simulation"
From ElphelWiki
Okdzhimiev (talk | contribs) |
Okdzhimiev (talk | contribs) |
||
Line 10: | Line 10: | ||
For correct writing/reading from DDR in model set phsel="01" (register=0x1008, value=0x00000004). | For correct writing/reading from DDR in model set phsel="01" (register=0x1008, value=0x00000004). | ||
− | ==Board tests== | + | ==Board tests== |
1. I2c check | 1. I2c check | ||
a. It doesn't work when assemled with mcontr and 2 DCMs. | a. It doesn't work when assemled with mcontr and 2 DCMs. | ||
Line 22: | Line 22: | ||
4. Three different boards operate identically: BRAM - ok, DDR - not | 4. Three different boards operate identically: BRAM - ok, DDR - not | ||
+ | a. not marked 359 | ||
+ | acquired data is 0x05020306 | ||
+ | acquired data is 0x05060706 | ||
+ | acquired data is 0x090a0b16 | ||
+ | acquired data is 0x0d0e1f16 | ||
+ | acquired data is 0x11121316 | ||
+ | acquired data is 0x15161716 | ||
+ | acquired data is 0x191a1b06 | ||
+ | acquired data is 0x1d1e0f26 | ||
+ | acquired data is 0x21222326 | ||
+ | acquired data is 0x25262726 | ||
+ | acquired data is 0x292a2b36 | ||
+ | acquired data is 0x2d2e3f36 | ||
+ | acquired data is 0x31323336 | ||
+ | acquired data is 0x35363736 | ||
+ | acquired data is 0x393a3b26 | ||
+ | acquired data is 0x3d3e2f46 | ||
+ | |||
+ | b. yellow circle marked 359 | ||
+ | acquired data is 0xfbdfdbf6 | ||
+ | acquired data is 0xfe71bff6 | ||
+ | acquired data is 0xf7d57f76 | ||
+ | acquired data is 0x1d9bfde6 | ||
+ | acquired data is 0xffecefe6 | ||
+ | acquired data is 0xf7fc7de6 | ||
+ | acquired data is 0xbbb63fe6 | ||
+ | acquired data is 0xddd6def6 | ||
+ | acquired data is 0xbff37ba6 | ||
+ | acquired data is 0x3f7ffff6 | ||
+ | acquired data is 0xffbcbf76 | ||
+ | acquired data is 0xbfffff66 | ||
+ | acquired data is 0xfdfd79e6 | ||
+ | acquired data is 0x77ef39c6 | ||
+ | acquired data is 0xfffbbfd6 | ||
+ | acquired data is 0xbb8bfb96 | ||
==Understanding how 353's mcontr works== | ==Understanding how 353's mcontr works== |
Revision as of 13:59, 4 March 2008
The main page for the board is 10359.
Verification
1. Channel 3 simulation:
- DDR initialization through i2c - done.
- write to DDR - done.
- read from DDR - done.
2. PHASE_SHIFT in DCM is not available currently, because the model had bad constructs, but SDCLK(SDNCLK) can be controlled by "phsel".
For correct writing/reading from DDR in model set phsel="01" (register=0x1008, value=0x00000004).
==Board tests==
1. I2c check
a. It doesn't work when assemled with mcontr and 2 DCMs. b. Started from the beginning. Works. c. Checked i2c four read with 1 start. Works fine. d. Adding DCMs.
2. Check BRAM read/write. All's fine
3. Check DDR read/write. Some problems. not solved
4. Three different boards operate identically: BRAM - ok, DDR - not
a. not marked 359 acquired data is 0x05020306 acquired data is 0x05060706 acquired data is 0x090a0b16 acquired data is 0x0d0e1f16 acquired data is 0x11121316 acquired data is 0x15161716 acquired data is 0x191a1b06 acquired data is 0x1d1e0f26 acquired data is 0x21222326 acquired data is 0x25262726 acquired data is 0x292a2b36 acquired data is 0x2d2e3f36 acquired data is 0x31323336 acquired data is 0x35363736 acquired data is 0x393a3b26 acquired data is 0x3d3e2f46
b. yellow circle marked 359 acquired data is 0xfbdfdbf6 acquired data is 0xfe71bff6 acquired data is 0xf7d57f76 acquired data is 0x1d9bfde6 acquired data is 0xffecefe6 acquired data is 0xf7fc7de6 acquired data is 0xbbb63fe6 acquired data is 0xddd6def6 acquired data is 0xbff37ba6 acquired data is 0x3f7ffff6 acquired data is 0xffbcbf76 acquired data is 0xbfffff66 acquired data is 0xfdfd79e6 acquired data is 0x77ef39c6 acquired data is 0xfffbbfd6 acquired data is 0xbb8bfb96
Understanding how 353's mcontr works
02/28/08: 15:04 for mode=0 ( 8 - burst length)
TileX - number of (32x8) blocks Seq_par(or Param) - the last write block length - (Seq_par)x8 TileY - number of TileX All this starts from StartAddress