Difference between revisions of "Talk:10359"
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09. '''fpcf -i2cw16 805 3''' - reset J4 DCM | 09. '''fpcf -i2cw16 805 3''' - reset J4 DCM | ||
+ | |||
+ | ===Write registers=== | ||
+ | All the registers are 16 bit wide | ||
+ | {| border="1" cellpadding="2" | ||
+ | | Address | ||
+ | | Bits/Values | ||
+ | | Description | ||
+ | |- | ||
+ | | 0x801 | ||
+ | | | ||
+ | 0x01 - "+" | ||
+ | |||
+ | 0x02 - "-" | ||
+ | |||
+ | 0x03 - reset small steps | ||
+ | |||
+ | 0x04 - "+90" | ||
+ | |||
+ | 0x08 - "-90" | ||
+ | |||
+ | 0x0c - reset quarter | ||
+ | |||
+ | | system clock DCM | ||
+ | |||
+ | |- | ||
+ | | 0x802 | ||
+ | | | ||
+ | 0x01 - "+" | ||
+ | |||
+ | 0x02 - "-" | ||
+ | |||
+ | 0x03 - reset small steps | ||
+ | | SDRAM clock DCM | ||
+ | |||
+ | |- | ||
+ | | 0x803 | ||
+ | | | ||
+ | 0x01 - "+" | ||
+ | |||
+ | 0x02 - "-" | ||
+ | |||
+ | 0x03 - reset small steps | ||
+ | |||
+ | 0x04 - "+90" | ||
+ | |||
+ | 0x08 - "-90" | ||
+ | |||
+ | 0x0c - reset quarter | ||
+ | |||
+ | 0x10,0x20 - add hact-data shift | ||
+ | |||
+ | 0x30 - reset hact-data shift | ||
+ | | ch0 receive clock DCM | ||
+ | |||
+ | |- | ||
+ | | 0x804 | ||
+ | | | ||
+ | 0x01 - "+" | ||
+ | |||
+ | 0x02 - "-" | ||
+ | |||
+ | 0x03 - reset small steps | ||
+ | |||
+ | 0x04 - "+90" | ||
+ | |||
+ | 0x08 - "-90" | ||
+ | |||
+ | 0x0c - reset quarter | ||
+ | |||
+ | 0x10,0x20 - add hact-data shift | ||
+ | |||
+ | 0x30 - reset hact-data shift | ||
+ | | ch1 receive clock DCM | ||
+ | |||
+ | |- | ||
+ | | 0x805 | ||
+ | | | ||
+ | 0x01 - "+" | ||
+ | |||
+ | 0x02 - "-" | ||
+ | |||
+ | 0x03 - reset small steps | ||
+ | |||
+ | 0x04 - "+90" | ||
+ | |||
+ | 0x08 - "-90" | ||
+ | |||
+ | 0x0c - reset quarter | ||
+ | |||
+ | 0x10,0x20 - add hact-data shift | ||
+ | |||
+ | 0x30 - reset hact-data shift | ||
+ | | ch2 receive clock DCM | ||
+ | |||
+ | |- | ||
+ | | 0x806 | ||
+ | | | ||
+ | [2] - enable J4 (ch2) | ||
+ | |||
+ | [1] - enable J3 (ch1) | ||
+ | |||
+ | [0] - enable J2 (ch0) | ||
+ | | switch direct channel | ||
+ | |||
+ | |- | ||
+ | | 0x807 | ||
+ | | | ||
+ | [1] - i2c bus select, 0 - sensors, 1 - CY22393 & EEPROM | ||
+ | |||
+ | [2] - 10359 sensors clock source, 0 - from 10353, 1 - onboard generator CY22393 | ||
+ | | system clock source / i2c bus select | ||
+ | |} |
Revision as of 14:08, 1 May 2010
Sensors addresses
0x48 - broadcast 0x4a - J2 0x4c - J3 0x4e - J4
Initialization sequence
01. Apply clock to 10359
02. fpcf -i2cw16 807 2 - switch i2c bus to EEPROM & CY22393
03. fpcf -X 4 96 - switch internal 96MHz on the 10359
04. fpcf -i2cw16 807 1 - switch from the 10353's clock to the 10359's generated clock
05. fpcf -i2cw16 801 3 - reset system clock DCM
06. fpcf -i2cw16 802 3 - reset SDRAM clock DCM
07. fpcf -i2cw16 803 3 - reset J2 DCM
08. fpcf -i2cw16 804 3 - reset J3 DCM
09. fpcf -i2cw16 805 3 - reset J4 DCM
Write registers
All the registers are 16 bit wide
Address | Bits/Values | Description |
0x801 |
0x01 - "+" 0x02 - "-" 0x03 - reset small steps 0x04 - "+90" 0x08 - "-90" 0x0c - reset quarter |
system clock DCM |
0x802 |
0x01 - "+" 0x02 - "-" 0x03 - reset small steps |
SDRAM clock DCM |
0x803 |
0x01 - "+" 0x02 - "-" 0x03 - reset small steps 0x04 - "+90" 0x08 - "-90" 0x0c - reset quarter 0x10,0x20 - add hact-data shift 0x30 - reset hact-data shift |
ch0 receive clock DCM |
0x804 |
0x01 - "+" 0x02 - "-" 0x03 - reset small steps 0x04 - "+90" 0x08 - "-90" 0x0c - reset quarter 0x10,0x20 - add hact-data shift 0x30 - reset hact-data shift |
ch1 receive clock DCM |
0x805 |
0x01 - "+" 0x02 - "-" 0x03 - reset small steps 0x04 - "+90" 0x08 - "-90" 0x0c - reset quarter 0x10,0x20 - add hact-data shift 0x30 - reset hact-data shift |
ch2 receive clock DCM |
0x806 |
[2] - enable J4 (ch2) [1] - enable J3 (ch1) [0] - enable J2 (ch0) |
switch direct channel |
0x807 |
[1] - i2c bus select, 0 - sensors, 1 - CY22393 & EEPROM [2] - 10359 sensors clock source, 0 - from 10353, 1 - onboard generator CY22393 |
system clock source / i2c bus select |