Difference between revisions of "10359 FPGA Simulation"
| Line 3: | Line 3: | ||
[[10359 work journal]]. | [[10359 work journal]]. | ||
| − | == | + | ==2008/02/14== |
1. Channel 3 simulation: | 1. Channel 3 simulation: | ||
* DDR initialization through i2c - done. | * DDR initialization through i2c - done. | ||
| Line 12: | Line 12: | ||
For correct writing/reading from DDR in model set phsel="01" (register=0x1008, value=0x00000004). | For correct writing/reading from DDR in model set phsel="01" (register=0x1008, value=0x00000004). | ||
| − | + | ==2008/02/20== | |
1. I2c check | 1. I2c check | ||
a. It doesn't work when assemled with mcontr and 2 DCMs. | a. It doesn't work when assemled with mcontr and 2 DCMs. | ||
| Line 63: | Line 63: | ||
Channel 3 (test channel) now works fine. And DDR is ok now. | Channel 3 (test channel) now works fine. And DDR is ok now. | ||
| − | ==Understanding how 353's mcontr works== | + | ==2008/02/20. Understanding how 353's mcontr works== |
02/28/08: | 02/28/08: | ||
15:04 | 15:04 | ||
| Line 71: | Line 71: | ||
TileY - number of TileX | TileY - number of TileX | ||
All this starts from StartAddress | All this starts from StartAddress | ||
| + | |||
| + | ==2008/03/12== | ||
| + | 1. DDR channel 3 has no problems @48MHz | ||
| + | 2. DCM stops working after first try to get the image. It needs to be reseted. | ||
| + | (Address:0x810, Data:0x00000001) | ||
| + | (Address:0x810, Data:0x00000000) | ||
| + | 3. Simulation model works fine: the stream from "the 3rd" sensor is written line by line to DDR and is read back (line by line as well). | ||
| + | 4. The board doesn't work properly (behaviour is different to the simulation model's ). | ||
Revision as of 10:54, 12 March 2008
The main page for the board is 10359.
2008/02/14
1. Channel 3 simulation:
- DDR initialization through i2c - done.
- write to DDR - done.
- read from DDR - done.
2. PHASE_SHIFT in DCM is not available currently, because the model had bad constructs, but SDCLK(SDNCLK) can be controlled by "phsel".
For correct writing/reading from DDR in model set phsel="01" (register=0x1008, value=0x00000004).
2008/02/20
1. I2c check
a. It doesn't work when assemled with mcontr and 2 DCMs. b. Started from the beginning. Works. c. Checked i2c four read with 1 start. Works fine. d. Adding DCMs.
2. Check BRAM read/write. All's fine
3. Check DDR read/write. Some problems. not solved All's fine now
4. Three different boards operate identically: BRAM - ok, DDR - not
a. not marked 359
acquired data is 0x05020306
acquired data is 0x05060706
acquired data is 0x090a0b16
acquired data is 0x0d0e1f16
acquired data is 0x11121316
acquired data is 0x15161716
acquired data is 0x191a1b06
acquired data is 0x1d1e0f26
acquired data is 0x21222326
acquired data is 0x25262726
acquired data is 0x292a2b36
acquired data is 0x2d2e3f36
acquired data is 0x31323336
acquired data is 0x35363736
acquired data is 0x393a3b26
acquired data is 0x3d3e2f46
b. yellow circle marked 359
acquired data is 0x01020306
acquired data is 0x05060706
acquired data is 0x090a0b16
acquired data is 0x0d0e1f16
acquired data is 0x11121316
acquired data is 0x15161716
acquired data is 0x191a1b06
acquired data is 0x1d1e0f26
acquired data is 0x21222326
acquired data is 0x25262726
acquired data is 0x292a2b36
acquired data is 0x2d2e3f36
acquired data is 0x31323336
acquired data is 0x35363736
acquired data is 0x393a3b26
acquired data is 0x3d3e2f46
Channel 3 (test channel) now works fine. And DDR is ok now.
2008/02/20. Understanding how 353's mcontr works
02/28/08: 15:04 for mode=0 ( 8 - burst length)
TileX - number of (32x8) blocks Seq_par(or Param) - the last write block length - (Seq_par)x8 TileY - number of TileX All this starts from StartAddress
2008/03/12
1. DDR channel 3 has no problems @48MHz 2. DCM stops working after first try to get the image. It needs to be reseted.
(Address:0x810, Data:0x00000001) (Address:0x810, Data:0x00000000)
3. Simulation model works fine: the stream from "the 3rd" sensor is written line by line to DDR and is read back (line by line as well). 4. The board doesn't work properly (behaviour is different to the simulation model's ).
