Difference between revisions of "Talk:10359"
| Line 173: | Line 173: | ||
read channel - 1024 words | read channel - 1024 words | ||
| − | reinitialization sequence: | + | =====Test channels reinitialization sequence===== |
| + | |||
| + | autorefresh: 0x850 bits[ 1: 0] | ||
| − | |||
test write channel 4: 0x840 bits[ 9: 8] | test write channel 4: 0x840 bits[ 9: 8] | ||
| + | |||
test read channel 5: 0x840 bits[11:10] | test read channel 5: 0x840 bits[11:10] | ||
| Line 182: | Line 184: | ||
i2c_send(0x850,0x0002); i2c_send(0x840,0x0a00); | i2c_send(0x850,0x0002); i2c_send(0x840,0x0a00); | ||
| + | =====Registers===== | ||
{| border="1" cellpadding="2" | {| border="1" cellpadding="2" | ||
| 0x863 | | 0x863 | ||
Revision as of 09:30, 4 May 2010
Contents
Sensors addresses
0x48 - broadcast 0x4a - J2 0x4c - J3 0x4e - J4
Initialization sequence
01. Apply clock to 10359
02. fpcf -i2cw16 807 1 - switch i2c bus to EEPROM & CY22393
03. fpcf -X 4 96 - switch internal 96MHz on the 10359
04. fpcf -i2cw16 808 1 - switch from the 10353's clock to the 10359's generated clock
05. fpcf -i2cw16 801 3 - reset system clock DCM
06. fpcf -i2cw16 802 3 - reset SDRAM clock DCM
07. fpcf -i2cw16 803 3 - reset J2 DCM
08. fpcf -i2cw16 804 3 - reset J3 DCM
09. fpcf -i2cw16 805 3 - reset J4 DCM
10. fpcf -i2cw16 807 0 - switch i2c bus back to sensors
SDRAM initialization sequence
for SDRAM clock phase - see reg 0x802
i2c_send(0x850,0x0001); i2c_send(0x840,0x5555); // Disable DDR SDRAM read/write channels i2c_send(0x851,0x0001); i2c_send(0x841,0x7fff); // PRE : Addr[10] = 1, Bank = 11 i2c_send(0x851,0x0000); i2c_send(0x841,0x2002); // Extended mode register - Enable DLL i2c_send(0x851,0x0000); i2c_send(0x841,0x0163); // Load Mode Register - Burst Length - 8, CAS latency - 2.5 i2c_send(0x851,0x0000); i2c_send(0x841,0x8000); // Refresh i2c_send(0x851,0x0000); i2c_send(0x841,0x8000); // Refresh i2c_send(0x851,0x0001); i2c_send(0x841,0x7fff); // PRE : Addr[10] = 1, Bank = 11 i2c_send(0x850,0x0001); i2c_send(0x840,0x0000); // Init auto refresh i2c_send(0x850,0x0000); i2c_send(0x840,0x5555); // Disable DDR SDRAM read/write channels i2c_send(0x850,0x0002); i2c_send(0x840,0x0000); // Enable auto refresh
Write registers
All the registers are 16 bit wide
| Address | Bits/Values | Description |
| 0x801 |
0x01 - "+" 0x02 - "-" 0x03 - reset small steps 0x04 - "+90" 0x08 - "-90" 0x0c - reset quarter |
system clock DCM |
| 0x802 |
0x01 - "+" 0x02 - "-" 0x03 - reset small steps 0x04 - "+90" 0x08 - "-90" 0x0c - reset quarter |
SDRAM clock DCM |
| 0x803 |
0x01 - "+" 0x02 - "-" 0x03 - reset small steps 0x04 - "+90" 0x08 - "-90" 0x0c - reset quarter 0x10,0x20 - add hact-data shift 0x30 - reset hact-data shift |
ch0 receive clock DCM |
| 0x804 |
0x01 - "+" 0x02 - "-" 0x03 - reset small steps 0x04 - "+90" 0x08 - "-90" 0x0c - reset quarter 0x10,0x20 - add hact-data shift 0x30 - reset hact-data shift |
ch1 receive clock DCM |
| 0x805 |
0x01 - "+" 0x02 - "-" 0x03 - reset small steps 0x04 - "+90" 0x08 - "-90" 0x0c - reset quarter 0x10,0x20 - add hact-data shift 0x30 - reset hact-data shift |
ch2 receive clock DCM |
| 0x806 |
[2] - enable J4 (ch2) [1] - enable J3 (ch1) [0] - enable J2 (ch0) |
switch direct channel |
| 0x807 |
[0] - i2c bus select, 0 - sensors, 1 - CY22393 & EEPROM |
i2c bus select |
| 0x808 |
[0] - 10359 sensors clock source, 0 - from 10353, 1 - onboard generator CY22393 |
system clock source |
DDR SDRAM test write registers
Phase adjust register - 0x802
1 page = 64 words
Channels buffers sizes:
write channel - 2048 words
read channel - 1024 words
Test channels reinitialization sequence
autorefresh: 0x850 bits[ 1: 0]
test write channel 4: 0x840 bits[ 9: 8]
test read channel 5: 0x840 bits[11:10]
i2c_send(0x850,0x0001); i2c_send(0x840,0x0500); i2c_send(0x850,0x0002); i2c_send(0x840,0x0a00);
Registers
| 0x863 |
[15:0] - any value - page(64 words) write |
page write |
| 0x864 |
[15:0] - any value - page(64 words) read |
page read |
| 0x870 |
[15:0] - data |
Write/Read word |
