Difference between revisions of "10359 FPGA Simulation"
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==Board tests== | ==Board tests== | ||
1. I2c check | 1. I2c check | ||
| − | a. It doesn't work when | + | a. It doesn't work when assemled with mcontr and 2 DCMs. |
b. Started from the beginning. Works. | b. Started from the beginning. Works. | ||
c. Checked i2c four read with 1 start. Works fine. | c. Checked i2c four read with 1 start. Works fine. | ||
Revision as of 14:59, 28 February 2008
The main page for the board is 10359.
Verification
1. Channel 3 simulation:
- DDR initialization through i2c - done.
- write to DDR - done.
- read from DDR - done.
2. PHASE_SHIFT in DCM is not available currently, because the model had bad constructs, but SDCLK(SDNCLK) can be controlled by "phsel".
For correct writing/reading from DDR in model set phsel="01" (register=0x1008, value=0x00000004).
Board tests
1. I2c check
a. It doesn't work when assemled with mcontr and 2 DCMs. b. Started from the beginning. Works. c. Checked i2c four read with 1 start. Works fine. d. Adding DCMs.
2. Check BRAM read/write.
3. Check DDR read/write.
