FPGA bitstream versions

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Updating 393 cameras FPGA bitstream versions after code modifications

Modifications to the SATA code

SATA controller subsystem source code is maintained in a x393_sata repository.

1. Edit py393sata/create_ahci_registers.py and modify RID value

2. Run create_ahci_registers.py

It will finish with lines similar to these:

AHCI register defaults are written to        /home/eyesis/git/elphel393/fpga-elphel/x393_sata/includes/ahci_defaults.vh
AHCI register bit field types are written to /home/eyesis/git/elphel393/fpga-elphel/x393_sata/includes/ahci_types.vh
AHCI localparam definitions are written to /home/eyesis/git/elphel393/fpga-elphel/x393_sata/includes/ahci_localparams.vh

3. Commit changes to the git repository

4. Copy SATA-related files (including new autogenerated ones) to x393 file tree by running

./copy_x393_sata.sh in the x393 folder. Relative path to SATA files is assumed to be ../x393sata - it is set up when installing all the software with   elphel393/setup.py

Modifications to the x393 code

FPGA version number is generated from the fpga_version.vh and it can be read in the camera at runtime as a 32-bit number. Version is stored as 0x0393VVVV, where VVVV is a 4-digit hex number (will try to keep it as 2 digits for major version/branch, and 2 lower for the incremented minor number).

  1. Increment the number
  2. Run implementation tools
  3. Verify timing ((now small errors are OK as the settings are for speed grade "-1", hardware is "-2")
  4. Copy result x393_parallel.bit from vivado_results to the root folder
  5. Verify bitsteram with the hardware
  6. Commit to git repository

Draft notes

Bitstream type?

  • In fpga-elphel/x393 x393_global.tcl:
    • checks if HISPI is enabled and make some kind of changes
  • status_read.v
    • writes fpga bitstream type