From ElphelWiki
Revision as of 13:03, 7 May 2008 by Oleg (talk | contribs)
Jump to: navigation, search


10359 is an optional multi-function board for Elplhel Model 353/363 Cameras. It can be connected between the 10353 Processor board and a sensor one (up to three sensor boards can be connected) This board has the same FPGA-DDR SDRAM pair as on the 10353 (Processor) board. It uses just one extra conductor in the flex cable to configure the on-board FPGA, rest of the JTAG programming interface pins share connections with the data signals. This board can fit in the standard camera enclosure (when only one sensor board is used) and does not interfere with the boards that use inter-board connectors (i.e. 10357) - the 10359 is mounted on the other side of the 10353 board.

10359 board can be used in the following applications (as well as other ones):

  • Additional custom image processing in the FPGA without the requirement to recompile the main FPGA on the 10353 board and solve possible conflicts with existent functionality.
  • multiplex several sensor boards (i.e. "day" - color and "night" - monochrome) to one 10353 camera board.
  • simultaneously acquire images from up to 3 sensors, compress them and send out one after another
  • extract 3-d information from multiple sensors in real time in FPGA
  • use additional sensor(s) to run correlation code (like in optical mice) to track camera orientation to compensate for the effect of Electronic_Rolling_Shutter
  • connect earlier sensor boards (with 3.3V interface) to the 10353 board. Interface voltage for the sensor boards can be switched from 2.5V to 3.3V (all 3 simultaneously)


  • 30-pin flex cable connector (J1) for data to/from the 10353 Processor board. It also receives 3.3V power through this connector
  • 3 of 30-pin flex cable connectors (J2, J3, J4) for the flex cables to the sensor boards (i.e. 10338, 10347)


Currently is available

1. Switching between 3 direct(w/o buffering in 10359 DDR) data streams from sensors. 2. Getting 2 frames from 2 sensors with programmed delay, one frame is being stored while the first is going directly through fpga.